18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci * 38c2ecf20Sopenharmony_ci * Copyright (C) 1999 by Kaz Kojima 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Defitions for the address spaces of the SH CPUs. 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci#ifndef __ASM_SH_ADDRSPACE_H 88c2ecf20Sopenharmony_ci#define __ASM_SH_ADDRSPACE_H 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#include <cpu/addrspace.h> 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci/* If this CPU supports segmentation, hook up the helpers */ 138c2ecf20Sopenharmony_ci#ifdef P1SEG 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci/* 168c2ecf20Sopenharmony_ci [ P0/U0 (virtual) ] 0x00000000 <------ User space 178c2ecf20Sopenharmony_ci [ P1 (fixed) cached ] 0x80000000 <------ Kernel space 188c2ecf20Sopenharmony_ci [ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access 198c2ecf20Sopenharmony_ci [ P3 (virtual) cached] 0xC0000000 <------ vmalloced area 208c2ecf20Sopenharmony_ci [ P4 control ] 0xE0000000 218c2ecf20Sopenharmony_ci */ 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci/* Returns the privileged segment base of a given address */ 248c2ecf20Sopenharmony_ci#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci#ifdef CONFIG_29BIT 278c2ecf20Sopenharmony_ci/* 288c2ecf20Sopenharmony_ci * Map an address to a certain privileged segment 298c2ecf20Sopenharmony_ci */ 308c2ecf20Sopenharmony_ci#define P1SEGADDR(a) \ 318c2ecf20Sopenharmony_ci ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) 328c2ecf20Sopenharmony_ci#define P2SEGADDR(a) \ 338c2ecf20Sopenharmony_ci ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) 348c2ecf20Sopenharmony_ci#define P3SEGADDR(a) \ 358c2ecf20Sopenharmony_ci ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) 368c2ecf20Sopenharmony_ci#define P4SEGADDR(a) \ 378c2ecf20Sopenharmony_ci ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) 388c2ecf20Sopenharmony_ci#else 398c2ecf20Sopenharmony_ci/* 408c2ecf20Sopenharmony_ci * These will never work in 32-bit, don't even bother. 418c2ecf20Sopenharmony_ci */ 428c2ecf20Sopenharmony_ci#define P1SEGADDR(a) ({ (void)(a); BUG(); NULL; }) 438c2ecf20Sopenharmony_ci#define P2SEGADDR(a) ({ (void)(a); BUG(); NULL; }) 448c2ecf20Sopenharmony_ci#define P3SEGADDR(a) ({ (void)(a); BUG(); NULL; }) 458c2ecf20Sopenharmony_ci#define P4SEGADDR(a) ({ (void)(a); BUG(); NULL; }) 468c2ecf20Sopenharmony_ci#endif 478c2ecf20Sopenharmony_ci#endif /* P1SEG */ 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci/* Check if an address can be reached in 29 bits */ 508c2ecf20Sopenharmony_ci#define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000) 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#ifdef CONFIG_SH_STORE_QUEUES 538c2ecf20Sopenharmony_ci/* 548c2ecf20Sopenharmony_ci * This is a special case for the SH-4 store queues, as pages for this 558c2ecf20Sopenharmony_ci * space still need to be faulted in before it's possible to flush the 568c2ecf20Sopenharmony_ci * store queue cache for writeout to the remapped region. 578c2ecf20Sopenharmony_ci */ 588c2ecf20Sopenharmony_ci#define P3_ADDR_MAX (P4SEG_STORE_QUE + 0x04000000) 598c2ecf20Sopenharmony_ci#else 608c2ecf20Sopenharmony_ci#define P3_ADDR_MAX P4SEG 618c2ecf20Sopenharmony_ci#endif 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci#endif /* __ASM_SH_ADDRSPACE_H */ 64