18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * sh7724 MMCIF loader 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * Copyright (C) 2010 Magnus Damm 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General Public 78c2ecf20Sopenharmony_ci * License. See the file "COPYING" in the main directory of this archive 88c2ecf20Sopenharmony_ci * for more details. 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#include <linux/mmc/sh_mmcif.h> 128c2ecf20Sopenharmony_ci#include <mach/romimage.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#define MMCIF_BASE (void __iomem *)0xa4ca0000 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#define MSTPCR2 0xa4150038 178c2ecf20Sopenharmony_ci#define PTWCR 0xa4050146 188c2ecf20Sopenharmony_ci#define PTXCR 0xa4050148 198c2ecf20Sopenharmony_ci#define PSELA 0xa405014e 208c2ecf20Sopenharmony_ci#define PSELE 0xa4050156 218c2ecf20Sopenharmony_ci#define HIZCRC 0xa405015c 228c2ecf20Sopenharmony_ci#define DRVCRA 0xa405018a 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_cienum { 258c2ecf20Sopenharmony_ci MMCIF_PROGRESS_ENTER, 268c2ecf20Sopenharmony_ci MMCIF_PROGRESS_INIT, 278c2ecf20Sopenharmony_ci MMCIF_PROGRESS_LOAD, 288c2ecf20Sopenharmony_ci MMCIF_PROGRESS_DONE 298c2ecf20Sopenharmony_ci}; 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci/* SH7724 specific MMCIF loader 328c2ecf20Sopenharmony_ci * 338c2ecf20Sopenharmony_ci * loads the romImage from an MMC card starting from block 512 348c2ecf20Sopenharmony_ci * use the following line to write the romImage to an MMC card 358c2ecf20Sopenharmony_ci * # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512 368c2ecf20Sopenharmony_ci */ 378c2ecf20Sopenharmony_ciasmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes) 388c2ecf20Sopenharmony_ci{ 398c2ecf20Sopenharmony_ci mmcif_update_progress(MMCIF_PROGRESS_ENTER); 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci /* enable clock to the MMCIF hardware block */ 428c2ecf20Sopenharmony_ci __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci /* setup pins D7-D0 */ 458c2ecf20Sopenharmony_ci __raw_writew(0x0000, PTWCR); 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci /* setup pins MMC_CLK, MMC_CMD */ 488c2ecf20Sopenharmony_ci __raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR); 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci /* select D3-D0 pin function */ 518c2ecf20Sopenharmony_ci __raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA); 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci /* select D7-D4 pin function */ 548c2ecf20Sopenharmony_ci __raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE); 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci /* disable Hi-Z for the MMC pins */ 578c2ecf20Sopenharmony_ci __raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC); 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ci /* high drive capability for MMC pins */ 608c2ecf20Sopenharmony_ci __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA); 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ci mmcif_update_progress(MMCIF_PROGRESS_INIT); 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_ci /* setup MMCIF hardware */ 658c2ecf20Sopenharmony_ci sh_mmcif_boot_init(MMCIF_BASE); 668c2ecf20Sopenharmony_ci 678c2ecf20Sopenharmony_ci mmcif_update_progress(MMCIF_PROGRESS_LOAD); 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_ci /* load kernel via MMCIF interface */ 708c2ecf20Sopenharmony_ci sh_mmcif_boot_do_read(MMCIF_BASE, 512, 718c2ecf20Sopenharmony_ci (no_bytes + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, 728c2ecf20Sopenharmony_ci buf); 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_ci /* disable clock to the MMCIF hardware block */ 758c2ecf20Sopenharmony_ci __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_ci mmcif_update_progress(MMCIF_PROGRESS_DONE); 788c2ecf20Sopenharmony_ci} 79