1// SPDX-License-Identifier: GPL-2.0 2/* 3 * linux/arch/sh/boards/magicpanel/setup.c 4 * 5 * Copyright (C) 2007 Markus Brunner, Mark Jonas 6 * 7 * Magic Panel Release 2 board setup 8 */ 9#include <linux/init.h> 10#include <linux/irq.h> 11#include <linux/platform_device.h> 12#include <linux/delay.h> 13#include <linux/gpio.h> 14#include <linux/regulator/fixed.h> 15#include <linux/regulator/machine.h> 16#include <linux/smsc911x.h> 17#include <linux/mtd/mtd.h> 18#include <linux/mtd/partitions.h> 19#include <linux/mtd/physmap.h> 20#include <linux/mtd/map.h> 21#include <linux/sh_intc.h> 22#include <mach/magicpanelr2.h> 23#include <asm/heartbeat.h> 24#include <cpu/sh7720.h> 25 26/* Dummy supplies, where voltage doesn't matter */ 27static struct regulator_consumer_supply dummy_supplies[] = { 28 REGULATOR_SUPPLY("vddvario", "smsc911x"), 29 REGULATOR_SUPPLY("vdd33a", "smsc911x"), 30}; 31 32#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) 33 34/* Wait until reset finished. Timeout is 100ms. */ 35static int __init ethernet_reset_finished(void) 36{ 37 int i; 38 39 if (LAN9115_READY) 40 return 1; 41 42 for (i = 0; i < 10; ++i) { 43 mdelay(10); 44 if (LAN9115_READY) 45 return 1; 46 } 47 48 return 0; 49} 50 51static void __init reset_ethernet(void) 52{ 53 /* PMDR: LAN_RESET=on */ 54 CLRBITS_OUTB(0x10, PORT_PMDR); 55 56 udelay(200); 57 58 /* PMDR: LAN_RESET=off */ 59 SETBITS_OUTB(0x10, PORT_PMDR); 60} 61 62static void __init setup_chip_select(void) 63{ 64 /* CS2: LAN (0x08000000 - 0x0bffffff) */ 65 /* no idle cycles, normal space, 8 bit data bus */ 66 __raw_writel(0x36db0400, CS2BCR); 67 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 68 __raw_writel(0x000003c0, CS2WCR); 69 70 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ 71 /* no idle cycles, normal space, 8 bit data bus */ 72 __raw_writel(0x00000200, CS4BCR); 73 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 74 __raw_writel(0x00100981, CS4WCR); 75 76 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ 77 /* no idle cycles, normal space, 8 bit data bus */ 78 __raw_writel(0x00000200, CS5ABCR); 79 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 80 __raw_writel(0x00100981, CS5AWCR); 81 82 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ 83 /* no idle cycles, normal space, 8 bit data bus */ 84 __raw_writel(0x00000200, CS5BBCR); 85 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 86 __raw_writel(0x00100981, CS5BWCR); 87 88 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ 89 /* no idle cycles, normal space, 8 bit data bus */ 90 __raw_writel(0x00000200, CS6ABCR); 91 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ 92 __raw_writel(0x001009C1, CS6AWCR); 93} 94 95static void __init setup_port_multiplexing(void) 96{ 97 /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); 98 * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); 99 */ 100 __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ 101 102 /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); 103 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); 104 */ 105 __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ 106 107 /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); 108 * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; 109 */ 110 __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ 111 112 /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); 113 * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); 114 */ 115 __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ 116 117 /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; 118 * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; 119 */ 120 __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ 121 122 /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; 123 * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); 124 */ 125 __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ 126 127 /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); 128 * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); 129 */ 130 __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ 131 132 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); 133 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; 134 */ 135 __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ 136 137 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; 138 * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; 139 */ 140 __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ 141 142 /* K7 (x); K6 (x); K5 (x); K4 (x); 143 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) 144 */ 145 __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ 146 147 /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; 148 * L3 TCK; L2 (x); L1 (x); L0 (x); 149 */ 150 __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ 151 152 /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); 153 * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); 154 * M1 CS5B(CAN3_CS); M0 GPI+(nc); 155 */ 156 __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ 157 158 /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, 159 * LAN_RESET=off, BUZZER=off, LCD_BL=off 160 */ 161#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 162 __raw_writeb(0x30, PORT_PMDR); 163#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 164 __raw_writeb(0xF0, PORT_PMDR); 165#else 166#error Unknown revision of PLATFORM_MP_R2 167#endif 168 169 /* P7 (x); P6 (x); P5 (x); 170 * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); 171 * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) 172 */ 173 __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ 174 __raw_writeb(0x10, PORT_PPDR); 175 176 /* R7 A25; R6 A24; R5 A23; R4 A22; 177 * R3 A21; R2 A20; R1 A19; R0 A0; 178 */ 179 gpio_request(GPIO_FN_A25, NULL); 180 gpio_request(GPIO_FN_A24, NULL); 181 gpio_request(GPIO_FN_A23, NULL); 182 gpio_request(GPIO_FN_A22, NULL); 183 gpio_request(GPIO_FN_A21, NULL); 184 gpio_request(GPIO_FN_A20, NULL); 185 gpio_request(GPIO_FN_A19, NULL); 186 gpio_request(GPIO_FN_A0, NULL); 187 188 /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); 189 * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; 190 */ 191 __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ 192 193 /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; 194 * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) 195 */ 196 __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ 197 198 /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); 199 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; 200 */ 201 __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ 202 203 /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); 204 * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); 205 */ 206 __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ 207} 208 209static void __init mpr2_setup(char **cmdline_p) 210{ 211 /* set Pin Select Register A: 212 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, 213 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND 214 */ 215 __raw_writew(0xAABC, PORT_PSELA); 216 /* set Pin Select Register B: 217 * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, 218 * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved 219 */ 220 __raw_writew(0x3C00, PORT_PSELB); 221 /* set Pin Select Register C: 222 * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved 223 */ 224 __raw_writew(0x0000, PORT_PSELC); 225 /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, 226 * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved 227 */ 228 __raw_writew(0x0000, PORT_PSELD); 229 /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ 230 __raw_writew(0x0101, PORT_UTRCTL); 231 /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ 232 __raw_writew(0xA5C0, PORT_UCLKCR_W); 233 234 setup_chip_select(); 235 236 setup_port_multiplexing(); 237 238 reset_ethernet(); 239 240 printk(KERN_INFO "Magic Panel Release 2 A.%i\n", 241 CONFIG_SH_MAGIC_PANEL_R2_VERSION); 242 243 if (ethernet_reset_finished() == 0) 244 printk(KERN_WARNING "Ethernet not ready\n"); 245} 246 247static struct resource smsc911x_resources[] = { 248 [0] = { 249 .start = 0xa8000000, 250 .end = 0xabffffff, 251 .flags = IORESOURCE_MEM, 252 }, 253 [1] = { 254 .start = evt2irq(0x660), 255 .end = evt2irq(0x660), 256 .flags = IORESOURCE_IRQ, 257 }, 258}; 259 260static struct smsc911x_platform_config smsc911x_config = { 261 .phy_interface = PHY_INTERFACE_MODE_MII, 262 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 263 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 264 .flags = SMSC911X_USE_32BIT, 265}; 266 267static struct platform_device smsc911x_device = { 268 .name = "smsc911x", 269 .id = -1, 270 .num_resources = ARRAY_SIZE(smsc911x_resources), 271 .resource = smsc911x_resources, 272 .dev = { 273 .platform_data = &smsc911x_config, 274 }, 275}; 276 277static struct resource heartbeat_resources[] = { 278 [0] = { 279 .start = PA_LED, 280 .end = PA_LED, 281 .flags = IORESOURCE_MEM, 282 }, 283}; 284 285static struct heartbeat_data heartbeat_data = { 286 .flags = HEARTBEAT_INVERTED, 287}; 288 289static struct platform_device heartbeat_device = { 290 .name = "heartbeat", 291 .id = -1, 292 .dev = { 293 .platform_data = &heartbeat_data, 294 }, 295 .num_resources = ARRAY_SIZE(heartbeat_resources), 296 .resource = heartbeat_resources, 297}; 298 299static struct mtd_partition mpr2_partitions[] = { 300 /* Reserved for bootloader, read-only */ 301 { 302 .name = "Bootloader", 303 .offset = 0x00000000UL, 304 .size = MPR2_MTD_BOOTLOADER_SIZE, 305 .mask_flags = MTD_WRITEABLE, 306 }, 307 /* Reserved for kernel image */ 308 { 309 .name = "Kernel", 310 .offset = MTDPART_OFS_NXTBLK, 311 .size = MPR2_MTD_KERNEL_SIZE, 312 }, 313 /* Rest is used for Flash FS */ 314 { 315 .name = "Flash_FS", 316 .offset = MTDPART_OFS_NXTBLK, 317 .size = MTDPART_SIZ_FULL, 318 } 319}; 320 321static struct physmap_flash_data flash_data = { 322 .parts = mpr2_partitions, 323 .nr_parts = ARRAY_SIZE(mpr2_partitions), 324 .width = 2, 325}; 326 327static struct resource flash_resource = { 328 .start = 0x00000000, 329 .end = 0x2000000UL, 330 .flags = IORESOURCE_MEM, 331}; 332 333static struct platform_device flash_device = { 334 .name = "physmap-flash", 335 .id = -1, 336 .resource = &flash_resource, 337 .num_resources = 1, 338 .dev = { 339 .platform_data = &flash_data, 340 }, 341}; 342 343/* 344 * Add all resources to the platform_device 345 */ 346 347static struct platform_device *mpr2_devices[] __initdata = { 348 &heartbeat_device, 349 &smsc911x_device, 350 &flash_device, 351}; 352 353 354static int __init mpr2_devices_setup(void) 355{ 356 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 357 358 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); 359} 360device_initcall(mpr2_devices_setup); 361 362/* 363 * Initialize IRQ setting 364 */ 365static void __init init_mpr2_IRQ(void) 366{ 367 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ 368 369 irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ 370 irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ 371 irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ 372 irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ 373 irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ 374 irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ 375 376 intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */ 377 intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */ 378 intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */ 379 intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */ 380} 381 382/* 383 * The Machine Vector 384 */ 385 386static struct sh_machine_vector mv_mpr2 __initmv = { 387 .mv_name = "mpr2", 388 .mv_setup = mpr2_setup, 389 .mv_init_irq = init_mpr2_IRQ, 390}; 391