1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6#ifndef _ASM_RISCV_PGTABLE_H 7#define _ASM_RISCV_PGTABLE_H 8 9#include <linux/mmzone.h> 10#include <linux/sizes.h> 11 12#include <asm/pgtable-bits.h> 13 14#ifndef CONFIG_MMU 15#define KERNEL_LINK_ADDR PAGE_OFFSET 16#else 17 18#define ADDRESS_SPACE_END (UL(-1)) 19 20#ifdef CONFIG_64BIT 21/* Leave 2GB for kernel and BPF at the end of the address space */ 22#define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 23#else 24#define KERNEL_LINK_ADDR PAGE_OFFSET 25#endif 26 27#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 28#define VMALLOC_END (PAGE_OFFSET - 1) 29#define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 30 31#define BPF_JIT_REGION_SIZE (SZ_128M) 32#ifdef CONFIG_64BIT 33/* KASLR should leave at least 128MB for BPF after the kernel */ 34#define BPF_JIT_REGION_START PFN_ALIGN((unsigned long)&_end) 35#define BPF_JIT_REGION_END (BPF_JIT_REGION_START + BPF_JIT_REGION_SIZE) 36#else 37#define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 38#define BPF_JIT_REGION_END (VMALLOC_END) 39#endif 40 41/* Modules always live before the kernel */ 42#ifdef CONFIG_64BIT 43#define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 44#define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 45#endif 46 47/* 48 * Roughly size the vmemmap space to be large enough to fit enough 49 * struct pages to map half the virtual address space. Then 50 * position vmemmap directly below the VMALLOC region. 51 */ 52#define VMEMMAP_SHIFT \ 53 (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 54#define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 55#define VMEMMAP_END (VMALLOC_START - 1) 56#define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 57 58/* 59 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 60 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 61 */ 62#define vmemmap ((struct page *)VMEMMAP_START) 63 64#define PCI_IO_SIZE SZ_16M 65#define PCI_IO_END VMEMMAP_START 66#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 67 68#define FIXADDR_TOP PCI_IO_START 69#ifdef CONFIG_64BIT 70#define FIXADDR_SIZE PMD_SIZE 71#else 72#define FIXADDR_SIZE PGDIR_SIZE 73#endif 74#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 75#endif 76 77#ifndef __ASSEMBLY__ 78 79/* Page Upper Directory not used in RISC-V */ 80#include <asm-generic/pgtable-nopud.h> 81#include <asm/page.h> 82#include <asm/tlbflush.h> 83#include <linux/mm_types.h> 84 85#ifdef CONFIG_64BIT 86#include <asm/pgtable-64.h> 87#else 88#include <asm/pgtable-32.h> 89#endif /* CONFIG_64BIT */ 90 91#ifdef CONFIG_MMU 92/* Number of entries in the page global directory */ 93#define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 94/* Number of entries in the page table */ 95#define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 96 97/* Number of PGD entries that a user-mode program can use */ 98#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 99 100/* Page protection bits */ 101#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 102 103#define PAGE_NONE __pgprot(_PAGE_PROT_NONE) 104#define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 105#define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 106#define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 107#define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 108#define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 109 _PAGE_EXEC | _PAGE_WRITE) 110 111#define PAGE_COPY PAGE_READ 112#define PAGE_COPY_EXEC PAGE_EXEC 113#define PAGE_COPY_READ_EXEC PAGE_READ_EXEC 114#define PAGE_SHARED PAGE_WRITE 115#define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 116 117#define _PAGE_KERNEL (_PAGE_READ \ 118 | _PAGE_WRITE \ 119 | _PAGE_PRESENT \ 120 | _PAGE_ACCESSED \ 121 | _PAGE_DIRTY) 122 123#define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 124#define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 125#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 126#define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 127 | _PAGE_EXEC) 128 129#define PAGE_TABLE __pgprot(_PAGE_TABLE) 130 131/* 132 * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't 133 * change the properties of memory regions. 134 */ 135#define _PAGE_IOREMAP _PAGE_KERNEL 136 137extern pgd_t swapper_pg_dir[]; 138 139/* MAP_PRIVATE permissions: xwr (copy-on-write) */ 140#define __P000 PAGE_NONE 141#define __P001 PAGE_READ 142#define __P010 PAGE_COPY 143#define __P011 PAGE_COPY 144#define __P100 PAGE_EXEC 145#define __P101 PAGE_READ_EXEC 146#define __P110 PAGE_COPY_EXEC 147#define __P111 PAGE_COPY_READ_EXEC 148 149/* MAP_SHARED permissions: xwr */ 150#define __S000 PAGE_NONE 151#define __S001 PAGE_READ 152#define __S010 PAGE_SHARED 153#define __S011 PAGE_SHARED 154#define __S100 PAGE_EXEC 155#define __S101 PAGE_READ_EXEC 156#define __S110 PAGE_SHARED_EXEC 157#define __S111 PAGE_SHARED_EXEC 158 159static inline int pmd_present(pmd_t pmd) 160{ 161 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 162} 163 164static inline int pmd_none(pmd_t pmd) 165{ 166 return (pmd_val(pmd) == 0); 167} 168 169static inline int pmd_bad(pmd_t pmd) 170{ 171 return !pmd_present(pmd); 172} 173 174#define pmd_leaf pmd_leaf 175static inline int pmd_leaf(pmd_t pmd) 176{ 177 return pmd_present(pmd) && 178 (pmd_val(pmd) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); 179} 180 181static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 182{ 183 *pmdp = pmd; 184} 185 186static inline void pmd_clear(pmd_t *pmdp) 187{ 188 set_pmd(pmdp, __pmd(0)); 189} 190 191static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 192{ 193 return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 194} 195 196static inline unsigned long _pgd_pfn(pgd_t pgd) 197{ 198 return pgd_val(pgd) >> _PAGE_PFN_SHIFT; 199} 200 201static inline struct page *pmd_page(pmd_t pmd) 202{ 203 return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 204} 205 206static inline unsigned long pmd_page_vaddr(pmd_t pmd) 207{ 208 return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 209} 210 211/* Yields the page frame number (PFN) of a page table entry */ 212static inline unsigned long pte_pfn(pte_t pte) 213{ 214 return (pte_val(pte) >> _PAGE_PFN_SHIFT); 215} 216 217#define pte_page(x) pfn_to_page(pte_pfn(x)) 218 219/* Constructs a page table entry */ 220static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 221{ 222 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 223} 224 225#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 226 227static inline int pte_present(pte_t pte) 228{ 229 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 230} 231 232static inline int pte_none(pte_t pte) 233{ 234 return (pte_val(pte) == 0); 235} 236 237static inline int pte_write(pte_t pte) 238{ 239 return pte_val(pte) & _PAGE_WRITE; 240} 241 242static inline int pte_exec(pte_t pte) 243{ 244 return pte_val(pte) & _PAGE_EXEC; 245} 246 247static inline int pte_huge(pte_t pte) 248{ 249 return pte_present(pte) 250 && (pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); 251} 252 253static inline int pte_dirty(pte_t pte) 254{ 255 return pte_val(pte) & _PAGE_DIRTY; 256} 257 258static inline int pte_young(pte_t pte) 259{ 260 return pte_val(pte) & _PAGE_ACCESSED; 261} 262 263static inline int pte_special(pte_t pte) 264{ 265 return pte_val(pte) & _PAGE_SPECIAL; 266} 267 268/* static inline pte_t pte_rdprotect(pte_t pte) */ 269 270static inline pte_t pte_wrprotect(pte_t pte) 271{ 272 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 273} 274 275/* static inline pte_t pte_mkread(pte_t pte) */ 276 277static inline pte_t pte_mkwrite(pte_t pte) 278{ 279 return __pte(pte_val(pte) | _PAGE_WRITE); 280} 281 282/* static inline pte_t pte_mkexec(pte_t pte) */ 283 284static inline pte_t pte_mkdirty(pte_t pte) 285{ 286 return __pte(pte_val(pte) | _PAGE_DIRTY); 287} 288 289static inline pte_t pte_mkclean(pte_t pte) 290{ 291 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 292} 293 294static inline pte_t pte_mkyoung(pte_t pte) 295{ 296 return __pte(pte_val(pte) | _PAGE_ACCESSED); 297} 298 299static inline pte_t pte_mkold(pte_t pte) 300{ 301 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 302} 303 304static inline pte_t pte_mkspecial(pte_t pte) 305{ 306 return __pte(pte_val(pte) | _PAGE_SPECIAL); 307} 308 309static inline pte_t pte_mkhuge(pte_t pte) 310{ 311 return pte; 312} 313 314/* Modify page protection bits */ 315static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 316{ 317 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 318} 319 320#define pgd_ERROR(e) \ 321 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 322 323 324/* Commit new configuration to MMU hardware */ 325static inline void update_mmu_cache(struct vm_area_struct *vma, 326 unsigned long address, pte_t *ptep) 327{ 328 /* 329 * The kernel assumes that TLBs don't cache invalid entries, but 330 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 331 * cache flush; it is necessary even after writing invalid entries. 332 * Relying on flush_tlb_fix_spurious_fault would suffice, but 333 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 334 */ 335 local_flush_tlb_page(address); 336} 337 338#define __HAVE_ARCH_PTE_SAME 339static inline int pte_same(pte_t pte_a, pte_t pte_b) 340{ 341 return pte_val(pte_a) == pte_val(pte_b); 342} 343 344/* 345 * Certain architectures need to do special things when PTEs within 346 * a page table are directly modified. Thus, the following hook is 347 * made available. 348 */ 349static inline void set_pte(pte_t *ptep, pte_t pteval) 350{ 351 *ptep = pteval; 352} 353 354void flush_icache_pte(pte_t pte); 355 356static inline void set_pte_at(struct mm_struct *mm, 357 unsigned long addr, pte_t *ptep, pte_t pteval) 358{ 359 if (pte_present(pteval) && pte_exec(pteval)) 360 flush_icache_pte(pteval); 361 362 set_pte(ptep, pteval); 363} 364 365static inline void pte_clear(struct mm_struct *mm, 366 unsigned long addr, pte_t *ptep) 367{ 368 set_pte_at(mm, addr, ptep, __pte(0)); 369} 370 371#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 372static inline int ptep_set_access_flags(struct vm_area_struct *vma, 373 unsigned long address, pte_t *ptep, 374 pte_t entry, int dirty) 375{ 376 if (!pte_same(*ptep, entry)) 377 set_pte_at(vma->vm_mm, address, ptep, entry); 378 /* 379 * update_mmu_cache will unconditionally execute, handling both 380 * the case that the PTE changed and the spurious fault case. 381 */ 382 return true; 383} 384 385#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 386static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 387 unsigned long address, pte_t *ptep) 388{ 389 return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 390} 391 392#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 393static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 394 unsigned long address, 395 pte_t *ptep) 396{ 397 if (!pte_young(*ptep)) 398 return 0; 399 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 400} 401 402#define __HAVE_ARCH_PTEP_SET_WRPROTECT 403static inline void ptep_set_wrprotect(struct mm_struct *mm, 404 unsigned long address, pte_t *ptep) 405{ 406 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 407} 408 409#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 410static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 411 unsigned long address, pte_t *ptep) 412{ 413 /* 414 * This comment is borrowed from x86, but applies equally to RISC-V: 415 * 416 * Clearing the accessed bit without a TLB flush 417 * doesn't cause data corruption. [ It could cause incorrect 418 * page aging and the (mistaken) reclaim of hot pages, but the 419 * chance of that should be relatively low. ] 420 * 421 * So as a performance optimization don't flush the TLB when 422 * clearing the accessed bit, it will eventually be flushed by 423 * a context switch or a VM operation anyway. [ In the rare 424 * event of it not getting flushed for a long time the delay 425 * shouldn't really matter because there's no real memory 426 * pressure for swapout to react to. ] 427 */ 428 return ptep_test_and_clear_young(vma, address, ptep); 429} 430 431/* 432 * Encode and decode a swap entry 433 * 434 * Format of swap PTE: 435 * bit 0: _PAGE_PRESENT (zero) 436 * bit 1: _PAGE_PROT_NONE (zero) 437 * bits 2 to 6: swap type 438 * bits 7 to XLEN-1: swap offset 439 */ 440#define __SWP_TYPE_SHIFT 2 441#define __SWP_TYPE_BITS 5 442#define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 443#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 444 445#define MAX_SWAPFILES_CHECK() \ 446 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 447 448#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 449#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 450#define __swp_entry(type, offset) ((swp_entry_t) \ 451 { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 452 453#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 454#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 455 456/* 457 * In the RV64 Linux scheme, we give the user half of the virtual-address space 458 * and give the kernel the other (upper) half. 459 */ 460#ifdef CONFIG_64BIT 461#define KERN_VIRT_START (-(BIT(CONFIG_VA_BITS)) + TASK_SIZE) 462#else 463#define KERN_VIRT_START FIXADDR_START 464#endif 465 466/* 467 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 468 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 469 */ 470#ifdef CONFIG_64BIT 471#define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) 472#else 473#define TASK_SIZE FIXADDR_START 474#endif 475 476#else /* CONFIG_MMU */ 477 478#define PAGE_SHARED __pgprot(0) 479#define PAGE_KERNEL __pgprot(0) 480#define swapper_pg_dir NULL 481#define TASK_SIZE 0xffffffffUL 482#define VMALLOC_START 0 483#define VMALLOC_END TASK_SIZE 484 485static inline void __kernel_map_pages(struct page *page, int numpages, int enable) {} 486 487#endif /* !CONFIG_MMU */ 488 489#define kern_addr_valid(addr) (1) /* FIXME */ 490 491extern char _start[]; 492extern void *dtb_early_va; 493extern uintptr_t dtb_early_pa; 494void setup_bootmem(void); 495void paging_init(void); 496void misc_mem_init(void); 497 498#define FIRST_USER_ADDRESS 0 499 500/* 501 * ZERO_PAGE is a global shared page that is always zero, 502 * used for zero-mapped memory areas, etc. 503 */ 504extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 505#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 506 507#endif /* !__ASSEMBLY__ */ 508 509#endif /* _ASM_RISCV_PGTABLE_H */ 510