18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright 2016,2017 IBM Corporation. 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci#ifndef __XIVE_INTERNAL_H 68c2ecf20Sopenharmony_ci#define __XIVE_INTERNAL_H 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci/* 98c2ecf20Sopenharmony_ci * A "disabled" interrupt should never fire, to catch problems 108c2ecf20Sopenharmony_ci * we set its logical number to this 118c2ecf20Sopenharmony_ci */ 128c2ecf20Sopenharmony_ci#define XIVE_BAD_IRQ 0x7fffffff 138c2ecf20Sopenharmony_ci#define XIVE_MAX_IRQ (XIVE_BAD_IRQ - 1) 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci/* Each CPU carry one of these with various per-CPU state */ 168c2ecf20Sopenharmony_cistruct xive_cpu { 178c2ecf20Sopenharmony_ci#ifdef CONFIG_SMP 188c2ecf20Sopenharmony_ci /* HW irq number and data of IPI */ 198c2ecf20Sopenharmony_ci u32 hw_ipi; 208c2ecf20Sopenharmony_ci struct xive_irq_data ipi_data; 218c2ecf20Sopenharmony_ci#endif /* CONFIG_SMP */ 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci int chip_id; 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci /* Queue datas. Only one is populated */ 268c2ecf20Sopenharmony_ci#define XIVE_MAX_QUEUES 8 278c2ecf20Sopenharmony_ci struct xive_q queue[XIVE_MAX_QUEUES]; 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci /* 308c2ecf20Sopenharmony_ci * Pending mask. Each bit corresponds to a priority that 318c2ecf20Sopenharmony_ci * potentially has pending interrupts. 328c2ecf20Sopenharmony_ci */ 338c2ecf20Sopenharmony_ci u8 pending_prio; 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci /* Cache of HW CPPR */ 368c2ecf20Sopenharmony_ci u8 cppr; 378c2ecf20Sopenharmony_ci}; 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci/* Backend ops */ 408c2ecf20Sopenharmony_cistruct xive_ops { 418c2ecf20Sopenharmony_ci int (*populate_irq_data)(u32 hw_irq, struct xive_irq_data *data); 428c2ecf20Sopenharmony_ci int (*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); 438c2ecf20Sopenharmony_ci int (*get_irq_config)(u32 hw_irq, u32 *target, u8 *prio, 448c2ecf20Sopenharmony_ci u32 *sw_irq); 458c2ecf20Sopenharmony_ci int (*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio); 468c2ecf20Sopenharmony_ci void (*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio); 478c2ecf20Sopenharmony_ci void (*setup_cpu)(unsigned int cpu, struct xive_cpu *xc); 488c2ecf20Sopenharmony_ci void (*teardown_cpu)(unsigned int cpu, struct xive_cpu *xc); 498c2ecf20Sopenharmony_ci bool (*match)(struct device_node *np); 508c2ecf20Sopenharmony_ci void (*shutdown)(void); 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci void (*update_pending)(struct xive_cpu *xc); 538c2ecf20Sopenharmony_ci void (*eoi)(u32 hw_irq); 548c2ecf20Sopenharmony_ci void (*sync_source)(u32 hw_irq); 558c2ecf20Sopenharmony_ci u64 (*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write); 568c2ecf20Sopenharmony_ci#ifdef CONFIG_SMP 578c2ecf20Sopenharmony_ci int (*get_ipi)(unsigned int cpu, struct xive_cpu *xc); 588c2ecf20Sopenharmony_ci void (*put_ipi)(unsigned int cpu, struct xive_cpu *xc); 598c2ecf20Sopenharmony_ci#endif 608c2ecf20Sopenharmony_ci int (*debug_show)(struct seq_file *m, void *private); 618c2ecf20Sopenharmony_ci const char *name; 628c2ecf20Sopenharmony_ci}; 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_cibool xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset, 658c2ecf20Sopenharmony_ci u8 max_prio); 668c2ecf20Sopenharmony_ci__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift); 678c2ecf20Sopenharmony_ciint xive_core_debug_init(void); 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_cistatic inline u32 xive_alloc_order(u32 queue_shift) 708c2ecf20Sopenharmony_ci{ 718c2ecf20Sopenharmony_ci return (queue_shift > PAGE_SHIFT) ? (queue_shift - PAGE_SHIFT) : 0; 728c2ecf20Sopenharmony_ci} 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_ciextern bool xive_cmdline_disabled; 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci#endif /* __XIVE_INTERNAL_H */ 77