1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2016,2017 IBM Corporation. 4 */ 5 6#define pr_fmt(fmt) "xive: " fmt 7 8#include <linux/types.h> 9#include <linux/threads.h> 10#include <linux/kernel.h> 11#include <linux/irq.h> 12#include <linux/debugfs.h> 13#include <linux/smp.h> 14#include <linux/interrupt.h> 15#include <linux/seq_file.h> 16#include <linux/init.h> 17#include <linux/cpu.h> 18#include <linux/of.h> 19#include <linux/slab.h> 20#include <linux/spinlock.h> 21#include <linux/msi.h> 22#include <linux/vmalloc.h> 23 24#include <asm/debugfs.h> 25#include <asm/prom.h> 26#include <asm/io.h> 27#include <asm/smp.h> 28#include <asm/machdep.h> 29#include <asm/irq.h> 30#include <asm/errno.h> 31#include <asm/xive.h> 32#include <asm/xive-regs.h> 33#include <asm/xmon.h> 34 35#include "xive-internal.h" 36 37#undef DEBUG_FLUSH 38#undef DEBUG_ALL 39 40#ifdef DEBUG_ALL 41#define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \ 42 smp_processor_id(), ## __VA_ARGS__) 43#else 44#define DBG_VERBOSE(fmt...) do { } while(0) 45#endif 46 47bool __xive_enabled; 48EXPORT_SYMBOL_GPL(__xive_enabled); 49bool xive_cmdline_disabled; 50 51/* We use only one priority for now */ 52static u8 xive_irq_priority; 53 54/* TIMA exported to KVM */ 55void __iomem *xive_tima; 56EXPORT_SYMBOL_GPL(xive_tima); 57u32 xive_tima_offset; 58 59/* Backend ops */ 60static const struct xive_ops *xive_ops; 61 62/* Our global interrupt domain */ 63static struct irq_domain *xive_irq_domain; 64 65#ifdef CONFIG_SMP 66/* The IPIs all use the same logical irq number */ 67static u32 xive_ipi_irq; 68#endif 69 70/* Xive state for each CPU */ 71static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu); 72 73/* An invalid CPU target */ 74#define XIVE_INVALID_TARGET (-1) 75 76/* 77 * Read the next entry in a queue, return its content if it's valid 78 * or 0 if there is no new entry. 79 * 80 * The queue pointer is moved forward unless "just_peek" is set 81 */ 82static u32 xive_read_eq(struct xive_q *q, bool just_peek) 83{ 84 u32 cur; 85 86 if (!q->qpage) 87 return 0; 88 cur = be32_to_cpup(q->qpage + q->idx); 89 90 /* Check valid bit (31) vs current toggle polarity */ 91 if ((cur >> 31) == q->toggle) 92 return 0; 93 94 /* If consuming from the queue ... */ 95 if (!just_peek) { 96 /* Next entry */ 97 q->idx = (q->idx + 1) & q->msk; 98 99 /* Wrap around: flip valid toggle */ 100 if (q->idx == 0) 101 q->toggle ^= 1; 102 } 103 /* Mask out the valid bit (31) */ 104 return cur & 0x7fffffff; 105} 106 107/* 108 * Scans all the queue that may have interrupts in them 109 * (based on "pending_prio") in priority order until an 110 * interrupt is found or all the queues are empty. 111 * 112 * Then updates the CPPR (Current Processor Priority 113 * Register) based on the most favored interrupt found 114 * (0xff if none) and return what was found (0 if none). 115 * 116 * If just_peek is set, return the most favored pending 117 * interrupt if any but don't update the queue pointers. 118 * 119 * Note: This function can operate generically on any number 120 * of queues (up to 8). The current implementation of the XIVE 121 * driver only uses a single queue however. 122 * 123 * Note2: This will also "flush" "the pending_count" of a queue 124 * into the "count" when that queue is observed to be empty. 125 * This is used to keep track of the amount of interrupts 126 * targetting a queue. When an interrupt is moved away from 127 * a queue, we only decrement that queue count once the queue 128 * has been observed empty to avoid races. 129 */ 130static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek) 131{ 132 u32 irq = 0; 133 u8 prio = 0; 134 135 /* Find highest pending priority */ 136 while (xc->pending_prio != 0) { 137 struct xive_q *q; 138 139 prio = ffs(xc->pending_prio) - 1; 140 DBG_VERBOSE("scan_irq: trying prio %d\n", prio); 141 142 /* Try to fetch */ 143 irq = xive_read_eq(&xc->queue[prio], just_peek); 144 145 /* Found something ? That's it */ 146 if (irq) { 147 if (just_peek || irq_to_desc(irq)) 148 break; 149 /* 150 * We should never get here; if we do then we must 151 * have failed to synchronize the interrupt properly 152 * when shutting it down. 153 */ 154 pr_crit("xive: got interrupt %d without descriptor, dropping\n", 155 irq); 156 WARN_ON(1); 157 continue; 158 } 159 160 /* Clear pending bits */ 161 xc->pending_prio &= ~(1 << prio); 162 163 /* 164 * Check if the queue count needs adjusting due to 165 * interrupts being moved away. See description of 166 * xive_dec_target_count() 167 */ 168 q = &xc->queue[prio]; 169 if (atomic_read(&q->pending_count)) { 170 int p = atomic_xchg(&q->pending_count, 0); 171 if (p) { 172 WARN_ON(p > atomic_read(&q->count)); 173 atomic_sub(p, &q->count); 174 } 175 } 176 } 177 178 /* If nothing was found, set CPPR to 0xff */ 179 if (irq == 0) 180 prio = 0xff; 181 182 /* Update HW CPPR to match if necessary */ 183 if (prio != xc->cppr) { 184 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio); 185 xc->cppr = prio; 186 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio); 187 } 188 189 return irq; 190} 191 192/* 193 * This is used to perform the magic loads from an ESB 194 * described in xive-regs.h 195 */ 196static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset) 197{ 198 u64 val; 199 200 if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI) 201 offset |= XIVE_ESB_LD_ST_MO; 202 203 /* Handle HW errata */ 204 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG) 205 offset |= offset << 4; 206 207 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw) 208 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0); 209 else 210 val = in_be64(xd->eoi_mmio + offset); 211 212 return (u8)val; 213} 214 215static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data) 216{ 217 /* Handle HW errata */ 218 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG) 219 offset |= offset << 4; 220 221 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw) 222 xive_ops->esb_rw(xd->hw_irq, offset, data, 1); 223 else 224 out_be64(xd->eoi_mmio + offset, data); 225} 226 227#ifdef CONFIG_XMON 228static notrace void xive_dump_eq(const char *name, struct xive_q *q) 229{ 230 u32 i0, i1, idx; 231 232 if (!q->qpage) 233 return; 234 idx = q->idx; 235 i0 = be32_to_cpup(q->qpage + idx); 236 idx = (idx + 1) & q->msk; 237 i1 = be32_to_cpup(q->qpage + idx); 238 xmon_printf("%s idx=%d T=%d %08x %08x ...", name, 239 q->idx, q->toggle, i0, i1); 240} 241 242notrace void xmon_xive_do_dump(int cpu) 243{ 244 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 245 246 xmon_printf("CPU %d:", cpu); 247 if (xc) { 248 xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr); 249 250#ifdef CONFIG_SMP 251 { 252 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET); 253 254 xmon_printf("IPI=0x%08x PQ=%c%c ", xc->hw_ipi, 255 val & XIVE_ESB_VAL_P ? 'P' : '-', 256 val & XIVE_ESB_VAL_Q ? 'Q' : '-'); 257 } 258#endif 259 xive_dump_eq("EQ", &xc->queue[xive_irq_priority]); 260 } 261 xmon_printf("\n"); 262} 263 264static struct irq_data *xive_get_irq_data(u32 hw_irq) 265{ 266 unsigned int irq = irq_find_mapping(xive_irq_domain, hw_irq); 267 268 return irq ? irq_get_irq_data(irq) : NULL; 269} 270 271int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d) 272{ 273 int rc; 274 u32 target; 275 u8 prio; 276 u32 lirq; 277 278 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq); 279 if (rc) { 280 xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc); 281 return rc; 282 } 283 284 xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ", 285 hw_irq, target, prio, lirq); 286 287 if (!d) 288 d = xive_get_irq_data(hw_irq); 289 290 if (d) { 291 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 292 u64 val = xive_esb_read(xd, XIVE_ESB_GET); 293 294 xmon_printf("flags=%c%c%c PQ=%c%c", 295 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ', 296 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ', 297 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ', 298 val & XIVE_ESB_VAL_P ? 'P' : '-', 299 val & XIVE_ESB_VAL_Q ? 'Q' : '-'); 300 } 301 302 xmon_printf("\n"); 303 return 0; 304} 305 306#endif /* CONFIG_XMON */ 307 308static unsigned int xive_get_irq(void) 309{ 310 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 311 u32 irq; 312 313 /* 314 * This can be called either as a result of a HW interrupt or 315 * as a "replay" because EOI decided there was still something 316 * in one of the queues. 317 * 318 * First we perform an ACK cycle in order to update our mask 319 * of pending priorities. This will also have the effect of 320 * updating the CPPR to the most favored pending interrupts. 321 * 322 * In the future, if we have a way to differentiate a first 323 * entry (on HW interrupt) from a replay triggered by EOI, 324 * we could skip this on replays unless we soft-mask tells us 325 * that a new HW interrupt occurred. 326 */ 327 xive_ops->update_pending(xc); 328 329 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio); 330 331 /* Scan our queue(s) for interrupts */ 332 irq = xive_scan_interrupts(xc, false); 333 334 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n", 335 irq, xc->pending_prio); 336 337 /* Return pending interrupt if any */ 338 if (irq == XIVE_BAD_IRQ) 339 return 0; 340 return irq; 341} 342 343/* 344 * After EOI'ing an interrupt, we need to re-check the queue 345 * to see if another interrupt is pending since multiple 346 * interrupts can coalesce into a single notification to the 347 * CPU. 348 * 349 * If we find that there is indeed more in there, we call 350 * force_external_irq_replay() to make Linux synthetize an 351 * external interrupt on the next call to local_irq_restore(). 352 */ 353static void xive_do_queue_eoi(struct xive_cpu *xc) 354{ 355 if (xive_scan_interrupts(xc, true) != 0) { 356 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio); 357 force_external_irq_replay(); 358 } 359} 360 361/* 362 * EOI an interrupt at the source. There are several methods 363 * to do this depending on the HW version and source type 364 */ 365static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd) 366{ 367 xd->stale_p = false; 368 /* If the XIVE supports the new "store EOI facility, use it */ 369 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) 370 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0); 371 else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) { 372 /* 373 * The FW told us to call it. This happens for some 374 * interrupt sources that need additional HW whacking 375 * beyond the ESB manipulation. For example LPC interrupts 376 * on P9 DD1.0 needed a latch to be clared in the LPC bridge 377 * itself. The Firmware will take care of it. 378 */ 379 if (WARN_ON_ONCE(!xive_ops->eoi)) 380 return; 381 xive_ops->eoi(hw_irq); 382 } else { 383 u8 eoi_val; 384 385 /* 386 * Otherwise for EOI, we use the special MMIO that does 387 * a clear of both P and Q and returns the old Q, 388 * except for LSIs where we use the "EOI cycle" special 389 * load. 390 * 391 * This allows us to then do a re-trigger if Q was set 392 * rather than synthesizing an interrupt in software 393 * 394 * For LSIs the HW EOI cycle is used rather than PQ bits, 395 * as they are automatically re-triggred in HW when still 396 * pending. 397 */ 398 if (xd->flags & XIVE_IRQ_FLAG_LSI) 399 xive_esb_read(xd, XIVE_ESB_LOAD_EOI); 400 else { 401 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00); 402 DBG_VERBOSE("eoi_val=%x\n", eoi_val); 403 404 /* Re-trigger if needed */ 405 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio) 406 out_be64(xd->trig_mmio, 0); 407 } 408 } 409} 410 411/* irq_chip eoi callback, called with irq descriptor lock held */ 412static void xive_irq_eoi(struct irq_data *d) 413{ 414 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 415 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 416 417 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n", 418 d->irq, irqd_to_hwirq(d), xc->pending_prio); 419 420 /* 421 * EOI the source if it hasn't been disabled and hasn't 422 * been passed-through to a KVM guest 423 */ 424 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) && 425 !(xd->flags & XIVE_IRQ_NO_EOI)) 426 xive_do_source_eoi(irqd_to_hwirq(d), xd); 427 else 428 xd->stale_p = true; 429 430 /* 431 * Clear saved_p to indicate that it's no longer occupying 432 * a queue slot on the target queue 433 */ 434 xd->saved_p = false; 435 436 /* Check for more work in the queue */ 437 xive_do_queue_eoi(xc); 438} 439 440/* 441 * Helper used to mask and unmask an interrupt source. This 442 * is only called for normal interrupts that do not require 443 * masking/unmasking via firmware. 444 */ 445static void xive_do_source_set_mask(struct xive_irq_data *xd, 446 bool mask) 447{ 448 u64 val; 449 450 /* 451 * If the interrupt had P set, it may be in a queue. 452 * 453 * We need to make sure we don't re-enable it until it 454 * has been fetched from that queue and EOId. We keep 455 * a copy of that P state and use it to restore the 456 * ESB accordingly on unmask. 457 */ 458 if (mask) { 459 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01); 460 if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P)) 461 xd->saved_p = true; 462 xd->stale_p = false; 463 } else if (xd->saved_p) { 464 xive_esb_read(xd, XIVE_ESB_SET_PQ_10); 465 xd->saved_p = false; 466 } else { 467 xive_esb_read(xd, XIVE_ESB_SET_PQ_00); 468 xd->stale_p = false; 469 } 470} 471 472/* 473 * Try to chose "cpu" as a new interrupt target. Increments 474 * the queue accounting for that target if it's not already 475 * full. 476 */ 477static bool xive_try_pick_target(int cpu) 478{ 479 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 480 struct xive_q *q = &xc->queue[xive_irq_priority]; 481 int max; 482 483 /* 484 * Calculate max number of interrupts in that queue. 485 * 486 * We leave a gap of 1 just in case... 487 */ 488 max = (q->msk + 1) - 1; 489 return !!atomic_add_unless(&q->count, 1, max); 490} 491 492/* 493 * Un-account an interrupt for a target CPU. We don't directly 494 * decrement q->count since the interrupt might still be present 495 * in the queue. 496 * 497 * Instead increment a separate counter "pending_count" which 498 * will be substracted from "count" later when that CPU observes 499 * the queue to be empty. 500 */ 501static void xive_dec_target_count(int cpu) 502{ 503 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 504 struct xive_q *q = &xc->queue[xive_irq_priority]; 505 506 if (WARN_ON(cpu < 0 || !xc)) { 507 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc); 508 return; 509 } 510 511 /* 512 * We increment the "pending count" which will be used 513 * to decrement the target queue count whenever it's next 514 * processed and found empty. This ensure that we don't 515 * decrement while we still have the interrupt there 516 * occupying a slot. 517 */ 518 atomic_inc(&q->pending_count); 519} 520 521/* Find a tentative CPU target in a CPU mask */ 522static int xive_find_target_in_mask(const struct cpumask *mask, 523 unsigned int fuzz) 524{ 525 int cpu, first, num, i; 526 527 /* Pick up a starting point CPU in the mask based on fuzz */ 528 num = min_t(int, cpumask_weight(mask), nr_cpu_ids); 529 first = fuzz % num; 530 531 /* Locate it */ 532 cpu = cpumask_first(mask); 533 for (i = 0; i < first && cpu < nr_cpu_ids; i++) 534 cpu = cpumask_next(cpu, mask); 535 536 /* Sanity check */ 537 if (WARN_ON(cpu >= nr_cpu_ids)) 538 cpu = cpumask_first(cpu_online_mask); 539 540 /* Remember first one to handle wrap-around */ 541 first = cpu; 542 543 /* 544 * Now go through the entire mask until we find a valid 545 * target. 546 */ 547 do { 548 /* 549 * We re-check online as the fallback case passes us 550 * an untested affinity mask 551 */ 552 if (cpu_online(cpu) && xive_try_pick_target(cpu)) 553 return cpu; 554 cpu = cpumask_next(cpu, mask); 555 /* Wrap around */ 556 if (cpu >= nr_cpu_ids) 557 cpu = cpumask_first(mask); 558 } while (cpu != first); 559 560 return -1; 561} 562 563/* 564 * Pick a target CPU for an interrupt. This is done at 565 * startup or if the affinity is changed in a way that 566 * invalidates the current target. 567 */ 568static int xive_pick_irq_target(struct irq_data *d, 569 const struct cpumask *affinity) 570{ 571 static unsigned int fuzz; 572 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 573 cpumask_var_t mask; 574 int cpu = -1; 575 576 /* 577 * If we have chip IDs, first we try to build a mask of 578 * CPUs matching the CPU and find a target in there 579 */ 580 if (xd->src_chip != XIVE_INVALID_CHIP_ID && 581 zalloc_cpumask_var(&mask, GFP_ATOMIC)) { 582 /* Build a mask of matching chip IDs */ 583 for_each_cpu_and(cpu, affinity, cpu_online_mask) { 584 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 585 if (xc->chip_id == xd->src_chip) 586 cpumask_set_cpu(cpu, mask); 587 } 588 /* Try to find a target */ 589 if (cpumask_empty(mask)) 590 cpu = -1; 591 else 592 cpu = xive_find_target_in_mask(mask, fuzz++); 593 free_cpumask_var(mask); 594 if (cpu >= 0) 595 return cpu; 596 fuzz--; 597 } 598 599 /* No chip IDs, fallback to using the affinity mask */ 600 return xive_find_target_in_mask(affinity, fuzz++); 601} 602 603static unsigned int xive_irq_startup(struct irq_data *d) 604{ 605 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 606 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 607 int target, rc; 608 609 xd->saved_p = false; 610 xd->stale_p = false; 611 pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n", 612 d->irq, hw_irq, d); 613 614#ifdef CONFIG_PCI_MSI 615 /* 616 * The generic MSI code returns with the interrupt disabled on the 617 * card, using the MSI mask bits. Firmware doesn't appear to unmask 618 * at that level, so we do it here by hand. 619 */ 620 if (irq_data_get_msi_desc(d)) 621 pci_msi_unmask_irq(d); 622#endif 623 624 /* Pick a target */ 625 target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d)); 626 if (target == XIVE_INVALID_TARGET) { 627 /* Try again breaking affinity */ 628 target = xive_pick_irq_target(d, cpu_online_mask); 629 if (target == XIVE_INVALID_TARGET) 630 return -ENXIO; 631 pr_warn("irq %d started with broken affinity\n", d->irq); 632 } 633 634 /* Sanity check */ 635 if (WARN_ON(target == XIVE_INVALID_TARGET || 636 target >= nr_cpu_ids)) 637 target = smp_processor_id(); 638 639 xd->target = target; 640 641 /* 642 * Configure the logical number to be the Linux IRQ number 643 * and set the target queue 644 */ 645 rc = xive_ops->configure_irq(hw_irq, 646 get_hard_smp_processor_id(target), 647 xive_irq_priority, d->irq); 648 if (rc) 649 return rc; 650 651 /* Unmask the ESB */ 652 xive_do_source_set_mask(xd, false); 653 654 return 0; 655} 656 657/* called with irq descriptor lock held */ 658static void xive_irq_shutdown(struct irq_data *d) 659{ 660 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 661 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 662 663 pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n", 664 d->irq, hw_irq, d); 665 666 if (WARN_ON(xd->target == XIVE_INVALID_TARGET)) 667 return; 668 669 /* Mask the interrupt at the source */ 670 xive_do_source_set_mask(xd, true); 671 672 /* 673 * Mask the interrupt in HW in the IVT/EAS and set the number 674 * to be the "bad" IRQ number 675 */ 676 xive_ops->configure_irq(hw_irq, 677 get_hard_smp_processor_id(xd->target), 678 0xff, XIVE_BAD_IRQ); 679 680 xive_dec_target_count(xd->target); 681 xd->target = XIVE_INVALID_TARGET; 682} 683 684static void xive_irq_unmask(struct irq_data *d) 685{ 686 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 687 688 pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd); 689 690 /* 691 * This is a workaround for PCI LSI problems on P9, for 692 * these, we call FW to set the mask. The problems might 693 * be fixed by P9 DD2.0, if that is the case, firmware 694 * will no longer set that flag. 695 */ 696 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) { 697 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 698 xive_ops->configure_irq(hw_irq, 699 get_hard_smp_processor_id(xd->target), 700 xive_irq_priority, d->irq); 701 return; 702 } 703 704 xive_do_source_set_mask(xd, false); 705} 706 707static void xive_irq_mask(struct irq_data *d) 708{ 709 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 710 711 pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd); 712 713 /* 714 * This is a workaround for PCI LSI problems on P9, for 715 * these, we call OPAL to set the mask. The problems might 716 * be fixed by P9 DD2.0, if that is the case, firmware 717 * will no longer set that flag. 718 */ 719 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) { 720 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 721 xive_ops->configure_irq(hw_irq, 722 get_hard_smp_processor_id(xd->target), 723 0xff, d->irq); 724 return; 725 } 726 727 xive_do_source_set_mask(xd, true); 728} 729 730static int xive_irq_set_affinity(struct irq_data *d, 731 const struct cpumask *cpumask, 732 bool force) 733{ 734 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 735 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 736 u32 target, old_target; 737 int rc = 0; 738 739 pr_devel("xive_irq_set_affinity: irq %d\n", d->irq); 740 741 /* Is this valid ? */ 742 if (cpumask_any_and(cpumask, cpu_online_mask) >= nr_cpu_ids) 743 return -EINVAL; 744 745 /* Don't do anything if the interrupt isn't started */ 746 if (!irqd_is_started(d)) 747 return IRQ_SET_MASK_OK; 748 749 /* 750 * If existing target is already in the new mask, and is 751 * online then do nothing. 752 */ 753 if (xd->target != XIVE_INVALID_TARGET && 754 cpu_online(xd->target) && 755 cpumask_test_cpu(xd->target, cpumask)) 756 return IRQ_SET_MASK_OK; 757 758 /* Pick a new target */ 759 target = xive_pick_irq_target(d, cpumask); 760 761 /* No target found */ 762 if (target == XIVE_INVALID_TARGET) 763 return -ENXIO; 764 765 /* Sanity check */ 766 if (WARN_ON(target >= nr_cpu_ids)) 767 target = smp_processor_id(); 768 769 old_target = xd->target; 770 771 /* 772 * Only configure the irq if it's not currently passed-through to 773 * a KVM guest 774 */ 775 if (!irqd_is_forwarded_to_vcpu(d)) 776 rc = xive_ops->configure_irq(hw_irq, 777 get_hard_smp_processor_id(target), 778 xive_irq_priority, d->irq); 779 if (rc < 0) { 780 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq); 781 return rc; 782 } 783 784 pr_devel(" target: 0x%x\n", target); 785 xd->target = target; 786 787 /* Give up previous target */ 788 if (old_target != XIVE_INVALID_TARGET) 789 xive_dec_target_count(old_target); 790 791 return IRQ_SET_MASK_OK; 792} 793 794static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type) 795{ 796 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 797 798 /* 799 * We only support these. This has really no effect other than setting 800 * the corresponding descriptor bits mind you but those will in turn 801 * affect the resend function when re-enabling an edge interrupt. 802 * 803 * Set set the default to edge as explained in map(). 804 */ 805 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE) 806 flow_type = IRQ_TYPE_EDGE_RISING; 807 808 if (flow_type != IRQ_TYPE_EDGE_RISING && 809 flow_type != IRQ_TYPE_LEVEL_LOW) 810 return -EINVAL; 811 812 irqd_set_trigger_type(d, flow_type); 813 814 /* 815 * Double check it matches what the FW thinks 816 * 817 * NOTE: We don't know yet if the PAPR interface will provide 818 * the LSI vs MSI information apart from the device-tree so 819 * this check might have to move into an optional backend call 820 * that is specific to the native backend 821 */ 822 if ((flow_type == IRQ_TYPE_LEVEL_LOW) != 823 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) { 824 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n", 825 d->irq, (u32)irqd_to_hwirq(d), 826 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge", 827 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge"); 828 } 829 830 return IRQ_SET_MASK_OK_NOCOPY; 831} 832 833static int xive_irq_retrigger(struct irq_data *d) 834{ 835 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 836 837 /* This should be only for MSIs */ 838 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI)) 839 return 0; 840 841 /* 842 * To perform a retrigger, we first set the PQ bits to 843 * 11, then perform an EOI. 844 */ 845 xive_esb_read(xd, XIVE_ESB_SET_PQ_11); 846 847 /* 848 * Note: We pass "0" to the hw_irq argument in order to 849 * avoid calling into the backend EOI code which we don't 850 * want to do in the case of a re-trigger. Backends typically 851 * only do EOI for LSIs anyway. 852 */ 853 xive_do_source_eoi(0, xd); 854 855 return 1; 856} 857 858/* 859 * Caller holds the irq descriptor lock, so this won't be called 860 * concurrently with xive_get_irqchip_state on the same interrupt. 861 */ 862static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state) 863{ 864 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); 865 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 866 int rc; 867 u8 pq; 868 869 /* 870 * We only support this on interrupts that do not require 871 * firmware calls for masking and unmasking 872 */ 873 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) 874 return -EIO; 875 876 /* 877 * This is called by KVM with state non-NULL for enabling 878 * pass-through or NULL for disabling it 879 */ 880 if (state) { 881 irqd_set_forwarded_to_vcpu(d); 882 883 /* Set it to PQ=10 state to prevent further sends */ 884 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10); 885 if (!xd->stale_p) { 886 xd->saved_p = !!(pq & XIVE_ESB_VAL_P); 887 xd->stale_p = !xd->saved_p; 888 } 889 890 /* No target ? nothing to do */ 891 if (xd->target == XIVE_INVALID_TARGET) { 892 /* 893 * An untargetted interrupt should have been 894 * also masked at the source 895 */ 896 WARN_ON(xd->saved_p); 897 898 return 0; 899 } 900 901 /* 902 * If P was set, adjust state to PQ=11 to indicate 903 * that a resend is needed for the interrupt to reach 904 * the guest. Also remember the value of P. 905 * 906 * This also tells us that it's in flight to a host queue 907 * or has already been fetched but hasn't been EOIed yet 908 * by the host. This it's potentially using up a host 909 * queue slot. This is important to know because as long 910 * as this is the case, we must not hard-unmask it when 911 * "returning" that interrupt to the host. 912 * 913 * This saved_p is cleared by the host EOI, when we know 914 * for sure the queue slot is no longer in use. 915 */ 916 if (xd->saved_p) { 917 xive_esb_read(xd, XIVE_ESB_SET_PQ_11); 918 919 /* 920 * Sync the XIVE source HW to ensure the interrupt 921 * has gone through the EAS before we change its 922 * target to the guest. That should guarantee us 923 * that we *will* eventually get an EOI for it on 924 * the host. Otherwise there would be a small window 925 * for P to be seen here but the interrupt going 926 * to the guest queue. 927 */ 928 if (xive_ops->sync_source) 929 xive_ops->sync_source(hw_irq); 930 } 931 } else { 932 irqd_clr_forwarded_to_vcpu(d); 933 934 /* No host target ? hard mask and return */ 935 if (xd->target == XIVE_INVALID_TARGET) { 936 xive_do_source_set_mask(xd, true); 937 return 0; 938 } 939 940 /* 941 * Sync the XIVE source HW to ensure the interrupt 942 * has gone through the EAS before we change its 943 * target to the host. 944 */ 945 if (xive_ops->sync_source) 946 xive_ops->sync_source(hw_irq); 947 948 /* 949 * By convention we are called with the interrupt in 950 * a PQ=10 or PQ=11 state, ie, it won't fire and will 951 * have latched in Q whether there's a pending HW 952 * interrupt or not. 953 * 954 * First reconfigure the target. 955 */ 956 rc = xive_ops->configure_irq(hw_irq, 957 get_hard_smp_processor_id(xd->target), 958 xive_irq_priority, d->irq); 959 if (rc) 960 return rc; 961 962 /* 963 * Then if saved_p is not set, effectively re-enable the 964 * interrupt with an EOI. If it is set, we know there is 965 * still a message in a host queue somewhere that will be 966 * EOId eventually. 967 * 968 * Note: We don't check irqd_irq_disabled(). Effectively, 969 * we *will* let the irq get through even if masked if the 970 * HW is still firing it in order to deal with the whole 971 * saved_p business properly. If the interrupt triggers 972 * while masked, the generic code will re-mask it anyway. 973 */ 974 if (!xd->saved_p) 975 xive_do_source_eoi(hw_irq, xd); 976 977 } 978 return 0; 979} 980 981/* Called with irq descriptor lock held. */ 982static int xive_get_irqchip_state(struct irq_data *data, 983 enum irqchip_irq_state which, bool *state) 984{ 985 struct xive_irq_data *xd = irq_data_get_irq_handler_data(data); 986 u8 pq; 987 988 switch (which) { 989 case IRQCHIP_STATE_ACTIVE: 990 pq = xive_esb_read(xd, XIVE_ESB_GET); 991 992 /* 993 * The esb value being all 1's means we couldn't get 994 * the PQ state of the interrupt through mmio. It may 995 * happen, for example when querying a PHB interrupt 996 * while the PHB is in an error state. We consider the 997 * interrupt to be inactive in that case. 998 */ 999 *state = (pq != XIVE_ESB_INVALID) && !xd->stale_p && 1000 (xd->saved_p || (!!(pq & XIVE_ESB_VAL_P) && 1001 !irqd_irq_disabled(data))); 1002 return 0; 1003 default: 1004 return -EINVAL; 1005 } 1006} 1007 1008static struct irq_chip xive_irq_chip = { 1009 .name = "XIVE-IRQ", 1010 .irq_startup = xive_irq_startup, 1011 .irq_shutdown = xive_irq_shutdown, 1012 .irq_eoi = xive_irq_eoi, 1013 .irq_mask = xive_irq_mask, 1014 .irq_unmask = xive_irq_unmask, 1015 .irq_set_affinity = xive_irq_set_affinity, 1016 .irq_set_type = xive_irq_set_type, 1017 .irq_retrigger = xive_irq_retrigger, 1018 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity, 1019 .irq_get_irqchip_state = xive_get_irqchip_state, 1020}; 1021 1022bool is_xive_irq(struct irq_chip *chip) 1023{ 1024 return chip == &xive_irq_chip; 1025} 1026EXPORT_SYMBOL_GPL(is_xive_irq); 1027 1028void xive_cleanup_irq_data(struct xive_irq_data *xd) 1029{ 1030 if (xd->eoi_mmio) { 1031 unmap_kernel_range((unsigned long)xd->eoi_mmio, 1032 1u << xd->esb_shift); 1033 iounmap(xd->eoi_mmio); 1034 if (xd->eoi_mmio == xd->trig_mmio) 1035 xd->trig_mmio = NULL; 1036 xd->eoi_mmio = NULL; 1037 } 1038 if (xd->trig_mmio) { 1039 unmap_kernel_range((unsigned long)xd->trig_mmio, 1040 1u << xd->esb_shift); 1041 iounmap(xd->trig_mmio); 1042 xd->trig_mmio = NULL; 1043 } 1044} 1045EXPORT_SYMBOL_GPL(xive_cleanup_irq_data); 1046 1047static int xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw) 1048{ 1049 struct xive_irq_data *xd; 1050 int rc; 1051 1052 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL); 1053 if (!xd) 1054 return -ENOMEM; 1055 rc = xive_ops->populate_irq_data(hw, xd); 1056 if (rc) { 1057 kfree(xd); 1058 return rc; 1059 } 1060 xd->target = XIVE_INVALID_TARGET; 1061 irq_set_handler_data(virq, xd); 1062 1063 /* 1064 * Turn OFF by default the interrupt being mapped. A side 1065 * effect of this check is the mapping the ESB page of the 1066 * interrupt in the Linux address space. This prevents page 1067 * fault issues in the crash handler which masks all 1068 * interrupts. 1069 */ 1070 xive_esb_read(xd, XIVE_ESB_SET_PQ_01); 1071 1072 return 0; 1073} 1074 1075static void xive_irq_free_data(unsigned int virq) 1076{ 1077 struct xive_irq_data *xd = irq_get_handler_data(virq); 1078 1079 if (!xd) 1080 return; 1081 irq_set_handler_data(virq, NULL); 1082 xive_cleanup_irq_data(xd); 1083 kfree(xd); 1084} 1085 1086#ifdef CONFIG_SMP 1087 1088static void xive_cause_ipi(int cpu) 1089{ 1090 struct xive_cpu *xc; 1091 struct xive_irq_data *xd; 1092 1093 xc = per_cpu(xive_cpu, cpu); 1094 1095 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n", 1096 smp_processor_id(), cpu, xc->hw_ipi); 1097 1098 xd = &xc->ipi_data; 1099 if (WARN_ON(!xd->trig_mmio)) 1100 return; 1101 out_be64(xd->trig_mmio, 0); 1102} 1103 1104static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id) 1105{ 1106 return smp_ipi_demux(); 1107} 1108 1109static void xive_ipi_eoi(struct irq_data *d) 1110{ 1111 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1112 1113 /* Handle possible race with unplug and drop stale IPIs */ 1114 if (!xc) 1115 return; 1116 1117 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n", 1118 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio); 1119 1120 xive_do_source_eoi(xc->hw_ipi, &xc->ipi_data); 1121 xive_do_queue_eoi(xc); 1122} 1123 1124static void xive_ipi_do_nothing(struct irq_data *d) 1125{ 1126 /* 1127 * Nothing to do, we never mask/unmask IPIs, but the callback 1128 * has to exist for the struct irq_chip. 1129 */ 1130} 1131 1132static struct irq_chip xive_ipi_chip = { 1133 .name = "XIVE-IPI", 1134 .irq_eoi = xive_ipi_eoi, 1135 .irq_mask = xive_ipi_do_nothing, 1136 .irq_unmask = xive_ipi_do_nothing, 1137}; 1138 1139static void __init xive_request_ipi(void) 1140{ 1141 unsigned int virq; 1142 1143 /* 1144 * Initialization failed, move on, we might manage to 1145 * reach the point where we display our errors before 1146 * the system falls appart 1147 */ 1148 if (!xive_irq_domain) 1149 return; 1150 1151 /* Initialize it */ 1152 virq = irq_create_mapping(xive_irq_domain, 0); 1153 xive_ipi_irq = virq; 1154 1155 WARN_ON(request_irq(virq, xive_muxed_ipi_action, 1156 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL)); 1157} 1158 1159static int xive_setup_cpu_ipi(unsigned int cpu) 1160{ 1161 struct xive_cpu *xc; 1162 int rc; 1163 1164 pr_debug("Setting up IPI for CPU %d\n", cpu); 1165 1166 xc = per_cpu(xive_cpu, cpu); 1167 1168 /* Check if we are already setup */ 1169 if (xc->hw_ipi != XIVE_BAD_IRQ) 1170 return 0; 1171 1172 /* Grab an IPI from the backend, this will populate xc->hw_ipi */ 1173 if (xive_ops->get_ipi(cpu, xc)) 1174 return -EIO; 1175 1176 /* 1177 * Populate the IRQ data in the xive_cpu structure and 1178 * configure the HW / enable the IPIs. 1179 */ 1180 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data); 1181 if (rc) { 1182 pr_err("Failed to populate IPI data on CPU %d\n", cpu); 1183 return -EIO; 1184 } 1185 rc = xive_ops->configure_irq(xc->hw_ipi, 1186 get_hard_smp_processor_id(cpu), 1187 xive_irq_priority, xive_ipi_irq); 1188 if (rc) { 1189 pr_err("Failed to map IPI CPU %d\n", cpu); 1190 return -EIO; 1191 } 1192 pr_devel("CPU %d HW IPI %x, virq %d, trig_mmio=%p\n", cpu, 1193 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio); 1194 1195 /* Unmask it */ 1196 xive_do_source_set_mask(&xc->ipi_data, false); 1197 1198 return 0; 1199} 1200 1201static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc) 1202{ 1203 /* Disable the IPI and free the IRQ data */ 1204 1205 /* Already cleaned up ? */ 1206 if (xc->hw_ipi == XIVE_BAD_IRQ) 1207 return; 1208 1209 /* Mask the IPI */ 1210 xive_do_source_set_mask(&xc->ipi_data, true); 1211 1212 /* 1213 * Note: We don't call xive_cleanup_irq_data() to free 1214 * the mappings as this is called from an IPI on kexec 1215 * which is not a safe environment to call iounmap() 1216 */ 1217 1218 /* Deconfigure/mask in the backend */ 1219 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(), 1220 0xff, xive_ipi_irq); 1221 1222 /* Free the IPIs in the backend */ 1223 xive_ops->put_ipi(cpu, xc); 1224} 1225 1226void __init xive_smp_probe(void) 1227{ 1228 smp_ops->cause_ipi = xive_cause_ipi; 1229 1230 /* Register the IPI */ 1231 xive_request_ipi(); 1232 1233 /* Allocate and setup IPI for the boot CPU */ 1234 xive_setup_cpu_ipi(smp_processor_id()); 1235} 1236 1237#endif /* CONFIG_SMP */ 1238 1239static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq, 1240 irq_hw_number_t hw) 1241{ 1242 int rc; 1243 1244 /* 1245 * Mark interrupts as edge sensitive by default so that resend 1246 * actually works. Will fix that up below if needed. 1247 */ 1248 irq_clear_status_flags(virq, IRQ_LEVEL); 1249 1250#ifdef CONFIG_SMP 1251 /* IPIs are special and come up with HW number 0 */ 1252 if (hw == 0) { 1253 /* 1254 * IPIs are marked per-cpu. We use separate HW interrupts under 1255 * the hood but associated with the same "linux" interrupt 1256 */ 1257 irq_set_chip_and_handler(virq, &xive_ipi_chip, 1258 handle_percpu_irq); 1259 return 0; 1260 } 1261#endif 1262 1263 rc = xive_irq_alloc_data(virq, hw); 1264 if (rc) 1265 return rc; 1266 1267 irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq); 1268 1269 return 0; 1270} 1271 1272static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq) 1273{ 1274 struct irq_data *data = irq_get_irq_data(virq); 1275 unsigned int hw_irq; 1276 1277 /* XXX Assign BAD number */ 1278 if (!data) 1279 return; 1280 hw_irq = (unsigned int)irqd_to_hwirq(data); 1281 if (hw_irq) 1282 xive_irq_free_data(virq); 1283} 1284 1285static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct, 1286 const u32 *intspec, unsigned int intsize, 1287 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 1288 1289{ 1290 *out_hwirq = intspec[0]; 1291 1292 /* 1293 * If intsize is at least 2, we look for the type in the second cell, 1294 * we assume the LSB indicates a level interrupt. 1295 */ 1296 if (intsize > 1) { 1297 if (intspec[1] & 1) 1298 *out_flags = IRQ_TYPE_LEVEL_LOW; 1299 else 1300 *out_flags = IRQ_TYPE_EDGE_RISING; 1301 } else 1302 *out_flags = IRQ_TYPE_LEVEL_LOW; 1303 1304 return 0; 1305} 1306 1307static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node, 1308 enum irq_domain_bus_token bus_token) 1309{ 1310 return xive_ops->match(node); 1311} 1312 1313static const struct irq_domain_ops xive_irq_domain_ops = { 1314 .match = xive_irq_domain_match, 1315 .map = xive_irq_domain_map, 1316 .unmap = xive_irq_domain_unmap, 1317 .xlate = xive_irq_domain_xlate, 1318}; 1319 1320static void __init xive_init_host(void) 1321{ 1322 xive_irq_domain = irq_domain_add_nomap(NULL, XIVE_MAX_IRQ, 1323 &xive_irq_domain_ops, NULL); 1324 if (WARN_ON(xive_irq_domain == NULL)) 1325 return; 1326 irq_set_default_host(xive_irq_domain); 1327} 1328 1329static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc) 1330{ 1331 if (xc->queue[xive_irq_priority].qpage) 1332 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority); 1333} 1334 1335static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc) 1336{ 1337 int rc = 0; 1338 1339 /* We setup 1 queues for now with a 64k page */ 1340 if (!xc->queue[xive_irq_priority].qpage) 1341 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority); 1342 1343 return rc; 1344} 1345 1346static int xive_prepare_cpu(unsigned int cpu) 1347{ 1348 struct xive_cpu *xc; 1349 1350 xc = per_cpu(xive_cpu, cpu); 1351 if (!xc) { 1352 struct device_node *np; 1353 1354 xc = kzalloc_node(sizeof(struct xive_cpu), 1355 GFP_KERNEL, cpu_to_node(cpu)); 1356 if (!xc) 1357 return -ENOMEM; 1358 np = of_get_cpu_node(cpu, NULL); 1359 if (np) 1360 xc->chip_id = of_get_ibm_chip_id(np); 1361 of_node_put(np); 1362 xc->hw_ipi = XIVE_BAD_IRQ; 1363 1364 per_cpu(xive_cpu, cpu) = xc; 1365 } 1366 1367 /* Setup EQs if not already */ 1368 return xive_setup_cpu_queues(cpu, xc); 1369} 1370 1371static void xive_setup_cpu(void) 1372{ 1373 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1374 1375 /* The backend might have additional things to do */ 1376 if (xive_ops->setup_cpu) 1377 xive_ops->setup_cpu(smp_processor_id(), xc); 1378 1379 /* Set CPPR to 0xff to enable flow of interrupts */ 1380 xc->cppr = 0xff; 1381 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); 1382} 1383 1384#ifdef CONFIG_SMP 1385void xive_smp_setup_cpu(void) 1386{ 1387 pr_devel("SMP setup CPU %d\n", smp_processor_id()); 1388 1389 /* This will have already been done on the boot CPU */ 1390 if (smp_processor_id() != boot_cpuid) 1391 xive_setup_cpu(); 1392 1393} 1394 1395int xive_smp_prepare_cpu(unsigned int cpu) 1396{ 1397 int rc; 1398 1399 /* Allocate per-CPU data and queues */ 1400 rc = xive_prepare_cpu(cpu); 1401 if (rc) 1402 return rc; 1403 1404 /* Allocate and setup IPI for the new CPU */ 1405 return xive_setup_cpu_ipi(cpu); 1406} 1407 1408#ifdef CONFIG_HOTPLUG_CPU 1409static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc) 1410{ 1411 u32 irq; 1412 1413 /* We assume local irqs are disabled */ 1414 WARN_ON(!irqs_disabled()); 1415 1416 /* Check what's already in the CPU queue */ 1417 while ((irq = xive_scan_interrupts(xc, false)) != 0) { 1418 /* 1419 * We need to re-route that interrupt to its new destination. 1420 * First get and lock the descriptor 1421 */ 1422 struct irq_desc *desc = irq_to_desc(irq); 1423 struct irq_data *d = irq_desc_get_irq_data(desc); 1424 struct xive_irq_data *xd; 1425 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); 1426 1427 /* 1428 * Ignore anything that isn't a XIVE irq and ignore 1429 * IPIs, so can just be dropped. 1430 */ 1431 if (d->domain != xive_irq_domain || hw_irq == 0) 1432 continue; 1433 1434 /* 1435 * The IRQ should have already been re-routed, it's just a 1436 * stale in the old queue, so re-trigger it in order to make 1437 * it reach is new destination. 1438 */ 1439#ifdef DEBUG_FLUSH 1440 pr_info("CPU %d: Got irq %d while offline, re-sending...\n", 1441 cpu, irq); 1442#endif 1443 raw_spin_lock(&desc->lock); 1444 xd = irq_desc_get_handler_data(desc); 1445 1446 /* 1447 * Clear saved_p to indicate that it's no longer pending 1448 */ 1449 xd->saved_p = false; 1450 1451 /* 1452 * For LSIs, we EOI, this will cause a resend if it's 1453 * still asserted. Otherwise do an MSI retrigger. 1454 */ 1455 if (xd->flags & XIVE_IRQ_FLAG_LSI) 1456 xive_do_source_eoi(irqd_to_hwirq(d), xd); 1457 else 1458 xive_irq_retrigger(d); 1459 1460 raw_spin_unlock(&desc->lock); 1461 } 1462} 1463 1464void xive_smp_disable_cpu(void) 1465{ 1466 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1467 unsigned int cpu = smp_processor_id(); 1468 1469 /* Migrate interrupts away from the CPU */ 1470 irq_migrate_all_off_this_cpu(); 1471 1472 /* Set CPPR to 0 to disable flow of interrupts */ 1473 xc->cppr = 0; 1474 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); 1475 1476 /* Flush everything still in the queue */ 1477 xive_flush_cpu_queue(cpu, xc); 1478 1479 /* Re-enable CPPR */ 1480 xc->cppr = 0xff; 1481 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); 1482} 1483 1484void xive_flush_interrupt(void) 1485{ 1486 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1487 unsigned int cpu = smp_processor_id(); 1488 1489 /* Called if an interrupt occurs while the CPU is hot unplugged */ 1490 xive_flush_cpu_queue(cpu, xc); 1491} 1492 1493#endif /* CONFIG_HOTPLUG_CPU */ 1494 1495#endif /* CONFIG_SMP */ 1496 1497void xive_teardown_cpu(void) 1498{ 1499 struct xive_cpu *xc = __this_cpu_read(xive_cpu); 1500 unsigned int cpu = smp_processor_id(); 1501 1502 /* Set CPPR to 0 to disable flow of interrupts */ 1503 xc->cppr = 0; 1504 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); 1505 1506 if (xive_ops->teardown_cpu) 1507 xive_ops->teardown_cpu(cpu, xc); 1508 1509#ifdef CONFIG_SMP 1510 /* Get rid of IPI */ 1511 xive_cleanup_cpu_ipi(cpu, xc); 1512#endif 1513 1514 /* Disable and free the queues */ 1515 xive_cleanup_cpu_queues(cpu, xc); 1516} 1517 1518void xive_shutdown(void) 1519{ 1520 xive_ops->shutdown(); 1521} 1522 1523bool __init xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset, 1524 u8 max_prio) 1525{ 1526 xive_tima = area; 1527 xive_tima_offset = offset; 1528 xive_ops = ops; 1529 xive_irq_priority = max_prio; 1530 1531 ppc_md.get_irq = xive_get_irq; 1532 __xive_enabled = true; 1533 1534 pr_devel("Initializing host..\n"); 1535 xive_init_host(); 1536 1537 pr_devel("Initializing boot CPU..\n"); 1538 1539 /* Allocate per-CPU data and queues */ 1540 xive_prepare_cpu(smp_processor_id()); 1541 1542 /* Get ready for interrupts */ 1543 xive_setup_cpu(); 1544 1545 pr_info("Interrupt handling initialized with %s backend\n", 1546 xive_ops->name); 1547 pr_info("Using priority %d for all interrupts\n", max_prio); 1548 1549 return true; 1550} 1551 1552__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift) 1553{ 1554 unsigned int alloc_order; 1555 struct page *pages; 1556 __be32 *qpage; 1557 1558 alloc_order = xive_alloc_order(queue_shift); 1559 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order); 1560 if (!pages) 1561 return ERR_PTR(-ENOMEM); 1562 qpage = (__be32 *)page_address(pages); 1563 memset(qpage, 0, 1 << queue_shift); 1564 1565 return qpage; 1566} 1567 1568static int __init xive_off(char *arg) 1569{ 1570 xive_cmdline_disabled = true; 1571 return 0; 1572} 1573__setup("xive=off", xive_off); 1574 1575static void xive_debug_show_cpu(struct seq_file *m, int cpu) 1576{ 1577 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); 1578 1579 seq_printf(m, "CPU %d:", cpu); 1580 if (xc) { 1581 seq_printf(m, "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr); 1582 1583#ifdef CONFIG_SMP 1584 { 1585 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET); 1586 1587 seq_printf(m, "IPI=0x%08x PQ=%c%c ", xc->hw_ipi, 1588 val & XIVE_ESB_VAL_P ? 'P' : '-', 1589 val & XIVE_ESB_VAL_Q ? 'Q' : '-'); 1590 } 1591#endif 1592 { 1593 struct xive_q *q = &xc->queue[xive_irq_priority]; 1594 u32 i0, i1, idx; 1595 1596 if (q->qpage) { 1597 idx = q->idx; 1598 i0 = be32_to_cpup(q->qpage + idx); 1599 idx = (idx + 1) & q->msk; 1600 i1 = be32_to_cpup(q->qpage + idx); 1601 seq_printf(m, "EQ idx=%d T=%d %08x %08x ...", 1602 q->idx, q->toggle, i0, i1); 1603 } 1604 } 1605 } 1606 seq_puts(m, "\n"); 1607} 1608 1609static void xive_debug_show_irq(struct seq_file *m, u32 hw_irq, struct irq_data *d) 1610{ 1611 struct irq_chip *chip = irq_data_get_irq_chip(d); 1612 int rc; 1613 u32 target; 1614 u8 prio; 1615 u32 lirq; 1616 struct xive_irq_data *xd; 1617 u64 val; 1618 1619 if (!is_xive_irq(chip)) 1620 return; 1621 1622 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq); 1623 if (rc) { 1624 seq_printf(m, "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc); 1625 return; 1626 } 1627 1628 seq_printf(m, "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ", 1629 hw_irq, target, prio, lirq); 1630 1631 xd = irq_data_get_irq_handler_data(d); 1632 val = xive_esb_read(xd, XIVE_ESB_GET); 1633 seq_printf(m, "flags=%c%c%c PQ=%c%c", 1634 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ', 1635 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ', 1636 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ', 1637 val & XIVE_ESB_VAL_P ? 'P' : '-', 1638 val & XIVE_ESB_VAL_Q ? 'Q' : '-'); 1639 seq_puts(m, "\n"); 1640} 1641 1642static int xive_core_debug_show(struct seq_file *m, void *private) 1643{ 1644 unsigned int i; 1645 struct irq_desc *desc; 1646 int cpu; 1647 1648 if (xive_ops->debug_show) 1649 xive_ops->debug_show(m, private); 1650 1651 for_each_possible_cpu(cpu) 1652 xive_debug_show_cpu(m, cpu); 1653 1654 for_each_irq_desc(i, desc) { 1655 struct irq_data *d = irq_desc_get_irq_data(desc); 1656 unsigned int hw_irq; 1657 1658 if (!d) 1659 continue; 1660 1661 hw_irq = (unsigned int)irqd_to_hwirq(d); 1662 1663 /* IPIs are special (HW number 0) */ 1664 if (hw_irq) 1665 xive_debug_show_irq(m, hw_irq, d); 1666 } 1667 return 0; 1668} 1669DEFINE_SHOW_ATTRIBUTE(xive_core_debug); 1670 1671int xive_core_debug_init(void) 1672{ 1673 if (xive_enabled()) 1674 debugfs_create_file("xive", 0400, powerpc_debugfs_root, 1675 NULL, &xive_core_debug_fops); 1676 return 0; 1677} 1678