18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * IPIC private definitions and structure. 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Maintainer: Kumar Gala <galak@kernel.crashing.org> 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Copyright 2005 Freescale Semiconductor, Inc 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci#ifndef __IPIC_H__ 108c2ecf20Sopenharmony_ci#define __IPIC_H__ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <asm/ipic.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#define NR_IPIC_INTS 128 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci/* External IRQS */ 178c2ecf20Sopenharmony_ci#define IPIC_IRQ_EXT0 48 188c2ecf20Sopenharmony_ci#define IPIC_IRQ_EXT1 17 198c2ecf20Sopenharmony_ci#define IPIC_IRQ_EXT7 23 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci/* Default Priority Registers */ 228c2ecf20Sopenharmony_ci#define IPIC_PRIORITY_DEFAULT 0x05309770 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci/* System Global Interrupt Configuration Register */ 258c2ecf20Sopenharmony_ci#define SICFR_IPSA 0x00010000 268c2ecf20Sopenharmony_ci#define SICFR_IPSB 0x00020000 278c2ecf20Sopenharmony_ci#define SICFR_IPSC 0x00040000 288c2ecf20Sopenharmony_ci#define SICFR_IPSD 0x00080000 298c2ecf20Sopenharmony_ci#define SICFR_MPSA 0x00200000 308c2ecf20Sopenharmony_ci#define SICFR_MPSB 0x00400000 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci/* System External Interrupt Mask Register */ 338c2ecf20Sopenharmony_ci#define SEMSR_SIRQ0 0x00008000 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci/* System Error Control Register */ 368c2ecf20Sopenharmony_ci#define SERCR_MCPR 0x00000001 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_cistruct ipic { 398c2ecf20Sopenharmony_ci volatile u32 __iomem *regs; 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci /* The remapper for this IPIC */ 428c2ecf20Sopenharmony_ci struct irq_domain *irqhost; 438c2ecf20Sopenharmony_ci}; 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_cistruct ipic_info { 468c2ecf20Sopenharmony_ci u8 ack; /* pending register offset from base if the irq 478c2ecf20Sopenharmony_ci supports ack operation */ 488c2ecf20Sopenharmony_ci u8 mask; /* mask register offset from base */ 498c2ecf20Sopenharmony_ci u8 prio; /* priority register offset from base */ 508c2ecf20Sopenharmony_ci u8 force; /* force register offset from base */ 518c2ecf20Sopenharmony_ci u8 bit; /* register bit position (as per doc) 528c2ecf20Sopenharmony_ci bit mask = 1 << (31 - bit) */ 538c2ecf20Sopenharmony_ci u8 prio_mask; /* priority mask value */ 548c2ecf20Sopenharmony_ci}; 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci#endif /* __IPIC_H__ */ 57