1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 4 * 5 * Rewrite, cleanup: 6 * 7 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 8 * Copyright (C) 2006 Olof Johansson <olof@lixom.net> 9 * 10 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. 11 */ 12 13#include <linux/init.h> 14#include <linux/types.h> 15#include <linux/slab.h> 16#include <linux/mm.h> 17#include <linux/memblock.h> 18#include <linux/spinlock.h> 19#include <linux/string.h> 20#include <linux/pci.h> 21#include <linux/dma-mapping.h> 22#include <linux/crash_dump.h> 23#include <linux/memory.h> 24#include <linux/of.h> 25#include <linux/iommu.h> 26#include <linux/rculist.h> 27#include <asm/io.h> 28#include <asm/prom.h> 29#include <asm/rtas.h> 30#include <asm/iommu.h> 31#include <asm/pci-bridge.h> 32#include <asm/machdep.h> 33#include <asm/firmware.h> 34#include <asm/tce.h> 35#include <asm/ppc-pci.h> 36#include <asm/udbg.h> 37#include <asm/mmzone.h> 38#include <asm/plpar_wrappers.h> 39 40#include "pseries.h" 41 42enum { 43 DDW_QUERY_PE_DMA_WIN = 0, 44 DDW_CREATE_PE_DMA_WIN = 1, 45 DDW_REMOVE_PE_DMA_WIN = 2, 46 47 DDW_APPLICABLE_SIZE 48}; 49 50enum { 51 DDW_EXT_SIZE = 0, 52 DDW_EXT_RESET_DMA_WIN = 1, 53 DDW_EXT_QUERY_OUT_SIZE = 2 54}; 55 56static struct iommu_table_group *iommu_pseries_alloc_group(int node) 57{ 58 struct iommu_table_group *table_group; 59 struct iommu_table *tbl; 60 61 table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL, 62 node); 63 if (!table_group) 64 return NULL; 65 66 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node); 67 if (!tbl) 68 goto free_group; 69 70 INIT_LIST_HEAD_RCU(&tbl->it_group_list); 71 kref_init(&tbl->it_kref); 72 73 table_group->tables[0] = tbl; 74 75 return table_group; 76 77free_group: 78 kfree(table_group); 79 return NULL; 80} 81 82static void iommu_pseries_free_group(struct iommu_table_group *table_group, 83 const char *node_name) 84{ 85 struct iommu_table *tbl; 86 87 if (!table_group) 88 return; 89 90 tbl = table_group->tables[0]; 91#ifdef CONFIG_IOMMU_API 92 if (table_group->group) { 93 iommu_group_put(table_group->group); 94 BUG_ON(table_group->group); 95 } 96#endif 97 iommu_tce_table_put(tbl); 98 99 kfree(table_group); 100} 101 102static int tce_build_pSeries(struct iommu_table *tbl, long index, 103 long npages, unsigned long uaddr, 104 enum dma_data_direction direction, 105 unsigned long attrs) 106{ 107 u64 proto_tce; 108 __be64 *tcep; 109 u64 rpn; 110 111 proto_tce = TCE_PCI_READ; // Read allowed 112 113 if (direction != DMA_TO_DEVICE) 114 proto_tce |= TCE_PCI_WRITE; 115 116 tcep = ((__be64 *)tbl->it_base) + index; 117 118 while (npages--) { 119 /* can't move this out since we might cross MEMBLOCK boundary */ 120 rpn = __pa(uaddr) >> TCE_SHIFT; 121 *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT); 122 123 uaddr += TCE_PAGE_SIZE; 124 tcep++; 125 } 126 return 0; 127} 128 129 130static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) 131{ 132 __be64 *tcep; 133 134 tcep = ((__be64 *)tbl->it_base) + index; 135 136 while (npages--) 137 *(tcep++) = 0; 138} 139 140static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) 141{ 142 __be64 *tcep; 143 144 tcep = ((__be64 *)tbl->it_base) + index; 145 146 return be64_to_cpu(*tcep); 147} 148 149static void tce_free_pSeriesLP(unsigned long liobn, long, long); 150static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long); 151 152static int tce_build_pSeriesLP(unsigned long liobn, long tcenum, long tceshift, 153 long npages, unsigned long uaddr, 154 enum dma_data_direction direction, 155 unsigned long attrs) 156{ 157 u64 rc = 0; 158 u64 proto_tce, tce; 159 u64 rpn; 160 int ret = 0; 161 long tcenum_start = tcenum, npages_start = npages; 162 163 rpn = __pa(uaddr) >> tceshift; 164 proto_tce = TCE_PCI_READ; 165 if (direction != DMA_TO_DEVICE) 166 proto_tce |= TCE_PCI_WRITE; 167 168 while (npages--) { 169 tce = proto_tce | (rpn & TCE_RPN_MASK) << tceshift; 170 rc = plpar_tce_put((u64)liobn, (u64)tcenum << tceshift, tce); 171 172 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { 173 ret = (int)rc; 174 tce_free_pSeriesLP(liobn, tcenum_start, 175 (npages_start - (npages + 1))); 176 break; 177 } 178 179 if (rc && printk_ratelimit()) { 180 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); 181 printk("\tindex = 0x%llx\n", (u64)liobn); 182 printk("\ttcenum = 0x%llx\n", (u64)tcenum); 183 printk("\ttce val = 0x%llx\n", tce ); 184 dump_stack(); 185 } 186 187 tcenum++; 188 rpn++; 189 } 190 return ret; 191} 192 193static DEFINE_PER_CPU(__be64 *, tce_page); 194 195static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, 196 long npages, unsigned long uaddr, 197 enum dma_data_direction direction, 198 unsigned long attrs) 199{ 200 u64 rc = 0; 201 u64 proto_tce; 202 __be64 *tcep; 203 u64 rpn; 204 long l, limit; 205 long tcenum_start = tcenum, npages_start = npages; 206 int ret = 0; 207 unsigned long flags; 208 209 if ((npages == 1) || !firmware_has_feature(FW_FEATURE_PUT_TCE_IND)) { 210 return tce_build_pSeriesLP(tbl->it_index, tcenum, 211 tbl->it_page_shift, npages, uaddr, 212 direction, attrs); 213 } 214 215 local_irq_save(flags); /* to protect tcep and the page behind it */ 216 217 tcep = __this_cpu_read(tce_page); 218 219 /* This is safe to do since interrupts are off when we're called 220 * from iommu_alloc{,_sg}() 221 */ 222 if (!tcep) { 223 tcep = (__be64 *)__get_free_page(GFP_ATOMIC); 224 /* If allocation fails, fall back to the loop implementation */ 225 if (!tcep) { 226 local_irq_restore(flags); 227 return tce_build_pSeriesLP(tbl->it_index, tcenum, 228 tbl->it_page_shift, 229 npages, uaddr, direction, attrs); 230 } 231 __this_cpu_write(tce_page, tcep); 232 } 233 234 rpn = __pa(uaddr) >> TCE_SHIFT; 235 proto_tce = TCE_PCI_READ; 236 if (direction != DMA_TO_DEVICE) 237 proto_tce |= TCE_PCI_WRITE; 238 239 /* We can map max one pageful of TCEs at a time */ 240 do { 241 /* 242 * Set up the page with TCE data, looping through and setting 243 * the values. 244 */ 245 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); 246 247 for (l = 0; l < limit; l++) { 248 tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT); 249 rpn++; 250 } 251 252 rc = plpar_tce_put_indirect((u64)tbl->it_index, 253 (u64)tcenum << 12, 254 (u64)__pa(tcep), 255 limit); 256 257 npages -= limit; 258 tcenum += limit; 259 } while (npages > 0 && !rc); 260 261 local_irq_restore(flags); 262 263 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { 264 ret = (int)rc; 265 tce_freemulti_pSeriesLP(tbl, tcenum_start, 266 (npages_start - (npages + limit))); 267 return ret; 268 } 269 270 if (rc && printk_ratelimit()) { 271 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); 272 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 273 printk("\tnpages = 0x%llx\n", (u64)npages); 274 printk("\ttce[0] val = 0x%llx\n", tcep[0]); 275 dump_stack(); 276 } 277 return ret; 278} 279 280static void tce_free_pSeriesLP(unsigned long liobn, long tcenum, long npages) 281{ 282 u64 rc; 283 284 while (npages--) { 285 rc = plpar_tce_put((u64)liobn, (u64)tcenum << 12, 0); 286 287 if (rc && printk_ratelimit()) { 288 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); 289 printk("\tindex = 0x%llx\n", (u64)liobn); 290 printk("\ttcenum = 0x%llx\n", (u64)tcenum); 291 dump_stack(); 292 } 293 294 tcenum++; 295 } 296} 297 298 299static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) 300{ 301 u64 rc; 302 303 if (!firmware_has_feature(FW_FEATURE_STUFF_TCE)) 304 return tce_free_pSeriesLP(tbl->it_index, tcenum, npages); 305 306 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); 307 308 if (rc && printk_ratelimit()) { 309 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); 310 printk("\trc = %lld\n", rc); 311 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 312 printk("\tnpages = 0x%llx\n", (u64)npages); 313 dump_stack(); 314 } 315} 316 317static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) 318{ 319 u64 rc; 320 unsigned long tce_ret; 321 322 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); 323 324 if (rc && printk_ratelimit()) { 325 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc); 326 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 327 printk("\ttcenum = 0x%llx\n", (u64)tcenum); 328 dump_stack(); 329 } 330 331 return tce_ret; 332} 333 334/* this is compatible with cells for the device tree property */ 335struct dynamic_dma_window_prop { 336 __be32 liobn; /* tce table number */ 337 __be64 dma_base; /* address hi,lo */ 338 __be32 tce_shift; /* ilog2(tce_page_size) */ 339 __be32 window_shift; /* ilog2(tce_window_size) */ 340}; 341 342struct direct_window { 343 struct device_node *device; 344 const struct dynamic_dma_window_prop *prop; 345 struct list_head list; 346}; 347 348/* Dynamic DMA Window support */ 349struct ddw_query_response { 350 u32 windows_available; 351 u64 largest_available_block; 352 u32 page_size; 353 u32 migration_capable; 354}; 355 356struct ddw_create_response { 357 u32 liobn; 358 u32 addr_hi; 359 u32 addr_lo; 360}; 361 362static LIST_HEAD(direct_window_list); 363/* prevents races between memory on/offline and window creation */ 364static DEFINE_SPINLOCK(direct_window_list_lock); 365/* protects initializing window twice for same device */ 366static DEFINE_MUTEX(direct_window_init_mutex); 367#define DIRECT64_PROPNAME "linux,direct64-ddr-window-info" 368 369static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn, 370 unsigned long num_pfn, const void *arg) 371{ 372 const struct dynamic_dma_window_prop *maprange = arg; 373 int rc; 374 u64 tce_size, num_tce, dma_offset, next; 375 u32 tce_shift; 376 long limit; 377 378 tce_shift = be32_to_cpu(maprange->tce_shift); 379 tce_size = 1ULL << tce_shift; 380 next = start_pfn << PAGE_SHIFT; 381 num_tce = num_pfn << PAGE_SHIFT; 382 383 /* round back to the beginning of the tce page size */ 384 num_tce += next & (tce_size - 1); 385 next &= ~(tce_size - 1); 386 387 /* covert to number of tces */ 388 num_tce |= tce_size - 1; 389 num_tce >>= tce_shift; 390 391 do { 392 /* 393 * Set up the page with TCE data, looping through and setting 394 * the values. 395 */ 396 limit = min_t(long, num_tce, 512); 397 dma_offset = next + be64_to_cpu(maprange->dma_base); 398 399 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn), 400 dma_offset, 401 0, limit); 402 next += limit * tce_size; 403 num_tce -= limit; 404 } while (num_tce > 0 && !rc); 405 406 return rc; 407} 408 409static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn, 410 unsigned long num_pfn, const void *arg) 411{ 412 const struct dynamic_dma_window_prop *maprange = arg; 413 u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn; 414 __be64 *tcep; 415 u32 tce_shift; 416 u64 rc = 0; 417 long l, limit; 418 419 if (!firmware_has_feature(FW_FEATURE_PUT_TCE_IND)) { 420 unsigned long tceshift = be32_to_cpu(maprange->tce_shift); 421 unsigned long dmastart = (start_pfn << PAGE_SHIFT) + 422 be64_to_cpu(maprange->dma_base); 423 unsigned long tcenum = dmastart >> tceshift; 424 unsigned long npages = num_pfn << PAGE_SHIFT >> tceshift; 425 void *uaddr = __va(start_pfn << PAGE_SHIFT); 426 427 return tce_build_pSeriesLP(be32_to_cpu(maprange->liobn), 428 tcenum, tceshift, npages, (unsigned long) uaddr, 429 DMA_BIDIRECTIONAL, 0); 430 } 431 432 local_irq_disable(); /* to protect tcep and the page behind it */ 433 tcep = __this_cpu_read(tce_page); 434 435 if (!tcep) { 436 tcep = (__be64 *)__get_free_page(GFP_ATOMIC); 437 if (!tcep) { 438 local_irq_enable(); 439 return -ENOMEM; 440 } 441 __this_cpu_write(tce_page, tcep); 442 } 443 444 proto_tce = TCE_PCI_READ | TCE_PCI_WRITE; 445 446 liobn = (u64)be32_to_cpu(maprange->liobn); 447 tce_shift = be32_to_cpu(maprange->tce_shift); 448 tce_size = 1ULL << tce_shift; 449 next = start_pfn << PAGE_SHIFT; 450 num_tce = num_pfn << PAGE_SHIFT; 451 452 /* round back to the beginning of the tce page size */ 453 num_tce += next & (tce_size - 1); 454 next &= ~(tce_size - 1); 455 456 /* covert to number of tces */ 457 num_tce |= tce_size - 1; 458 num_tce >>= tce_shift; 459 460 /* We can map max one pageful of TCEs at a time */ 461 do { 462 /* 463 * Set up the page with TCE data, looping through and setting 464 * the values. 465 */ 466 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE); 467 dma_offset = next + be64_to_cpu(maprange->dma_base); 468 469 for (l = 0; l < limit; l++) { 470 tcep[l] = cpu_to_be64(proto_tce | next); 471 next += tce_size; 472 } 473 474 rc = plpar_tce_put_indirect(liobn, 475 dma_offset, 476 (u64)__pa(tcep), 477 limit); 478 479 num_tce -= limit; 480 } while (num_tce > 0 && !rc); 481 482 /* error cleanup: caller will clear whole range */ 483 484 local_irq_enable(); 485 return rc; 486} 487 488static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn, 489 unsigned long num_pfn, void *arg) 490{ 491 return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg); 492} 493 494static void iommu_table_setparms(struct pci_controller *phb, 495 struct device_node *dn, 496 struct iommu_table *tbl) 497{ 498 struct device_node *node; 499 const unsigned long *basep; 500 const u32 *sizep; 501 502 node = phb->dn; 503 504 basep = of_get_property(node, "linux,tce-base", NULL); 505 sizep = of_get_property(node, "linux,tce-size", NULL); 506 if (basep == NULL || sizep == NULL) { 507 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %pOF has " 508 "missing tce entries !\n", dn); 509 return; 510 } 511 512 tbl->it_base = (unsigned long)__va(*basep); 513 514 if (!is_kdump_kernel()) 515 memset((void *)tbl->it_base, 0, *sizep); 516 517 tbl->it_busno = phb->bus->number; 518 tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K; 519 520 /* Units of tce entries */ 521 tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift; 522 523 /* Test if we are going over 2GB of DMA space */ 524 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { 525 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 526 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 527 } 528 529 phb->dma_window_base_cur += phb->dma_window_size; 530 531 /* Set the tce table size - measured in entries */ 532 tbl->it_size = phb->dma_window_size >> tbl->it_page_shift; 533 534 tbl->it_index = 0; 535 tbl->it_blocksize = 16; 536 tbl->it_type = TCE_PCI; 537} 538 539/* 540 * iommu_table_setparms_lpar 541 * 542 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. 543 */ 544static void iommu_table_setparms_lpar(struct pci_controller *phb, 545 struct device_node *dn, 546 struct iommu_table *tbl, 547 struct iommu_table_group *table_group, 548 const __be32 *dma_window) 549{ 550 unsigned long offset, size; 551 552 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); 553 554 tbl->it_busno = phb->bus->number; 555 tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K; 556 tbl->it_base = 0; 557 tbl->it_blocksize = 16; 558 tbl->it_type = TCE_PCI; 559 tbl->it_offset = offset >> tbl->it_page_shift; 560 tbl->it_size = size >> tbl->it_page_shift; 561 562 table_group->tce32_start = offset; 563 table_group->tce32_size = size; 564} 565 566struct iommu_table_ops iommu_table_pseries_ops = { 567 .set = tce_build_pSeries, 568 .clear = tce_free_pSeries, 569 .get = tce_get_pseries 570}; 571 572static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) 573{ 574 struct device_node *dn; 575 struct iommu_table *tbl; 576 struct device_node *isa_dn, *isa_dn_orig; 577 struct device_node *tmp; 578 struct pci_dn *pci; 579 int children; 580 581 dn = pci_bus_to_OF_node(bus); 582 583 pr_debug("pci_dma_bus_setup_pSeries: setting up bus %pOF\n", dn); 584 585 if (bus->self) { 586 /* This is not a root bus, any setup will be done for the 587 * device-side of the bridge in iommu_dev_setup_pSeries(). 588 */ 589 return; 590 } 591 pci = PCI_DN(dn); 592 593 /* Check if the ISA bus on the system is under 594 * this PHB. 595 */ 596 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); 597 598 while (isa_dn && isa_dn != dn) 599 isa_dn = isa_dn->parent; 600 601 of_node_put(isa_dn_orig); 602 603 /* Count number of direct PCI children of the PHB. */ 604 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) 605 children++; 606 607 pr_debug("Children: %d\n", children); 608 609 /* Calculate amount of DMA window per slot. Each window must be 610 * a power of two (due to pci_alloc_consistent requirements). 611 * 612 * Keep 256MB aside for PHBs with ISA. 613 */ 614 615 if (!isa_dn) { 616 /* No ISA/IDE - just set window size and return */ 617 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ 618 619 while (pci->phb->dma_window_size * children > 0x80000000ul) 620 pci->phb->dma_window_size >>= 1; 621 pr_debug("No ISA/IDE, window size is 0x%llx\n", 622 pci->phb->dma_window_size); 623 pci->phb->dma_window_base_cur = 0; 624 625 return; 626 } 627 628 /* If we have ISA, then we probably have an IDE 629 * controller too. Allocate a 128MB table but 630 * skip the first 128MB to avoid stepping on ISA 631 * space. 632 */ 633 pci->phb->dma_window_size = 0x8000000ul; 634 pci->phb->dma_window_base_cur = 0x8000000ul; 635 636 pci->table_group = iommu_pseries_alloc_group(pci->phb->node); 637 tbl = pci->table_group->tables[0]; 638 639 iommu_table_setparms(pci->phb, dn, tbl); 640 tbl->it_ops = &iommu_table_pseries_ops; 641 iommu_init_table(tbl, pci->phb->node, 0, 0); 642 643 /* Divide the rest (1.75GB) among the children */ 644 pci->phb->dma_window_size = 0x80000000ul; 645 while (pci->phb->dma_window_size * children > 0x70000000ul) 646 pci->phb->dma_window_size >>= 1; 647 648 pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size); 649} 650 651#ifdef CONFIG_IOMMU_API 652static int tce_exchange_pseries(struct iommu_table *tbl, long index, unsigned 653 long *tce, enum dma_data_direction *direction, 654 bool realmode) 655{ 656 long rc; 657 unsigned long ioba = (unsigned long) index << tbl->it_page_shift; 658 unsigned long flags, oldtce = 0; 659 u64 proto_tce = iommu_direction_to_tce_perm(*direction); 660 unsigned long newtce = *tce | proto_tce; 661 662 spin_lock_irqsave(&tbl->large_pool.lock, flags); 663 664 rc = plpar_tce_get((u64)tbl->it_index, ioba, &oldtce); 665 if (!rc) 666 rc = plpar_tce_put((u64)tbl->it_index, ioba, newtce); 667 668 if (!rc) { 669 *direction = iommu_tce_direction(oldtce); 670 *tce = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE); 671 } 672 673 spin_unlock_irqrestore(&tbl->large_pool.lock, flags); 674 675 return rc; 676} 677#endif 678 679struct iommu_table_ops iommu_table_lpar_multi_ops = { 680 .set = tce_buildmulti_pSeriesLP, 681#ifdef CONFIG_IOMMU_API 682 .xchg_no_kill = tce_exchange_pseries, 683#endif 684 .clear = tce_freemulti_pSeriesLP, 685 .get = tce_get_pSeriesLP 686}; 687 688static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) 689{ 690 struct iommu_table *tbl; 691 struct device_node *dn, *pdn; 692 struct pci_dn *ppci; 693 const __be32 *dma_window = NULL; 694 695 dn = pci_bus_to_OF_node(bus); 696 697 pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %pOF\n", 698 dn); 699 700 /* Find nearest ibm,dma-window, walking up the device tree */ 701 for (pdn = dn; pdn != NULL; pdn = pdn->parent) { 702 dma_window = of_get_property(pdn, "ibm,dma-window", NULL); 703 if (dma_window != NULL) 704 break; 705 } 706 707 if (dma_window == NULL) { 708 pr_debug(" no ibm,dma-window property !\n"); 709 return; 710 } 711 712 ppci = PCI_DN(pdn); 713 714 pr_debug(" parent is %pOF, iommu_table: 0x%p\n", 715 pdn, ppci->table_group); 716 717 if (!ppci->table_group) { 718 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node); 719 tbl = ppci->table_group->tables[0]; 720 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, 721 ppci->table_group, dma_window); 722 tbl->it_ops = &iommu_table_lpar_multi_ops; 723 iommu_init_table(tbl, ppci->phb->node, 0, 0); 724 iommu_register_group(ppci->table_group, 725 pci_domain_nr(bus), 0); 726 pr_debug(" created table: %p\n", ppci->table_group); 727 } 728} 729 730 731static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) 732{ 733 struct device_node *dn; 734 struct iommu_table *tbl; 735 736 pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); 737 738 dn = dev->dev.of_node; 739 740 /* If we're the direct child of a root bus, then we need to allocate 741 * an iommu table ourselves. The bus setup code should have setup 742 * the window sizes already. 743 */ 744 if (!dev->bus->self) { 745 struct pci_controller *phb = PCI_DN(dn)->phb; 746 747 pr_debug(" --> first child, no bridge. Allocating iommu table.\n"); 748 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node); 749 tbl = PCI_DN(dn)->table_group->tables[0]; 750 iommu_table_setparms(phb, dn, tbl); 751 tbl->it_ops = &iommu_table_pseries_ops; 752 iommu_init_table(tbl, phb->node, 0, 0); 753 set_iommu_table_base(&dev->dev, tbl); 754 return; 755 } 756 757 /* If this device is further down the bus tree, search upwards until 758 * an already allocated iommu table is found and use that. 759 */ 760 761 while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL) 762 dn = dn->parent; 763 764 if (dn && PCI_DN(dn)) 765 set_iommu_table_base(&dev->dev, 766 PCI_DN(dn)->table_group->tables[0]); 767 else 768 printk(KERN_WARNING "iommu: Device %s has no iommu table\n", 769 pci_name(dev)); 770} 771 772static int __read_mostly disable_ddw; 773 774static int __init disable_ddw_setup(char *str) 775{ 776 disable_ddw = 1; 777 printk(KERN_INFO "ppc iommu: disabling ddw.\n"); 778 779 return 0; 780} 781 782early_param("disable_ddw", disable_ddw_setup); 783 784static void remove_dma_window(struct device_node *np, u32 *ddw_avail, 785 struct property *win) 786{ 787 struct dynamic_dma_window_prop *dwp; 788 u64 liobn; 789 int ret; 790 791 dwp = win->value; 792 liobn = (u64)be32_to_cpu(dwp->liobn); 793 794 /* clear the whole window, note the arg is in kernel pages */ 795 ret = tce_clearrange_multi_pSeriesLP(0, 796 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp); 797 if (ret) 798 pr_warn("%pOF failed to clear tces in window.\n", 799 np); 800 else 801 pr_debug("%pOF successfully cleared tces in window.\n", 802 np); 803 804 ret = rtas_call(ddw_avail[DDW_REMOVE_PE_DMA_WIN], 1, 1, NULL, liobn); 805 if (ret) 806 pr_warn("%pOF: failed to remove direct window: rtas returned " 807 "%d to ibm,remove-pe-dma-window(%x) %llx\n", 808 np, ret, ddw_avail[DDW_REMOVE_PE_DMA_WIN], liobn); 809 else 810 pr_debug("%pOF: successfully removed direct window: rtas returned " 811 "%d to ibm,remove-pe-dma-window(%x) %llx\n", 812 np, ret, ddw_avail[DDW_REMOVE_PE_DMA_WIN], liobn); 813} 814 815static void remove_ddw(struct device_node *np, bool remove_prop) 816{ 817 struct property *win; 818 u32 ddw_avail[DDW_APPLICABLE_SIZE]; 819 int ret = 0; 820 821 ret = of_property_read_u32_array(np, "ibm,ddw-applicable", 822 &ddw_avail[0], DDW_APPLICABLE_SIZE); 823 if (ret) 824 return; 825 826 win = of_find_property(np, DIRECT64_PROPNAME, NULL); 827 if (!win) 828 return; 829 830 if (win->length >= sizeof(struct dynamic_dma_window_prop)) 831 remove_dma_window(np, ddw_avail, win); 832 833 if (!remove_prop) 834 return; 835 836 ret = of_remove_property(np, win); 837 if (ret) 838 pr_warn("%pOF: failed to remove direct window property: %d\n", 839 np, ret); 840} 841 842static u64 find_existing_ddw(struct device_node *pdn) 843{ 844 struct direct_window *window; 845 const struct dynamic_dma_window_prop *direct64; 846 u64 dma_addr = 0; 847 848 spin_lock(&direct_window_list_lock); 849 /* check if we already created a window and dupe that config if so */ 850 list_for_each_entry(window, &direct_window_list, list) { 851 if (window->device == pdn) { 852 direct64 = window->prop; 853 dma_addr = be64_to_cpu(direct64->dma_base); 854 break; 855 } 856 } 857 spin_unlock(&direct_window_list_lock); 858 859 return dma_addr; 860} 861 862static int find_existing_ddw_windows(void) 863{ 864 int len; 865 struct device_node *pdn; 866 struct direct_window *window; 867 const struct dynamic_dma_window_prop *direct64; 868 869 if (!firmware_has_feature(FW_FEATURE_LPAR)) 870 return 0; 871 872 for_each_node_with_property(pdn, DIRECT64_PROPNAME) { 873 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len); 874 if (!direct64) 875 continue; 876 877 window = kzalloc(sizeof(*window), GFP_KERNEL); 878 if (!window || len < sizeof(struct dynamic_dma_window_prop)) { 879 kfree(window); 880 remove_ddw(pdn, true); 881 continue; 882 } 883 884 window->device = pdn; 885 window->prop = direct64; 886 spin_lock(&direct_window_list_lock); 887 list_add(&window->list, &direct_window_list); 888 spin_unlock(&direct_window_list_lock); 889 } 890 891 return 0; 892} 893machine_arch_initcall(pseries, find_existing_ddw_windows); 894 895/** 896 * ddw_read_ext - Get the value of an DDW extension 897 * @np: device node from which the extension value is to be read. 898 * @extnum: index number of the extension. 899 * @value: pointer to return value, modified when extension is available. 900 * 901 * Checks if "ibm,ddw-extensions" exists for this node, and get the value 902 * on index 'extnum'. 903 * It can be used only to check if a property exists, passing value == NULL. 904 * 905 * Returns: 906 * 0 if extension successfully read 907 * -EINVAL if the "ibm,ddw-extensions" does not exist, 908 * -ENODATA if "ibm,ddw-extensions" does not have a value, and 909 * -EOVERFLOW if "ibm,ddw-extensions" does not contain this extension. 910 */ 911static inline int ddw_read_ext(const struct device_node *np, int extnum, 912 u32 *value) 913{ 914 static const char propname[] = "ibm,ddw-extensions"; 915 u32 count; 916 int ret; 917 918 ret = of_property_read_u32_index(np, propname, DDW_EXT_SIZE, &count); 919 if (ret) 920 return ret; 921 922 if (count < extnum) 923 return -EOVERFLOW; 924 925 if (!value) 926 value = &count; 927 928 return of_property_read_u32_index(np, propname, extnum, value); 929} 930 931static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail, 932 struct ddw_query_response *query, 933 struct device_node *parent) 934{ 935 struct device_node *dn; 936 struct pci_dn *pdn; 937 u32 cfg_addr, ext_query, query_out[5]; 938 u64 buid; 939 int ret, out_sz; 940 941 /* 942 * From LoPAR level 2.8, "ibm,ddw-extensions" index 3 can rule how many 943 * output parameters ibm,query-pe-dma-windows will have, ranging from 944 * 5 to 6. 945 */ 946 ret = ddw_read_ext(parent, DDW_EXT_QUERY_OUT_SIZE, &ext_query); 947 if (!ret && ext_query == 1) 948 out_sz = 6; 949 else 950 out_sz = 5; 951 952 /* 953 * Get the config address and phb buid of the PE window. 954 * Rely on eeh to retrieve this for us. 955 * Retrieve them from the pci device, not the node with the 956 * dma-window property 957 */ 958 dn = pci_device_to_OF_node(dev); 959 pdn = PCI_DN(dn); 960 buid = pdn->phb->buid; 961 cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8)); 962 963 ret = rtas_call(ddw_avail[DDW_QUERY_PE_DMA_WIN], 3, out_sz, query_out, 964 cfg_addr, BUID_HI(buid), BUID_LO(buid)); 965 dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x returned %d\n", 966 ddw_avail[DDW_QUERY_PE_DMA_WIN], cfg_addr, BUID_HI(buid), 967 BUID_LO(buid), ret); 968 969 switch (out_sz) { 970 case 5: 971 query->windows_available = query_out[0]; 972 query->largest_available_block = query_out[1]; 973 query->page_size = query_out[2]; 974 query->migration_capable = query_out[3]; 975 break; 976 case 6: 977 query->windows_available = query_out[0]; 978 query->largest_available_block = ((u64)query_out[1] << 32) | 979 query_out[2]; 980 query->page_size = query_out[3]; 981 query->migration_capable = query_out[4]; 982 break; 983 } 984 985 return ret; 986} 987 988static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail, 989 struct ddw_create_response *create, int page_shift, 990 int window_shift) 991{ 992 struct device_node *dn; 993 struct pci_dn *pdn; 994 u32 cfg_addr; 995 u64 buid; 996 int ret; 997 998 /* 999 * Get the config address and phb buid of the PE window. 1000 * Rely on eeh to retrieve this for us. 1001 * Retrieve them from the pci device, not the node with the 1002 * dma-window property 1003 */ 1004 dn = pci_device_to_OF_node(dev); 1005 pdn = PCI_DN(dn); 1006 buid = pdn->phb->buid; 1007 cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8)); 1008 1009 do { 1010 /* extra outputs are LIOBN and dma-addr (hi, lo) */ 1011 ret = rtas_call(ddw_avail[DDW_CREATE_PE_DMA_WIN], 5, 4, 1012 (u32 *)create, cfg_addr, BUID_HI(buid), 1013 BUID_LO(buid), page_shift, window_shift); 1014 } while (rtas_busy_delay(ret)); 1015 dev_info(&dev->dev, 1016 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d " 1017 "(liobn = 0x%x starting addr = %x %x)\n", 1018 ddw_avail[DDW_CREATE_PE_DMA_WIN], cfg_addr, BUID_HI(buid), 1019 BUID_LO(buid), page_shift, window_shift, ret, create->liobn, 1020 create->addr_hi, create->addr_lo); 1021 1022 return ret; 1023} 1024 1025struct failed_ddw_pdn { 1026 struct device_node *pdn; 1027 struct list_head list; 1028}; 1029 1030static LIST_HEAD(failed_ddw_pdn_list); 1031 1032static phys_addr_t ddw_memory_hotplug_max(void) 1033{ 1034 phys_addr_t max_addr = memory_hotplug_max(); 1035 struct device_node *memory; 1036 1037 for_each_node_by_type(memory, "memory") { 1038 unsigned long start, size; 1039 int n_mem_addr_cells, n_mem_size_cells, len; 1040 const __be32 *memcell_buf; 1041 1042 memcell_buf = of_get_property(memory, "reg", &len); 1043 if (!memcell_buf || len <= 0) 1044 continue; 1045 1046 n_mem_addr_cells = of_n_addr_cells(memory); 1047 n_mem_size_cells = of_n_size_cells(memory); 1048 1049 start = of_read_number(memcell_buf, n_mem_addr_cells); 1050 memcell_buf += n_mem_addr_cells; 1051 size = of_read_number(memcell_buf, n_mem_size_cells); 1052 memcell_buf += n_mem_size_cells; 1053 1054 max_addr = max_t(phys_addr_t, max_addr, start + size); 1055 } 1056 1057 return max_addr; 1058} 1059 1060/* 1061 * Platforms supporting the DDW option starting with LoPAR level 2.7 implement 1062 * ibm,ddw-extensions, which carries the rtas token for 1063 * ibm,reset-pe-dma-windows. 1064 * That rtas-call can be used to restore the default DMA window for the device. 1065 */ 1066static void reset_dma_window(struct pci_dev *dev, struct device_node *par_dn) 1067{ 1068 int ret; 1069 u32 cfg_addr, reset_dma_win; 1070 u64 buid; 1071 struct device_node *dn; 1072 struct pci_dn *pdn; 1073 1074 ret = ddw_read_ext(par_dn, DDW_EXT_RESET_DMA_WIN, &reset_dma_win); 1075 if (ret) 1076 return; 1077 1078 dn = pci_device_to_OF_node(dev); 1079 pdn = PCI_DN(dn); 1080 buid = pdn->phb->buid; 1081 cfg_addr = (pdn->busno << 16) | (pdn->devfn << 8); 1082 1083 ret = rtas_call(reset_dma_win, 3, 1, NULL, cfg_addr, BUID_HI(buid), 1084 BUID_LO(buid)); 1085 if (ret) 1086 dev_info(&dev->dev, 1087 "ibm,reset-pe-dma-windows(%x) %x %x %x returned %d ", 1088 reset_dma_win, cfg_addr, BUID_HI(buid), BUID_LO(buid), 1089 ret); 1090} 1091 1092/* 1093 * If the PE supports dynamic dma windows, and there is space for a table 1094 * that can map all pages in a linear offset, then setup such a table, 1095 * and record the dma-offset in the struct device. 1096 * 1097 * dev: the pci device we are checking 1098 * pdn: the parent pe node with the ibm,dma_window property 1099 * Future: also check if we can remap the base window for our base page size 1100 * 1101 * returns the dma offset for use by the direct mapped DMA code. 1102 */ 1103static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn) 1104{ 1105 int len, ret; 1106 struct ddw_query_response query; 1107 struct ddw_create_response create; 1108 int page_shift; 1109 u64 dma_addr, max_addr; 1110 struct device_node *dn; 1111 u32 ddw_avail[DDW_APPLICABLE_SIZE]; 1112 struct direct_window *window; 1113 struct property *win64; 1114 struct dynamic_dma_window_prop *ddwprop; 1115 struct failed_ddw_pdn *fpdn; 1116 bool default_win_removed = false; 1117 1118 mutex_lock(&direct_window_init_mutex); 1119 1120 dma_addr = find_existing_ddw(pdn); 1121 if (dma_addr != 0) 1122 goto out_unlock; 1123 1124 /* 1125 * If we already went through this for a previous function of 1126 * the same device and failed, we don't want to muck with the 1127 * DMA window again, as it will race with in-flight operations 1128 * and can lead to EEHs. The above mutex protects access to the 1129 * list. 1130 */ 1131 list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) { 1132 if (fpdn->pdn == pdn) 1133 goto out_unlock; 1134 } 1135 1136 /* 1137 * the ibm,ddw-applicable property holds the tokens for: 1138 * ibm,query-pe-dma-window 1139 * ibm,create-pe-dma-window 1140 * ibm,remove-pe-dma-window 1141 * for the given node in that order. 1142 * the property is actually in the parent, not the PE 1143 */ 1144 ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable", 1145 &ddw_avail[0], DDW_APPLICABLE_SIZE); 1146 if (ret) 1147 goto out_failed; 1148 1149 /* 1150 * Query if there is a second window of size to map the 1151 * whole partition. Query returns number of windows, largest 1152 * block assigned to PE (partition endpoint), and two bitmasks 1153 * of page sizes: supported and supported for migrate-dma. 1154 */ 1155 dn = pci_device_to_OF_node(dev); 1156 ret = query_ddw(dev, ddw_avail, &query, pdn); 1157 if (ret != 0) 1158 goto out_failed; 1159 1160 /* 1161 * If there is no window available, remove the default DMA window, 1162 * if it's present. This will make all the resources available to the 1163 * new DDW window. 1164 * If anything fails after this, we need to restore it, so also check 1165 * for extensions presence. 1166 */ 1167 if (query.windows_available == 0) { 1168 struct property *default_win; 1169 int reset_win_ext; 1170 1171 default_win = of_find_property(pdn, "ibm,dma-window", NULL); 1172 if (!default_win) 1173 goto out_failed; 1174 1175 reset_win_ext = ddw_read_ext(pdn, DDW_EXT_RESET_DMA_WIN, NULL); 1176 if (reset_win_ext) 1177 goto out_failed; 1178 1179 remove_dma_window(pdn, ddw_avail, default_win); 1180 default_win_removed = true; 1181 1182 /* Query again, to check if the window is available */ 1183 ret = query_ddw(dev, ddw_avail, &query, pdn); 1184 if (ret != 0) 1185 goto out_failed; 1186 1187 if (query.windows_available == 0) { 1188 /* no windows are available for this device. */ 1189 dev_dbg(&dev->dev, "no free dynamic windows"); 1190 goto out_failed; 1191 } 1192 } 1193 if (query.page_size & 4) { 1194 page_shift = 24; /* 16MB */ 1195 } else if (query.page_size & 2) { 1196 page_shift = 16; /* 64kB */ 1197 } else if (query.page_size & 1) { 1198 page_shift = 12; /* 4kB */ 1199 } else { 1200 dev_dbg(&dev->dev, "no supported direct page size in mask %x", 1201 query.page_size); 1202 goto out_failed; 1203 } 1204 /* verify the window * number of ptes will map the partition */ 1205 /* check largest block * page size > max memory hotplug addr */ 1206 max_addr = ddw_memory_hotplug_max(); 1207 if (query.largest_available_block < (max_addr >> page_shift)) { 1208 dev_dbg(&dev->dev, "can't map partition max 0x%llx with %llu " 1209 "%llu-sized pages\n", max_addr, query.largest_available_block, 1210 1ULL << page_shift); 1211 goto out_failed; 1212 } 1213 len = order_base_2(max_addr); 1214 win64 = kzalloc(sizeof(struct property), GFP_KERNEL); 1215 if (!win64) { 1216 dev_info(&dev->dev, 1217 "couldn't allocate property for 64bit dma window\n"); 1218 goto out_failed; 1219 } 1220 win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL); 1221 win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL); 1222 win64->length = sizeof(*ddwprop); 1223 if (!win64->name || !win64->value) { 1224 dev_info(&dev->dev, 1225 "couldn't allocate property name and value\n"); 1226 goto out_free_prop; 1227 } 1228 1229 ret = create_ddw(dev, ddw_avail, &create, page_shift, len); 1230 if (ret != 0) 1231 goto out_free_prop; 1232 1233 ddwprop->liobn = cpu_to_be32(create.liobn); 1234 ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) | 1235 create.addr_lo); 1236 ddwprop->tce_shift = cpu_to_be32(page_shift); 1237 ddwprop->window_shift = cpu_to_be32(len); 1238 1239 dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %pOF\n", 1240 create.liobn, dn); 1241 1242 window = kzalloc(sizeof(*window), GFP_KERNEL); 1243 if (!window) 1244 goto out_clear_window; 1245 1246 ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT, 1247 win64->value, tce_setrange_multi_pSeriesLP_walk); 1248 if (ret) { 1249 dev_info(&dev->dev, "failed to map direct window for %pOF: %d\n", 1250 dn, ret); 1251 goto out_free_window; 1252 } 1253 1254 ret = of_add_property(pdn, win64); 1255 if (ret) { 1256 dev_err(&dev->dev, "unable to add dma window property for %pOF: %d", 1257 pdn, ret); 1258 goto out_free_window; 1259 } 1260 1261 window->device = pdn; 1262 window->prop = ddwprop; 1263 spin_lock(&direct_window_list_lock); 1264 list_add(&window->list, &direct_window_list); 1265 spin_unlock(&direct_window_list_lock); 1266 1267 dma_addr = be64_to_cpu(ddwprop->dma_base); 1268 goto out_unlock; 1269 1270out_free_window: 1271 kfree(window); 1272 1273out_clear_window: 1274 remove_ddw(pdn, true); 1275 1276out_free_prop: 1277 kfree(win64->name); 1278 kfree(win64->value); 1279 kfree(win64); 1280 1281out_failed: 1282 if (default_win_removed) 1283 reset_dma_window(dev, pdn); 1284 1285 fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL); 1286 if (!fpdn) 1287 goto out_unlock; 1288 fpdn->pdn = pdn; 1289 list_add(&fpdn->list, &failed_ddw_pdn_list); 1290 1291out_unlock: 1292 mutex_unlock(&direct_window_init_mutex); 1293 return dma_addr; 1294} 1295 1296static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) 1297{ 1298 struct device_node *pdn, *dn; 1299 struct iommu_table *tbl; 1300 const __be32 *dma_window = NULL; 1301 struct pci_dn *pci; 1302 1303 pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); 1304 1305 /* dev setup for LPAR is a little tricky, since the device tree might 1306 * contain the dma-window properties per-device and not necessarily 1307 * for the bus. So we need to search upwards in the tree until we 1308 * either hit a dma-window property, OR find a parent with a table 1309 * already allocated. 1310 */ 1311 dn = pci_device_to_OF_node(dev); 1312 pr_debug(" node is %pOF\n", dn); 1313 1314 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group; 1315 pdn = pdn->parent) { 1316 dma_window = of_get_property(pdn, "ibm,dma-window", NULL); 1317 if (dma_window) 1318 break; 1319 } 1320 1321 if (!pdn || !PCI_DN(pdn)) { 1322 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: " 1323 "no DMA window found for pci dev=%s dn=%pOF\n", 1324 pci_name(dev), dn); 1325 return; 1326 } 1327 pr_debug(" parent is %pOF\n", pdn); 1328 1329 pci = PCI_DN(pdn); 1330 if (!pci->table_group) { 1331 pci->table_group = iommu_pseries_alloc_group(pci->phb->node); 1332 tbl = pci->table_group->tables[0]; 1333 iommu_table_setparms_lpar(pci->phb, pdn, tbl, 1334 pci->table_group, dma_window); 1335 tbl->it_ops = &iommu_table_lpar_multi_ops; 1336 iommu_init_table(tbl, pci->phb->node, 0, 0); 1337 iommu_register_group(pci->table_group, 1338 pci_domain_nr(pci->phb->bus), 0); 1339 pr_debug(" created table: %p\n", pci->table_group); 1340 } else { 1341 pr_debug(" found DMA window, table: %p\n", pci->table_group); 1342 } 1343 1344 set_iommu_table_base(&dev->dev, pci->table_group->tables[0]); 1345 iommu_add_device(pci->table_group, &dev->dev); 1346} 1347 1348static bool iommu_bypass_supported_pSeriesLP(struct pci_dev *pdev, u64 dma_mask) 1349{ 1350 struct device_node *dn = pci_device_to_OF_node(pdev), *pdn; 1351 const __be32 *dma_window = NULL; 1352 1353 /* only attempt to use a new window if 64-bit DMA is requested */ 1354 if (dma_mask < DMA_BIT_MASK(64)) 1355 return false; 1356 1357 dev_dbg(&pdev->dev, "node is %pOF\n", dn); 1358 1359 /* 1360 * the device tree might contain the dma-window properties 1361 * per-device and not necessarily for the bus. So we need to 1362 * search upwards in the tree until we either hit a dma-window 1363 * property, OR find a parent with a table already allocated. 1364 */ 1365 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group; 1366 pdn = pdn->parent) { 1367 dma_window = of_get_property(pdn, "ibm,dma-window", NULL); 1368 if (dma_window) 1369 break; 1370 } 1371 1372 if (pdn && PCI_DN(pdn)) { 1373 pdev->dev.archdata.dma_offset = enable_ddw(pdev, pdn); 1374 if (pdev->dev.archdata.dma_offset) 1375 return true; 1376 } 1377 1378 return false; 1379} 1380 1381static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action, 1382 void *data) 1383{ 1384 struct direct_window *window; 1385 struct memory_notify *arg = data; 1386 int ret = 0; 1387 1388 switch (action) { 1389 case MEM_GOING_ONLINE: 1390 spin_lock(&direct_window_list_lock); 1391 list_for_each_entry(window, &direct_window_list, list) { 1392 ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn, 1393 arg->nr_pages, window->prop); 1394 /* XXX log error */ 1395 } 1396 spin_unlock(&direct_window_list_lock); 1397 break; 1398 case MEM_CANCEL_ONLINE: 1399 case MEM_OFFLINE: 1400 spin_lock(&direct_window_list_lock); 1401 list_for_each_entry(window, &direct_window_list, list) { 1402 ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn, 1403 arg->nr_pages, window->prop); 1404 /* XXX log error */ 1405 } 1406 spin_unlock(&direct_window_list_lock); 1407 break; 1408 default: 1409 break; 1410 } 1411 if (ret && action != MEM_CANCEL_ONLINE) 1412 return NOTIFY_BAD; 1413 1414 return NOTIFY_OK; 1415} 1416 1417static struct notifier_block iommu_mem_nb = { 1418 .notifier_call = iommu_mem_notifier, 1419}; 1420 1421static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data) 1422{ 1423 int err = NOTIFY_OK; 1424 struct of_reconfig_data *rd = data; 1425 struct device_node *np = rd->dn; 1426 struct pci_dn *pci = PCI_DN(np); 1427 struct direct_window *window; 1428 1429 switch (action) { 1430 case OF_RECONFIG_DETACH_NODE: 1431 /* 1432 * Removing the property will invoke the reconfig 1433 * notifier again, which causes dead-lock on the 1434 * read-write semaphore of the notifier chain. So 1435 * we have to remove the property when releasing 1436 * the device node. 1437 */ 1438 remove_ddw(np, false); 1439 if (pci && pci->table_group) 1440 iommu_pseries_free_group(pci->table_group, 1441 np->full_name); 1442 1443 spin_lock(&direct_window_list_lock); 1444 list_for_each_entry(window, &direct_window_list, list) { 1445 if (window->device == np) { 1446 list_del(&window->list); 1447 kfree(window); 1448 break; 1449 } 1450 } 1451 spin_unlock(&direct_window_list_lock); 1452 break; 1453 default: 1454 err = NOTIFY_DONE; 1455 break; 1456 } 1457 return err; 1458} 1459 1460static struct notifier_block iommu_reconfig_nb = { 1461 .notifier_call = iommu_reconfig_notifier, 1462}; 1463 1464/* These are called very early. */ 1465void iommu_init_early_pSeries(void) 1466{ 1467 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) 1468 return; 1469 1470 if (firmware_has_feature(FW_FEATURE_LPAR)) { 1471 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP; 1472 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP; 1473 if (!disable_ddw) 1474 pseries_pci_controller_ops.iommu_bypass_supported = 1475 iommu_bypass_supported_pSeriesLP; 1476 } else { 1477 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries; 1478 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries; 1479 } 1480 1481 1482 of_reconfig_notifier_register(&iommu_reconfig_nb); 1483 register_memory_notifier(&iommu_mem_nb); 1484 1485 set_pci_dma_ops(&dma_iommu_ops); 1486} 1487 1488static int __init disable_multitce(char *str) 1489{ 1490 if (strcmp(str, "off") == 0 && 1491 firmware_has_feature(FW_FEATURE_LPAR) && 1492 (firmware_has_feature(FW_FEATURE_PUT_TCE_IND) || 1493 firmware_has_feature(FW_FEATURE_STUFF_TCE))) { 1494 printk(KERN_INFO "Disabling MULTITCE firmware feature\n"); 1495 powerpc_firmware_features &= 1496 ~(FW_FEATURE_PUT_TCE_IND | FW_FEATURE_STUFF_TCE); 1497 } 1498 return 1; 1499} 1500 1501__setup("multitce=", disable_multitce); 1502 1503static int tce_iommu_bus_notifier(struct notifier_block *nb, 1504 unsigned long action, void *data) 1505{ 1506 struct device *dev = data; 1507 1508 switch (action) { 1509 case BUS_NOTIFY_DEL_DEVICE: 1510 iommu_del_device(dev); 1511 return 0; 1512 default: 1513 return 0; 1514 } 1515} 1516 1517static struct notifier_block tce_iommu_bus_nb = { 1518 .notifier_call = tce_iommu_bus_notifier, 1519}; 1520 1521static int __init tce_iommu_bus_notifier_init(void) 1522{ 1523 bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb); 1524 return 0; 1525} 1526machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init); 1527