1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * PowerNV setup code.
4 *
5 * Copyright 2011 IBM Corp.
6 */
7
8#undef DEBUG
9
10#include <linux/cpu.h>
11#include <linux/errno.h>
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/tty.h>
15#include <linux/reboot.h>
16#include <linux/init.h>
17#include <linux/console.h>
18#include <linux/delay.h>
19#include <linux/irq.h>
20#include <linux/seq_file.h>
21#include <linux/of.h>
22#include <linux/of_fdt.h>
23#include <linux/interrupt.h>
24#include <linux/bug.h>
25#include <linux/pci.h>
26#include <linux/cpufreq.h>
27#include <linux/memblock.h>
28
29#include <asm/machdep.h>
30#include <asm/firmware.h>
31#include <asm/xics.h>
32#include <asm/xive.h>
33#include <asm/opal.h>
34#include <asm/kexec.h>
35#include <asm/smp.h>
36#include <asm/tm.h>
37#include <asm/setup.h>
38#include <asm/security_features.h>
39
40#include "powernv.h"
41
42
43static bool fw_feature_is(const char *state, const char *name,
44			  struct device_node *fw_features)
45{
46	struct device_node *np;
47	bool rc = false;
48
49	np = of_get_child_by_name(fw_features, name);
50	if (np) {
51		rc = of_property_read_bool(np, state);
52		of_node_put(np);
53	}
54
55	return rc;
56}
57
58static void init_fw_feat_flags(struct device_node *np)
59{
60	if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
61		security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
62
63	if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
64		security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
65
66	if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
67		security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
68
69	if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
70		security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
71
72	if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
73		security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
74
75	if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
76		security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
77
78	if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
79		security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
80
81	if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
82		security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
83
84	/*
85	 * The features below are enabled by default, so we instead look to see
86	 * if firmware has *disabled* them, and clear them if so.
87	 */
88	if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
89		security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
90
91	if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
92		security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
93
94	if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
95		security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
96
97	if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
98		security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
99}
100
101static void pnv_setup_security_mitigations(void)
102{
103	struct device_node *np, *fw_features;
104	enum l1d_flush_type type;
105	bool enable;
106
107	/* Default to fallback in case fw-features are not available */
108	type = L1D_FLUSH_FALLBACK;
109
110	np = of_find_node_by_name(NULL, "ibm,opal");
111	fw_features = of_get_child_by_name(np, "fw-features");
112	of_node_put(np);
113
114	if (fw_features) {
115		init_fw_feat_flags(fw_features);
116		of_node_put(fw_features);
117
118		if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
119			type = L1D_FLUSH_MTTRIG;
120
121		if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
122			type = L1D_FLUSH_ORI;
123	}
124
125	/*
126	 * If we are non-Power9 bare metal, we don't need to flush on kernel
127	 * entry or after user access: they fix a P9 specific vulnerability.
128	 */
129	if (!pvr_version_is(PVR_POWER9)) {
130		security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
131		security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
132	}
133
134	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
135		 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR)   || \
136		  security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
137
138	setup_rfi_flush(type, enable);
139	setup_count_cache_flush();
140
141	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
142		 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
143	setup_entry_flush(enable);
144
145	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
146		 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
147	setup_uaccess_flush(enable);
148
149	setup_stf_barrier();
150}
151
152static void __init pnv_check_guarded_cores(void)
153{
154	struct device_node *dn;
155	int bad_count = 0;
156
157	for_each_node_by_type(dn, "cpu") {
158		if (of_property_match_string(dn, "status", "bad") >= 0)
159			bad_count++;
160	};
161
162	if (bad_count) {
163		printk("  _     _______________\n");
164		pr_cont(" | |   /               \\\n");
165		pr_cont(" | |   |    WARNING!   |\n");
166		pr_cont(" | |   |               |\n");
167		pr_cont(" | |   | It looks like |\n");
168		pr_cont(" |_|   |  you have %*d |\n", 3, bad_count);
169		pr_cont("  _    | guarded cores |\n");
170		pr_cont(" (_)   \\_______________/\n");
171	}
172}
173
174static void __init pnv_setup_arch(void)
175{
176	set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
177
178	pnv_setup_security_mitigations();
179
180	/* Initialize SMP */
181	pnv_smp_init();
182
183	/* Setup PCI */
184	pnv_pci_init();
185
186	/* Setup RTC and NVRAM callbacks */
187	if (firmware_has_feature(FW_FEATURE_OPAL))
188		opal_nvram_init();
189
190	/* Enable NAP mode */
191	powersave_nap = 1;
192
193	pnv_check_guarded_cores();
194
195	/* XXX PMCS */
196
197	pnv_rng_init();
198}
199
200static void __init pnv_init(void)
201{
202	/*
203	 * Initialize the LPC bus now so that legacy serial
204	 * ports can be found on it
205	 */
206	opal_lpc_init();
207
208#ifdef CONFIG_HVC_OPAL
209	if (firmware_has_feature(FW_FEATURE_OPAL))
210		hvc_opal_init_early();
211	else
212#endif
213		add_preferred_console("hvc", 0, NULL);
214
215	if (!radix_enabled()) {
216		size_t size = sizeof(struct slb_entry) * mmu_slb_size;
217		int i;
218
219		/* Allocate per cpu area to save old slb contents during MCE */
220		for_each_possible_cpu(i) {
221			paca_ptrs[i]->mce_faulty_slbs =
222					memblock_alloc_node(size,
223						__alignof__(struct slb_entry),
224						cpu_to_node(i));
225		}
226	}
227}
228
229static void __init pnv_init_IRQ(void)
230{
231	/* Try using a XIVE if available, otherwise use a XICS */
232	if (!xive_native_init())
233		xics_init();
234
235	WARN_ON(!ppc_md.get_irq);
236}
237
238static void pnv_show_cpuinfo(struct seq_file *m)
239{
240	struct device_node *root;
241	const char *model = "";
242
243	root = of_find_node_by_path("/");
244	if (root)
245		model = of_get_property(root, "model", NULL);
246	seq_printf(m, "machine\t\t: PowerNV %s\n", model);
247	if (firmware_has_feature(FW_FEATURE_OPAL))
248		seq_printf(m, "firmware\t: OPAL\n");
249	else
250		seq_printf(m, "firmware\t: BML\n");
251	of_node_put(root);
252	if (radix_enabled())
253		seq_printf(m, "MMU\t\t: Radix\n");
254	else
255		seq_printf(m, "MMU\t\t: Hash\n");
256}
257
258static void pnv_prepare_going_down(void)
259{
260	/*
261	 * Disable all notifiers from OPAL, we can't
262	 * service interrupts anymore anyway
263	 */
264	opal_event_shutdown();
265
266	/* Print flash update message if one is scheduled. */
267	opal_flash_update_print_message();
268
269	smp_send_stop();
270
271	hard_irq_disable();
272}
273
274static void  __noreturn pnv_restart(char *cmd)
275{
276	long rc;
277
278	pnv_prepare_going_down();
279
280	do {
281		if (!cmd || !strlen(cmd))
282			rc = opal_cec_reboot();
283		else if (strcmp(cmd, "full") == 0)
284			rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL);
285		else if (strcmp(cmd, "mpipl") == 0)
286			rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL);
287		else if (strcmp(cmd, "error") == 0)
288			rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL);
289		else if (strcmp(cmd, "fast") == 0)
290			rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL);
291		else
292			rc = OPAL_UNSUPPORTED;
293
294		if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
295			/* Opal is busy wait for some time and retry */
296			opal_poll_events(NULL);
297			mdelay(10);
298
299		} else	if (cmd && rc) {
300			/* Unknown error while issuing reboot */
301			if (rc == OPAL_UNSUPPORTED)
302				pr_err("Unsupported '%s' reboot.\n", cmd);
303			else
304				pr_err("Unable to issue '%s' reboot. Err=%ld\n",
305				       cmd, rc);
306			pr_info("Forcing a cec-reboot\n");
307			cmd = NULL;
308			rc = OPAL_BUSY;
309
310		} else if (rc != OPAL_SUCCESS) {
311			/* Unknown error while issuing cec-reboot */
312			pr_err("Unable to reboot. Err=%ld\n", rc);
313		}
314
315	} while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT);
316
317	for (;;)
318		opal_poll_events(NULL);
319}
320
321static void __noreturn pnv_power_off(void)
322{
323	long rc = OPAL_BUSY;
324
325	pnv_prepare_going_down();
326
327	while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
328		rc = opal_cec_power_down(0);
329		if (rc == OPAL_BUSY_EVENT)
330			opal_poll_events(NULL);
331		else
332			mdelay(10);
333	}
334	for (;;)
335		opal_poll_events(NULL);
336}
337
338static void __noreturn pnv_halt(void)
339{
340	pnv_power_off();
341}
342
343static void pnv_progress(char *s, unsigned short hex)
344{
345}
346
347static void pnv_shutdown(void)
348{
349	/* Let the PCI code clear up IODA tables */
350	pnv_pci_shutdown();
351
352	/*
353	 * Stop OPAL activity: Unregister all OPAL interrupts so they
354	 * don't fire up while we kexec and make sure all potentially
355	 * DMA'ing ops are complete (such as dump retrieval).
356	 */
357	opal_shutdown();
358}
359
360#ifdef CONFIG_KEXEC_CORE
361static void pnv_kexec_wait_secondaries_down(void)
362{
363	int my_cpu, i, notified = -1;
364
365	my_cpu = get_cpu();
366
367	for_each_online_cpu(i) {
368		uint8_t status;
369		int64_t rc, timeout = 1000;
370
371		if (i == my_cpu)
372			continue;
373
374		for (;;) {
375			rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
376						   &status);
377			if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
378				break;
379			barrier();
380			if (i != notified) {
381				printk(KERN_INFO "kexec: waiting for cpu %d "
382				       "(physical %d) to enter OPAL\n",
383				       i, paca_ptrs[i]->hw_cpu_id);
384				notified = i;
385			}
386
387			/*
388			 * On crash secondaries might be unreachable or hung,
389			 * so timeout if we've waited too long
390			 * */
391			mdelay(1);
392			if (timeout-- == 0) {
393				printk(KERN_ERR "kexec: timed out waiting for "
394				       "cpu %d (physical %d) to enter OPAL\n",
395				       i, paca_ptrs[i]->hw_cpu_id);
396				break;
397			}
398		}
399	}
400}
401
402static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
403{
404	u64 reinit_flags;
405
406	if (xive_enabled())
407		xive_teardown_cpu();
408	else
409		xics_kexec_teardown_cpu(secondary);
410
411	/* On OPAL, we return all CPUs to firmware */
412	if (!firmware_has_feature(FW_FEATURE_OPAL))
413		return;
414
415	if (secondary) {
416		/* Return secondary CPUs to firmware on OPAL v3 */
417		mb();
418		get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
419		mb();
420
421		/* Return the CPU to OPAL */
422		opal_return_cpu();
423	} else {
424		/* Primary waits for the secondaries to have reached OPAL */
425		pnv_kexec_wait_secondaries_down();
426
427		/* Switch XIVE back to emulation mode */
428		if (xive_enabled())
429			xive_shutdown();
430
431		/*
432		 * We might be running as little-endian - now that interrupts
433		 * are disabled, reset the HILE bit to big-endian so we don't
434		 * take interrupts in the wrong endian later
435		 *
436		 * We reinit to enable both radix and hash on P9 to ensure
437		 * the mode used by the next kernel is always supported.
438		 */
439		reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
440		if (cpu_has_feature(CPU_FTR_ARCH_300))
441			reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
442				OPAL_REINIT_CPUS_MMU_HASH;
443		opal_reinit_cpus(reinit_flags);
444	}
445}
446#endif /* CONFIG_KEXEC_CORE */
447
448#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
449static unsigned long pnv_memory_block_size(void)
450{
451	/*
452	 * We map the kernel linear region with 1GB large pages on radix. For
453	 * memory hot unplug to work our memory block size must be at least
454	 * this size.
455	 */
456	if (radix_enabled())
457		return radix_mem_block_size;
458	else
459		return 256UL * 1024 * 1024;
460}
461#endif
462
463static void __init pnv_setup_machdep_opal(void)
464{
465	ppc_md.get_boot_time = opal_get_boot_time;
466	ppc_md.restart = pnv_restart;
467	pm_power_off = pnv_power_off;
468	ppc_md.halt = pnv_halt;
469	/* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
470	ppc_md.machine_check_exception = opal_machine_check;
471	ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
472	if (opal_check_token(OPAL_HANDLE_HMI2))
473		ppc_md.hmi_exception_early = opal_hmi_exception_early2;
474	else
475		ppc_md.hmi_exception_early = opal_hmi_exception_early;
476	ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
477}
478
479static int __init pnv_probe(void)
480{
481	if (!of_machine_is_compatible("ibm,powernv"))
482		return 0;
483
484	if (firmware_has_feature(FW_FEATURE_OPAL))
485		pnv_setup_machdep_opal();
486
487	pr_debug("PowerNV detected !\n");
488
489	pnv_init();
490
491	return 1;
492}
493
494#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
495void __init pnv_tm_init(void)
496{
497	if (!firmware_has_feature(FW_FEATURE_OPAL) ||
498	    !pvr_version_is(PVR_POWER9) ||
499	    early_cpu_has_feature(CPU_FTR_TM))
500		return;
501
502	if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
503		return;
504
505	pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
506	cur_cpu_spec->cpu_features |= CPU_FTR_TM;
507	/* Make sure "normal" HTM is off (it should be) */
508	cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
509	/* Turn on no suspend mode, and HTM no SC */
510	cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \
511					    PPC_FEATURE2_HTM_NOSC;
512	tm_suspend_disabled = true;
513}
514#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
515
516/*
517 * Returns the cpu frequency for 'cpu' in Hz. This is used by
518 * /proc/cpuinfo
519 */
520static unsigned long pnv_get_proc_freq(unsigned int cpu)
521{
522	unsigned long ret_freq;
523
524	ret_freq = cpufreq_get(cpu) * 1000ul;
525
526	/*
527	 * If the backend cpufreq driver does not exist,
528         * then fallback to old way of reporting the clockrate.
529	 */
530	if (!ret_freq)
531		ret_freq = ppc_proc_freq;
532	return ret_freq;
533}
534
535static long pnv_machine_check_early(struct pt_regs *regs)
536{
537	long handled = 0;
538
539	if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
540		handled = cur_cpu_spec->machine_check_early(regs);
541
542	return handled;
543}
544
545define_machine(powernv) {
546	.name			= "PowerNV",
547	.probe			= pnv_probe,
548	.setup_arch		= pnv_setup_arch,
549	.init_IRQ		= pnv_init_IRQ,
550	.show_cpuinfo		= pnv_show_cpuinfo,
551	.get_proc_freq          = pnv_get_proc_freq,
552	.progress		= pnv_progress,
553	.machine_shutdown	= pnv_shutdown,
554	.power_save             = NULL,
555	.calibrate_decr		= generic_calibrate_decr,
556	.machine_check_early	= pnv_machine_check_early,
557#ifdef CONFIG_KEXEC_CORE
558	.kexec_cpu_down		= pnv_kexec_cpu_down,
559#endif
560#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
561	.memory_block_size	= pnv_memory_block_size,
562#endif
563};
564