1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __POWERNV_PCI_H 3#define __POWERNV_PCI_H 4 5#include <linux/compiler.h> /* for __printf */ 6#include <linux/iommu.h> 7#include <asm/iommu.h> 8#include <asm/msi_bitmap.h> 9 10struct pci_dn; 11 12enum pnv_phb_type { 13 PNV_PHB_IODA1 = 0, 14 PNV_PHB_IODA2 = 1, 15 PNV_PHB_NPU_NVLINK = 2, 16 PNV_PHB_NPU_OCAPI = 3, 17}; 18 19/* Precise PHB model for error management */ 20enum pnv_phb_model { 21 PNV_PHB_MODEL_UNKNOWN, 22 PNV_PHB_MODEL_P7IOC, 23 PNV_PHB_MODEL_PHB3, 24 PNV_PHB_MODEL_NPU, 25 PNV_PHB_MODEL_NPU2, 26}; 27 28#define PNV_PCI_DIAG_BUF_SIZE 8192 29#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 30#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 31#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 32#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 33#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 34#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 35 36/* 37 * A brief note on PNV_IODA_PE_BUS_ALL 38 * 39 * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses 40 * the Requester ID field of the PCIe request header to determine the device 41 * (and PE) that initiated a DMA. In legacy PCI individual memory read/write 42 * requests aren't tagged with the RID. To work around this the PCIe-to-PCI 43 * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side. 44 * 45 * PCIe-to-X bridges have a similar issue even though PCI-X requests also have 46 * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take 47 * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe 48 * side of the bridge. 49 * 50 * To work around these problems we use the BUS_ALL flag since every subordinate 51 * bus of the bridge should go into the same PE. 52 */ 53 54/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 55#define PNV_IODA_STOPPED_STATE 0x8000000000000000 56 57/* Data associated with a PE, including IOMMU tracking etc.. */ 58struct pnv_phb; 59struct pnv_ioda_pe { 60 unsigned long flags; 61 struct pnv_phb *phb; 62 int device_count; 63 64 /* A PE can be associated with a single device or an 65 * entire bus (& children). In the former case, pdev 66 * is populated, in the later case, pbus is. 67 */ 68#ifdef CONFIG_PCI_IOV 69 struct pci_dev *parent_dev; 70#endif 71 struct pci_dev *pdev; 72 struct pci_bus *pbus; 73 74 /* Effective RID (device RID for a device PE and base bus 75 * RID with devfn 0 for a bus PE) 76 */ 77 unsigned int rid; 78 79 /* PE number */ 80 unsigned int pe_number; 81 82 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 83 struct iommu_table_group table_group; 84 struct npu_comp *npucomp; 85 86 /* 64-bit TCE bypass region */ 87 bool tce_bypass_enabled; 88 uint64_t tce_bypass_base; 89 90 /* 91 * Used to track whether we've done DMA setup for this PE or not. We 92 * want to defer allocating TCE tables, etc until we've added a 93 * non-bridge device to the PE. 94 */ 95 bool dma_setup_done; 96 97 /* MSIs. MVE index is identical for 32 and 64 bit MSI 98 * and -1 if not supported. (It's actually identical to the 99 * PE number) 100 */ 101 int mve_number; 102 103 /* PEs in compound case */ 104 struct pnv_ioda_pe *master; 105 struct list_head slaves; 106 107 /* Link in list of PE#s */ 108 struct list_head list; 109}; 110 111#define PNV_PHB_FLAG_EEH (1 << 0) 112 113struct pnv_phb { 114 struct pci_controller *hose; 115 enum pnv_phb_type type; 116 enum pnv_phb_model model; 117 u64 hub_id; 118 u64 opal_id; 119 int flags; 120 void __iomem *regs; 121 u64 regs_phys; 122 int initialized; 123 spinlock_t lock; 124 125#ifdef CONFIG_DEBUG_FS 126 int has_dbgfs; 127 struct dentry *dbgfs; 128#endif 129 130 unsigned int msi_base; 131 unsigned int msi32_support; 132 struct msi_bitmap msi_bmp; 133 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 134 unsigned int hwirq, unsigned int virq, 135 unsigned int is_64, struct msi_msg *msg); 136 int (*init_m64)(struct pnv_phb *phb); 137 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 138 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 139 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 140 141 struct { 142 /* Global bridge info */ 143 unsigned int total_pe_num; 144 unsigned int reserved_pe_idx; 145 unsigned int root_pe_idx; 146 147 /* 32-bit MMIO window */ 148 unsigned int m32_size; 149 unsigned int m32_segsize; 150 unsigned int m32_pci_base; 151 152 /* 64-bit MMIO window */ 153 unsigned int m64_bar_idx; 154 unsigned long m64_size; 155 unsigned long m64_segsize; 156 unsigned long m64_base; 157#define MAX_M64_BARS 64 158 unsigned long m64_bar_alloc; 159 160 /* IO ports */ 161 unsigned int io_size; 162 unsigned int io_segsize; 163 unsigned int io_pci_base; 164 165 /* PE allocation */ 166 struct mutex pe_alloc_mutex; 167 unsigned long *pe_alloc; 168 struct pnv_ioda_pe *pe_array; 169 170 /* M32 & IO segment maps */ 171 unsigned int *m64_segmap; 172 unsigned int *m32_segmap; 173 unsigned int *io_segmap; 174 175 /* DMA32 segment maps - IODA1 only */ 176 unsigned int dma32_count; 177 unsigned int *dma32_segmap; 178 179 /* IRQ chip */ 180 int irq_chip_init; 181 struct irq_chip irq_chip; 182 183 /* Sorted list of used PE's based 184 * on the sequence of creation 185 */ 186 struct list_head pe_list; 187 struct mutex pe_list_mutex; 188 189 /* Reverse map of PEs, indexed by {bus, devfn} */ 190 unsigned int pe_rmap[0x10000]; 191 } ioda; 192 193 /* PHB and hub diagnostics */ 194 unsigned int diag_data_size; 195 u8 *diag_data; 196}; 197 198 199/* IODA PE management */ 200 201static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 202{ 203 /* 204 * WARNING: We cannot rely on the resource flags. The Linux PCI 205 * allocation code sometimes decides to put a 64-bit prefetchable 206 * BAR in the 32-bit window, so we have to compare the addresses. 207 * 208 * For simplicity we only test resource start. 209 */ 210 return (r->start >= phb->ioda.m64_base && 211 r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 212} 213 214static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 215{ 216 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 217 218 return (resource_flags & flags) == flags; 219} 220 221int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 222int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 223 224void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 225void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe); 226 227struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count); 228void pnv_ioda_free_pe(struct pnv_ioda_pe *pe); 229 230#ifdef CONFIG_PCI_IOV 231/* 232 * For SR-IOV we want to put each VF's MMIO resource in to a separate PE. 233 * This requires a bit of acrobatics with the MMIO -> PE configuration 234 * and this structure is used to keep track of it all. 235 */ 236struct pnv_iov_data { 237 /* number of VFs enabled */ 238 u16 num_vfs; 239 240 /* pointer to the array of VF PEs. num_vfs long*/ 241 struct pnv_ioda_pe *vf_pe_arr; 242 243 /* Did we map the VF BAR with single-PE IODA BARs? */ 244 bool m64_single_mode[PCI_SRIOV_NUM_BARS]; 245 246 /* 247 * True if we're using any segmented windows. In that case we need 248 * shift the start of the IOV resource the segment corresponding to 249 * the allocated PE. 250 */ 251 bool need_shift; 252 253 /* 254 * Bit mask used to track which m64 windows are used to map the 255 * SR-IOV BARs for this device. 256 */ 257 DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS); 258 259 /* 260 * If we map the SR-IOV BARs with a segmented window then 261 * parts of that window will be "claimed" by other PEs. 262 * 263 * "holes" here is used to reserve the leading portion 264 * of the window that is used by other (non VF) PEs. 265 */ 266 struct resource holes[PCI_SRIOV_NUM_BARS]; 267}; 268 269static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev) 270{ 271 return pdev->dev.archdata.iov_data; 272} 273 274void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev); 275resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno); 276 277int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 278int pnv_pcibios_sriov_disable(struct pci_dev *pdev); 279#endif /* CONFIG_PCI_IOV */ 280 281extern struct pci_ops pnv_pci_ops; 282 283void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 284 unsigned char *log_buff); 285int pnv_pci_cfg_read(struct pci_dn *pdn, 286 int where, int size, u32 *val); 287int pnv_pci_cfg_write(struct pci_dn *pdn, 288 int where, int size, u32 val); 289extern struct iommu_table *pnv_pci_table_alloc(int nid); 290 291extern void pnv_pci_init_ioda_hub(struct device_node *np); 292extern void pnv_pci_init_ioda2_phb(struct device_node *np); 293extern void pnv_pci_init_npu_phb(struct device_node *np); 294extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 295extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr); 296extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 297extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 298 299extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 300extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 301extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn); 302extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 303extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 304extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 305 __u64 window_size, __u32 levels); 306extern int pnv_eeh_post_init(void); 307 308__printf(3, 4) 309extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 310 const char *fmt, ...); 311#define pe_err(pe, fmt, ...) \ 312 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 313#define pe_warn(pe, fmt, ...) \ 314 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 315#define pe_info(pe, fmt, ...) \ 316 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 317 318/* Nvlink functions */ 319extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 320extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 321extern void pnv_pci_npu_setup_iommu_groups(void); 322 323/* pci-ioda-tce.c */ 324#define POWERNV_IOMMU_DEFAULT_LEVELS 2 325#define POWERNV_IOMMU_MAX_LEVELS 5 326 327extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 328 unsigned long uaddr, enum dma_data_direction direction, 329 unsigned long attrs); 330extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 331extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 332 unsigned long *hpa, enum dma_data_direction *direction, 333 bool alloc); 334extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 335 bool alloc); 336extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 337 338extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 339 __u32 page_shift, __u64 window_size, __u32 levels, 340 bool alloc_userspace_copy, struct iommu_table *tbl); 341extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 342 343extern long pnv_pci_link_table_and_group(int node, int num, 344 struct iommu_table *tbl, 345 struct iommu_table_group *table_group); 346extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 347 struct iommu_table_group *table_group); 348extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 349 void *tce_mem, u64 tce_size, 350 u64 dma_offset, unsigned int page_shift); 351 352extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 353 354static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus) 355{ 356 struct pci_controller *hose = bus->sysdata; 357 358 if (hose) 359 return hose->private_data; 360 361 return NULL; 362} 363 364#endif /* __POWERNV_PCI_H */ 365