1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * SMP support for power macintosh. 4 * 5 * We support both the old "powersurge" SMP architecture 6 * and the current Core99 (G4 PowerMac) machines. 7 * 8 * Note that we don't support the very first rev. of 9 * Apple/DayStar 2 CPUs board, the one with the funky 10 * watchdog. Hopefully, none of these should be there except 11 * maybe internally to Apple. I should probably still add some 12 * code to detect this card though and disable SMP. --BenH. 13 * 14 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) 15 * and Ben Herrenschmidt <benh@kernel.crashing.org>. 16 * 17 * Support for DayStar quad CPU cards 18 * Copyright (C) XLR8, Inc. 1994-2000 19 */ 20#include <linux/kernel.h> 21#include <linux/sched.h> 22#include <linux/sched/hotplug.h> 23#include <linux/smp.h> 24#include <linux/interrupt.h> 25#include <linux/kernel_stat.h> 26#include <linux/delay.h> 27#include <linux/init.h> 28#include <linux/spinlock.h> 29#include <linux/errno.h> 30#include <linux/hardirq.h> 31#include <linux/cpu.h> 32#include <linux/compiler.h> 33#include <linux/pgtable.h> 34 35#include <asm/ptrace.h> 36#include <linux/atomic.h> 37#include <asm/code-patching.h> 38#include <asm/irq.h> 39#include <asm/page.h> 40#include <asm/sections.h> 41#include <asm/io.h> 42#include <asm/prom.h> 43#include <asm/smp.h> 44#include <asm/machdep.h> 45#include <asm/pmac_feature.h> 46#include <asm/time.h> 47#include <asm/mpic.h> 48#include <asm/cacheflush.h> 49#include <asm/keylargo.h> 50#include <asm/pmac_low_i2c.h> 51#include <asm/pmac_pfunc.h> 52#include <asm/inst.h> 53 54#include "pmac.h" 55 56#undef DEBUG 57 58#ifdef DEBUG 59#define DBG(fmt...) udbg_printf(fmt) 60#else 61#define DBG(fmt...) 62#endif 63 64extern void __secondary_start_pmac_0(void); 65 66static void (*pmac_tb_freeze)(int freeze); 67static u64 timebase; 68static int tb_req; 69 70#ifdef CONFIG_PPC_PMAC32_PSURGE 71 72/* 73 * Powersurge (old powermac SMP) support. 74 */ 75 76/* Addresses for powersurge registers */ 77#define HAMMERHEAD_BASE 0xf8000000 78#define HHEAD_CONFIG 0x90 79#define HHEAD_SEC_INTR 0xc0 80 81/* register for interrupting the primary processor on the powersurge */ 82/* N.B. this is actually the ethernet ROM! */ 83#define PSURGE_PRI_INTR 0xf3019000 84 85/* register for storing the start address for the secondary processor */ 86/* N.B. this is the PCI config space address register for the 1st bridge */ 87#define PSURGE_START 0xf2800000 88 89/* Daystar/XLR8 4-CPU card */ 90#define PSURGE_QUAD_REG_ADDR 0xf8800000 91 92#define PSURGE_QUAD_IRQ_SET 0 93#define PSURGE_QUAD_IRQ_CLR 1 94#define PSURGE_QUAD_IRQ_PRIMARY 2 95#define PSURGE_QUAD_CKSTOP_CTL 3 96#define PSURGE_QUAD_PRIMARY_ARB 4 97#define PSURGE_QUAD_BOARD_ID 6 98#define PSURGE_QUAD_WHICH_CPU 7 99#define PSURGE_QUAD_CKSTOP_RDBK 8 100#define PSURGE_QUAD_RESET_CTL 11 101 102#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) 103#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) 104#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) 105#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 106 107/* virtual addresses for the above */ 108static volatile u8 __iomem *hhead_base; 109static volatile u8 __iomem *quad_base; 110static volatile u32 __iomem *psurge_pri_intr; 111static volatile u8 __iomem *psurge_sec_intr; 112static volatile u32 __iomem *psurge_start; 113 114/* values for psurge_type */ 115#define PSURGE_NONE -1 116#define PSURGE_DUAL 0 117#define PSURGE_QUAD_OKEE 1 118#define PSURGE_QUAD_COTTON 2 119#define PSURGE_QUAD_ICEGRASS 3 120 121/* what sort of powersurge board we have */ 122static int psurge_type = PSURGE_NONE; 123 124/* irq for secondary cpus to report */ 125static struct irq_domain *psurge_host; 126int psurge_secondary_virq; 127 128/* 129 * Set and clear IPIs for powersurge. 130 */ 131static inline void psurge_set_ipi(int cpu) 132{ 133 if (psurge_type == PSURGE_NONE) 134 return; 135 if (cpu == 0) 136 in_be32(psurge_pri_intr); 137 else if (psurge_type == PSURGE_DUAL) 138 out_8(psurge_sec_intr, 0); 139 else 140 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); 141} 142 143static inline void psurge_clr_ipi(int cpu) 144{ 145 if (cpu > 0) { 146 switch(psurge_type) { 147 case PSURGE_DUAL: 148 out_8(psurge_sec_intr, ~0); 149 case PSURGE_NONE: 150 break; 151 default: 152 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); 153 } 154 } 155} 156 157/* 158 * On powersurge (old SMP powermac architecture) we don't have 159 * separate IPIs for separate messages like openpic does. Instead 160 * use the generic demux helpers 161 * -- paulus. 162 */ 163static irqreturn_t psurge_ipi_intr(int irq, void *d) 164{ 165 psurge_clr_ipi(smp_processor_id()); 166 smp_ipi_demux(); 167 168 return IRQ_HANDLED; 169} 170 171static void smp_psurge_cause_ipi(int cpu) 172{ 173 psurge_set_ipi(cpu); 174} 175 176static int psurge_host_map(struct irq_domain *h, unsigned int virq, 177 irq_hw_number_t hw) 178{ 179 irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq); 180 181 return 0; 182} 183 184static const struct irq_domain_ops psurge_host_ops = { 185 .map = psurge_host_map, 186}; 187 188static int psurge_secondary_ipi_init(void) 189{ 190 int rc = -ENOMEM; 191 192 psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL); 193 194 if (psurge_host) 195 psurge_secondary_virq = irq_create_direct_mapping(psurge_host); 196 197 if (psurge_secondary_virq) 198 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr, 199 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL); 200 201 if (rc) 202 pr_err("Failed to setup secondary cpu IPI\n"); 203 204 return rc; 205} 206 207/* 208 * Determine a quad card presence. We read the board ID register, we 209 * force the data bus to change to something else, and we read it again. 210 * It it's stable, then the register probably exist (ugh !) 211 */ 212static int __init psurge_quad_probe(void) 213{ 214 int type; 215 unsigned int i; 216 217 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); 218 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS 219 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 220 return PSURGE_DUAL; 221 222 /* looks OK, try a slightly more rigorous test */ 223 /* bogus is not necessarily cacheline-aligned, 224 though I don't suppose that really matters. -- paulus */ 225 for (i = 0; i < 100; i++) { 226 volatile u32 bogus[8]; 227 bogus[(0+i)%8] = 0x00000000; 228 bogus[(1+i)%8] = 0x55555555; 229 bogus[(2+i)%8] = 0xFFFFFFFF; 230 bogus[(3+i)%8] = 0xAAAAAAAA; 231 bogus[(4+i)%8] = 0x33333333; 232 bogus[(5+i)%8] = 0xCCCCCCCC; 233 bogus[(6+i)%8] = 0xCCCCCCCC; 234 bogus[(7+i)%8] = 0x33333333; 235 wmb(); 236 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); 237 mb(); 238 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 239 return PSURGE_DUAL; 240 } 241 return type; 242} 243 244static void __init psurge_quad_init(void) 245{ 246 int procbits; 247 248 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); 249 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); 250 if (psurge_type == PSURGE_QUAD_ICEGRASS) 251 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 252 else 253 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); 254 mdelay(33); 255 out_8(psurge_sec_intr, ~0); 256 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); 257 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 258 if (psurge_type != PSURGE_QUAD_ICEGRASS) 259 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); 260 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); 261 mdelay(33); 262 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); 263 mdelay(33); 264 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); 265 mdelay(33); 266} 267 268static void __init smp_psurge_probe(void) 269{ 270 int i, ncpus; 271 struct device_node *dn; 272 273 /* 274 * The powersurge cpu board can be used in the generation 275 * of powermacs that have a socket for an upgradeable cpu card, 276 * including the 7500, 8500, 9500, 9600. 277 * The device tree doesn't tell you if you have 2 cpus because 278 * OF doesn't know anything about the 2nd processor. 279 * Instead we look for magic bits in magic registers, 280 * in the hammerhead memory controller in the case of the 281 * dual-cpu powersurge board. -- paulus. 282 */ 283 dn = of_find_node_by_name(NULL, "hammerhead"); 284 if (dn == NULL) 285 return; 286 of_node_put(dn); 287 288 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 289 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); 290 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; 291 292 psurge_type = psurge_quad_probe(); 293 if (psurge_type != PSURGE_DUAL) { 294 psurge_quad_init(); 295 /* All released cards using this HW design have 4 CPUs */ 296 ncpus = 4; 297 /* No sure how timebase sync works on those, let's use SW */ 298 smp_ops->give_timebase = smp_generic_give_timebase; 299 smp_ops->take_timebase = smp_generic_take_timebase; 300 } else { 301 iounmap(quad_base); 302 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 303 /* not a dual-cpu card */ 304 iounmap(hhead_base); 305 psurge_type = PSURGE_NONE; 306 return; 307 } 308 ncpus = 2; 309 } 310 311 if (psurge_secondary_ipi_init()) 312 return; 313 314 psurge_start = ioremap(PSURGE_START, 4); 315 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 316 317 /* This is necessary because OF doesn't know about the 318 * secondary cpu(s), and thus there aren't nodes in the 319 * device tree for them, and smp_setup_cpu_maps hasn't 320 * set their bits in cpu_present_mask. 321 */ 322 if (ncpus > NR_CPUS) 323 ncpus = NR_CPUS; 324 for (i = 1; i < ncpus ; ++i) 325 set_cpu_present(i, true); 326 327 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 328} 329 330static int __init smp_psurge_kick_cpu(int nr) 331{ 332 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 333 unsigned long a, flags; 334 int i, j; 335 336 /* Defining this here is evil ... but I prefer hiding that 337 * crap to avoid giving people ideas that they can do the 338 * same. 339 */ 340 extern volatile unsigned int cpu_callin_map[NR_CPUS]; 341 342 /* may need to flush here if secondary bats aren't setup */ 343 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 344 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); 345 asm volatile("sync"); 346 347 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 348 349 /* This is going to freeze the timeebase, we disable interrupts */ 350 local_irq_save(flags); 351 352 out_be32(psurge_start, start); 353 mb(); 354 355 psurge_set_ipi(nr); 356 357 /* 358 * We can't use udelay here because the timebase is now frozen. 359 */ 360 for (i = 0; i < 2000; ++i) 361 asm volatile("nop" : : : "memory"); 362 psurge_clr_ipi(nr); 363 364 /* 365 * Also, because the timebase is frozen, we must not return to the 366 * caller which will try to do udelay's etc... Instead, we wait -here- 367 * for the CPU to callin. 368 */ 369 for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { 370 for (j = 1; j < 10000; j++) 371 asm volatile("nop" : : : "memory"); 372 asm volatile("sync" : : : "memory"); 373 } 374 if (!cpu_callin_map[nr]) 375 goto stuck; 376 377 /* And we do the TB sync here too for standard dual CPU cards */ 378 if (psurge_type == PSURGE_DUAL) { 379 while(!tb_req) 380 barrier(); 381 tb_req = 0; 382 mb(); 383 timebase = get_tb(); 384 mb(); 385 while (timebase) 386 barrier(); 387 mb(); 388 } 389 stuck: 390 /* now interrupt the secondary, restarting both TBs */ 391 if (psurge_type == PSURGE_DUAL) 392 psurge_set_ipi(1); 393 394 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 395 396 return 0; 397} 398 399static void __init smp_psurge_setup_cpu(int cpu_nr) 400{ 401 unsigned long flags = IRQF_PERCPU | IRQF_NO_THREAD; 402 int irq; 403 404 if (cpu_nr != 0 || !psurge_start) 405 return; 406 407 /* reset the entry point so if we get another intr we won't 408 * try to startup again */ 409 out_be32(psurge_start, 0x100); 410 irq = irq_create_mapping(NULL, 30); 411 if (request_irq(irq, psurge_ipi_intr, flags, "primary IPI", NULL)) 412 printk(KERN_ERR "Couldn't get primary IPI interrupt"); 413} 414 415void __init smp_psurge_take_timebase(void) 416{ 417 if (psurge_type != PSURGE_DUAL) 418 return; 419 420 tb_req = 1; 421 mb(); 422 while (!timebase) 423 barrier(); 424 mb(); 425 set_tb(timebase >> 32, timebase & 0xffffffff); 426 timebase = 0; 427 mb(); 428 set_dec(tb_ticks_per_jiffy/2); 429} 430 431void __init smp_psurge_give_timebase(void) 432{ 433 /* Nothing to do here */ 434} 435 436/* PowerSurge-style Macs */ 437struct smp_ops_t psurge_smp_ops = { 438 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */ 439 .cause_ipi = smp_psurge_cause_ipi, 440 .cause_nmi_ipi = NULL, 441 .probe = smp_psurge_probe, 442 .kick_cpu = smp_psurge_kick_cpu, 443 .setup_cpu = smp_psurge_setup_cpu, 444 .give_timebase = smp_psurge_give_timebase, 445 .take_timebase = smp_psurge_take_timebase, 446}; 447#endif /* CONFIG_PPC_PMAC32_PSURGE */ 448 449/* 450 * Core 99 and later support 451 */ 452 453 454static void smp_core99_give_timebase(void) 455{ 456 unsigned long flags; 457 458 local_irq_save(flags); 459 460 while(!tb_req) 461 barrier(); 462 tb_req = 0; 463 (*pmac_tb_freeze)(1); 464 mb(); 465 timebase = get_tb(); 466 mb(); 467 while (timebase) 468 barrier(); 469 mb(); 470 (*pmac_tb_freeze)(0); 471 mb(); 472 473 local_irq_restore(flags); 474} 475 476 477static void smp_core99_take_timebase(void) 478{ 479 unsigned long flags; 480 481 local_irq_save(flags); 482 483 tb_req = 1; 484 mb(); 485 while (!timebase) 486 barrier(); 487 mb(); 488 set_tb(timebase >> 32, timebase & 0xffffffff); 489 timebase = 0; 490 mb(); 491 492 local_irq_restore(flags); 493} 494 495#ifdef CONFIG_PPC64 496/* 497 * G5s enable/disable the timebase via an i2c-connected clock chip. 498 */ 499static struct pmac_i2c_bus *pmac_tb_clock_chip_host; 500static u8 pmac_tb_pulsar_addr; 501 502static void smp_core99_cypress_tb_freeze(int freeze) 503{ 504 u8 data; 505 int rc; 506 507 /* Strangely, the device-tree says address is 0xd2, but darwin 508 * accesses 0xd0 ... 509 */ 510 pmac_i2c_setmode(pmac_tb_clock_chip_host, 511 pmac_i2c_mode_combined); 512 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 513 0xd0 | pmac_i2c_read, 514 1, 0x81, &data, 1); 515 if (rc != 0) 516 goto bail; 517 518 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); 519 520 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 521 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 522 0xd0 | pmac_i2c_write, 523 1, 0x81, &data, 1); 524 525 bail: 526 if (rc != 0) { 527 printk("Cypress Timebase %s rc: %d\n", 528 freeze ? "freeze" : "unfreeze", rc); 529 panic("Timebase freeze failed !\n"); 530 } 531} 532 533 534static void smp_core99_pulsar_tb_freeze(int freeze) 535{ 536 u8 data; 537 int rc; 538 539 pmac_i2c_setmode(pmac_tb_clock_chip_host, 540 pmac_i2c_mode_combined); 541 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 542 pmac_tb_pulsar_addr | pmac_i2c_read, 543 1, 0x2e, &data, 1); 544 if (rc != 0) 545 goto bail; 546 547 data = (data & 0x88) | (freeze ? 0x11 : 0x22); 548 549 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 550 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 551 pmac_tb_pulsar_addr | pmac_i2c_write, 552 1, 0x2e, &data, 1); 553 bail: 554 if (rc != 0) { 555 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", 556 freeze ? "freeze" : "unfreeze", rc); 557 panic("Timebase freeze failed !\n"); 558 } 559} 560 561static void __init smp_core99_setup_i2c_hwsync(int ncpus) 562{ 563 struct device_node *cc = NULL; 564 struct device_node *p; 565 const char *name = NULL; 566 const u32 *reg; 567 int ok; 568 569 /* Look for the clock chip */ 570 for_each_node_by_name(cc, "i2c-hwclock") { 571 p = of_get_parent(cc); 572 ok = p && of_device_is_compatible(p, "uni-n-i2c"); 573 of_node_put(p); 574 if (!ok) 575 continue; 576 577 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); 578 if (pmac_tb_clock_chip_host == NULL) 579 continue; 580 reg = of_get_property(cc, "reg", NULL); 581 if (reg == NULL) 582 continue; 583 switch (*reg) { 584 case 0xd2: 585 if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) { 586 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 587 pmac_tb_pulsar_addr = 0xd2; 588 name = "Pulsar"; 589 } else if (of_device_is_compatible(cc, "cy28508")) { 590 pmac_tb_freeze = smp_core99_cypress_tb_freeze; 591 name = "Cypress"; 592 } 593 break; 594 case 0xd4: 595 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 596 pmac_tb_pulsar_addr = 0xd4; 597 name = "Pulsar"; 598 break; 599 } 600 if (pmac_tb_freeze != NULL) 601 break; 602 } 603 if (pmac_tb_freeze != NULL) { 604 /* Open i2c bus for synchronous access */ 605 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { 606 printk(KERN_ERR "Failed top open i2c bus for clock" 607 " sync, fallback to software sync !\n"); 608 goto no_i2c_sync; 609 } 610 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", 611 name); 612 return; 613 } 614 no_i2c_sync: 615 pmac_tb_freeze = NULL; 616 pmac_tb_clock_chip_host = NULL; 617} 618 619 620 621/* 622 * Newer G5s uses a platform function 623 */ 624 625static void smp_core99_pfunc_tb_freeze(int freeze) 626{ 627 struct device_node *cpus; 628 struct pmf_args args; 629 630 cpus = of_find_node_by_path("/cpus"); 631 BUG_ON(cpus == NULL); 632 args.count = 1; 633 args.u[0].v = !freeze; 634 pmf_call_function(cpus, "cpu-timebase", &args); 635 of_node_put(cpus); 636} 637 638#else /* CONFIG_PPC64 */ 639 640/* 641 * SMP G4 use a GPIO to enable/disable the timebase. 642 */ 643 644static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ 645 646static void smp_core99_gpio_tb_freeze(int freeze) 647{ 648 if (freeze) 649 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); 650 else 651 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); 652 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); 653} 654 655 656#endif /* !CONFIG_PPC64 */ 657 658static void core99_init_caches(int cpu) 659{ 660#ifndef CONFIG_PPC64 661 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 662 static long int core99_l2_cache; 663 static long int core99_l3_cache; 664 665 if (!cpu_has_feature(CPU_FTR_L2CR)) 666 return; 667 668 if (cpu == 0) { 669 core99_l2_cache = _get_L2CR(); 670 printk("CPU0: L2CR is %lx\n", core99_l2_cache); 671 } else { 672 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); 673 _set_L2CR(0); 674 _set_L2CR(core99_l2_cache); 675 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); 676 } 677 678 if (!cpu_has_feature(CPU_FTR_L3CR)) 679 return; 680 681 if (cpu == 0){ 682 core99_l3_cache = _get_L3CR(); 683 printk("CPU0: L3CR is %lx\n", core99_l3_cache); 684 } else { 685 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); 686 _set_L3CR(0); 687 _set_L3CR(core99_l3_cache); 688 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); 689 } 690#endif /* !CONFIG_PPC64 */ 691} 692 693static void __init smp_core99_setup(int ncpus) 694{ 695#ifdef CONFIG_PPC64 696 697 /* i2c based HW sync on some G5s */ 698 if (of_machine_is_compatible("PowerMac7,2") || 699 of_machine_is_compatible("PowerMac7,3") || 700 of_machine_is_compatible("RackMac3,1")) 701 smp_core99_setup_i2c_hwsync(ncpus); 702 703 /* pfunc based HW sync on recent G5s */ 704 if (pmac_tb_freeze == NULL) { 705 struct device_node *cpus = 706 of_find_node_by_path("/cpus"); 707 if (cpus && 708 of_get_property(cpus, "platform-cpu-timebase", NULL)) { 709 pmac_tb_freeze = smp_core99_pfunc_tb_freeze; 710 printk(KERN_INFO "Processor timebase sync using" 711 " platform function\n"); 712 } 713 } 714 715#else /* CONFIG_PPC64 */ 716 717 /* GPIO based HW sync on ppc32 Core99 */ 718 if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) { 719 struct device_node *cpu; 720 const u32 *tbprop = NULL; 721 722 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ 723 cpu = of_find_node_by_type(NULL, "cpu"); 724 if (cpu != NULL) { 725 tbprop = of_get_property(cpu, "timebase-enable", NULL); 726 if (tbprop) 727 core99_tb_gpio = *tbprop; 728 of_node_put(cpu); 729 } 730 pmac_tb_freeze = smp_core99_gpio_tb_freeze; 731 printk(KERN_INFO "Processor timebase sync using" 732 " GPIO 0x%02x\n", core99_tb_gpio); 733 } 734 735#endif /* CONFIG_PPC64 */ 736 737 /* No timebase sync, fallback to software */ 738 if (pmac_tb_freeze == NULL) { 739 smp_ops->give_timebase = smp_generic_give_timebase; 740 smp_ops->take_timebase = smp_generic_take_timebase; 741 printk(KERN_INFO "Processor timebase sync using software\n"); 742 } 743 744#ifndef CONFIG_PPC64 745 { 746 int i; 747 748 /* XXX should get this from reg properties */ 749 for (i = 1; i < ncpus; ++i) 750 set_hard_smp_processor_id(i, i); 751 } 752#endif 753 754 /* 32 bits SMP can't NAP */ 755 if (!of_machine_is_compatible("MacRISC4")) 756 powersave_nap = 0; 757} 758 759static void __init smp_core99_probe(void) 760{ 761 struct device_node *cpus; 762 int ncpus = 0; 763 764 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); 765 766 /* Count CPUs in the device-tree */ 767 for_each_node_by_type(cpus, "cpu") 768 ++ncpus; 769 770 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); 771 772 /* Nothing more to do if less than 2 of them */ 773 if (ncpus <= 1) 774 return; 775 776 /* We need to perform some early initialisations before we can start 777 * setting up SMP as we are running before initcalls 778 */ 779 pmac_pfunc_base_install(); 780 pmac_i2c_init(); 781 782 /* Setup various bits like timebase sync method, ability to nap, ... */ 783 smp_core99_setup(ncpus); 784 785 /* Install IPIs */ 786 mpic_request_ipis(); 787 788 /* Collect l2cr and l3cr values from CPU 0 */ 789 core99_init_caches(0); 790} 791 792static int smp_core99_kick_cpu(int nr) 793{ 794 unsigned int save_vector; 795 unsigned long target, flags; 796 unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100); 797 798 if (nr < 0 || nr > 3) 799 return -ENOENT; 800 801 if (ppc_md.progress) 802 ppc_md.progress("smp_core99_kick_cpu", 0x346); 803 804 local_irq_save(flags); 805 806 /* Save reset vector */ 807 save_vector = *vector; 808 809 /* Setup fake reset vector that does 810 * b __secondary_start_pmac_0 + nr*8 811 */ 812 target = (unsigned long) __secondary_start_pmac_0 + nr * 8; 813 patch_branch((struct ppc_inst *)vector, target, BRANCH_SET_LINK); 814 815 /* Put some life in our friend */ 816 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); 817 818 /* FIXME: We wait a bit for the CPU to take the exception, I should 819 * instead wait for the entry code to set something for me. Well, 820 * ideally, all that crap will be done in prom.c and the CPU left 821 * in a RAM-based wait loop like CHRP. 822 */ 823 mdelay(1); 824 825 /* Restore our exception vector */ 826 patch_instruction((struct ppc_inst *)vector, ppc_inst(save_vector)); 827 828 local_irq_restore(flags); 829 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); 830 831 return 0; 832} 833 834static void smp_core99_setup_cpu(int cpu_nr) 835{ 836 /* Setup L2/L3 */ 837 if (cpu_nr != 0) 838 core99_init_caches(cpu_nr); 839 840 /* Setup openpic */ 841 mpic_setup_this_cpu(); 842} 843 844#ifdef CONFIG_PPC64 845#ifdef CONFIG_HOTPLUG_CPU 846static unsigned int smp_core99_host_open; 847 848static int smp_core99_cpu_prepare(unsigned int cpu) 849{ 850 int rc; 851 852 /* Open i2c bus if it was used for tb sync */ 853 if (pmac_tb_clock_chip_host && !smp_core99_host_open) { 854 rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1); 855 if (rc) { 856 pr_err("Failed to open i2c bus for time sync\n"); 857 return notifier_from_errno(rc); 858 } 859 smp_core99_host_open = 1; 860 } 861 return 0; 862} 863 864static int smp_core99_cpu_online(unsigned int cpu) 865{ 866 /* Close i2c bus if it was used for tb sync */ 867 if (pmac_tb_clock_chip_host && smp_core99_host_open) { 868 pmac_i2c_close(pmac_tb_clock_chip_host); 869 smp_core99_host_open = 0; 870 } 871 return 0; 872} 873#endif /* CONFIG_HOTPLUG_CPU */ 874 875static void __init smp_core99_bringup_done(void) 876{ 877 extern void g5_phy_disable_cpu1(void); 878 879 /* Close i2c bus if it was used for tb sync */ 880 if (pmac_tb_clock_chip_host) 881 pmac_i2c_close(pmac_tb_clock_chip_host); 882 883 /* If we didn't start the second CPU, we must take 884 * it off the bus. 885 */ 886 if (of_machine_is_compatible("MacRISC4") && 887 num_online_cpus() < 2) { 888 set_cpu_present(1, false); 889 g5_phy_disable_cpu1(); 890 } 891#ifdef CONFIG_HOTPLUG_CPU 892 cpuhp_setup_state_nocalls(CPUHP_POWERPC_PMAC_PREPARE, 893 "powerpc/pmac:prepare", smp_core99_cpu_prepare, 894 NULL); 895 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "powerpc/pmac:online", 896 smp_core99_cpu_online, NULL); 897#endif 898 899 if (ppc_md.progress) 900 ppc_md.progress("smp_core99_bringup_done", 0x349); 901} 902#endif /* CONFIG_PPC64 */ 903 904#ifdef CONFIG_HOTPLUG_CPU 905 906static int smp_core99_cpu_disable(void) 907{ 908 int rc = generic_cpu_disable(); 909 if (rc) 910 return rc; 911 912 mpic_cpu_set_priority(0xf); 913 914 cleanup_cpu_mmu_context(); 915 916 return 0; 917} 918 919#ifdef CONFIG_PPC32 920 921static void pmac_cpu_offline_self(void) 922{ 923 int cpu = smp_processor_id(); 924 925 local_irq_disable(); 926 idle_task_exit(); 927 pr_debug("CPU%d offline\n", cpu); 928 generic_set_cpu_dead(cpu); 929 smp_wmb(); 930 mb(); 931 low_cpu_offline_self(); 932} 933 934#else /* CONFIG_PPC32 */ 935 936static void pmac_cpu_offline_self(void) 937{ 938 int cpu = smp_processor_id(); 939 940 local_irq_disable(); 941 idle_task_exit(); 942 943 /* 944 * turn off as much as possible, we'll be 945 * kicked out as this will only be invoked 946 * on core99 platforms for now ... 947 */ 948 949 printk(KERN_INFO "CPU#%d offline\n", cpu); 950 generic_set_cpu_dead(cpu); 951 smp_wmb(); 952 953 /* 954 * Re-enable interrupts. The NAP code needs to enable them 955 * anyways, do it now so we deal with the case where one already 956 * happened while soft-disabled. 957 * We shouldn't get any external interrupts, only decrementer, and the 958 * decrementer handler is safe for use on offline CPUs 959 */ 960 local_irq_enable(); 961 962 while (1) { 963 /* let's not take timer interrupts too often ... */ 964 set_dec(0x7fffffff); 965 966 /* Enter NAP mode */ 967 power4_idle(); 968 } 969} 970 971#endif /* else CONFIG_PPC32 */ 972#endif /* CONFIG_HOTPLUG_CPU */ 973 974/* Core99 Macs (dual G4s and G5s) */ 975static struct smp_ops_t core99_smp_ops = { 976 .message_pass = smp_mpic_message_pass, 977 .probe = smp_core99_probe, 978#ifdef CONFIG_PPC64 979 .bringup_done = smp_core99_bringup_done, 980#endif 981 .kick_cpu = smp_core99_kick_cpu, 982 .setup_cpu = smp_core99_setup_cpu, 983 .give_timebase = smp_core99_give_timebase, 984 .take_timebase = smp_core99_take_timebase, 985#if defined(CONFIG_HOTPLUG_CPU) 986 .cpu_disable = smp_core99_cpu_disable, 987 .cpu_die = generic_cpu_die, 988#endif 989}; 990 991void __init pmac_setup_smp(void) 992{ 993 struct device_node *np; 994 995 /* Check for Core99 */ 996 np = of_find_node_by_name(NULL, "uni-n"); 997 if (!np) 998 np = of_find_node_by_name(NULL, "u3"); 999 if (!np) 1000 np = of_find_node_by_name(NULL, "u4"); 1001 if (np) { 1002 of_node_put(np); 1003 smp_ops = &core99_smp_ops; 1004 } 1005#ifdef CONFIG_PPC_PMAC32_PSURGE 1006 else { 1007 /* We have to set bits in cpu_possible_mask here since the 1008 * secondary CPU(s) aren't in the device tree. Various 1009 * things won't be initialized for CPUs not in the possible 1010 * map, so we really need to fix it up here. 1011 */ 1012 int cpu; 1013 1014 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) 1015 set_cpu_possible(cpu, true); 1016 smp_ops = &psurge_smp_ops; 1017 } 1018#endif /* CONFIG_PPC_PMAC32_PSURGE */ 1019 1020#ifdef CONFIG_HOTPLUG_CPU 1021 smp_ops->cpu_offline_self = pmac_cpu_offline_self; 1022#endif 1023} 1024 1025 1026