1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *  Support for the interrupt controllers found on Power Macintosh,
4 *  currently Apple's "Grand Central" interrupt controller in all
5 *  it's incarnations. OpenPIC support used on newer machines is
6 *  in a separate file
7 *
8 *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
9 *  Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
10 *                     IBM, Corp.
11 */
12
13#include <linux/stddef.h>
14#include <linux/init.h>
15#include <linux/sched.h>
16#include <linux/signal.h>
17#include <linux/pci.h>
18#include <linux/interrupt.h>
19#include <linux/syscore_ops.h>
20#include <linux/adb.h>
21#include <linux/pmu.h>
22
23#include <asm/sections.h>
24#include <asm/io.h>
25#include <asm/smp.h>
26#include <asm/prom.h>
27#include <asm/pci-bridge.h>
28#include <asm/time.h>
29#include <asm/pmac_feature.h>
30#include <asm/mpic.h>
31#include <asm/xmon.h>
32
33#include "pmac.h"
34
35#ifdef CONFIG_PPC32
36struct pmac_irq_hw {
37        unsigned int    event;
38        unsigned int    enable;
39        unsigned int    ack;
40        unsigned int    level;
41};
42
43/* Workaround flags for 32bit powermac machines */
44unsigned int of_irq_workarounds;
45struct device_node *of_irq_dflt_pic;
46
47/* Default addresses */
48static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
49
50static int max_irqs;
51static int max_real_irqs;
52
53static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
54
55/* The max irq number this driver deals with is 128; see max_irqs */
56static DECLARE_BITMAP(ppc_lost_interrupts, 128);
57static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
58static int pmac_irq_cascade = -1;
59static struct irq_domain *pmac_pic_host;
60
61static void __pmac_retrigger(unsigned int irq_nr)
62{
63	if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
64		__set_bit(irq_nr, ppc_lost_interrupts);
65		irq_nr = pmac_irq_cascade;
66		mb();
67	}
68	if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
69		atomic_inc(&ppc_n_lost_interrupts);
70		set_dec(1);
71	}
72}
73
74static void pmac_mask_and_ack_irq(struct irq_data *d)
75{
76	unsigned int src = irqd_to_hwirq(d);
77        unsigned long bit = 1UL << (src & 0x1f);
78        int i = src >> 5;
79        unsigned long flags;
80
81	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
82        __clear_bit(src, ppc_cached_irq_mask);
83        if (__test_and_clear_bit(src, ppc_lost_interrupts))
84                atomic_dec(&ppc_n_lost_interrupts);
85        out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
86        out_le32(&pmac_irq_hw[i]->ack, bit);
87        do {
88                /* make sure ack gets to controller before we enable
89                   interrupts */
90                mb();
91        } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
92                != (ppc_cached_irq_mask[i] & bit));
93	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
94}
95
96static void pmac_ack_irq(struct irq_data *d)
97{
98	unsigned int src = irqd_to_hwirq(d);
99        unsigned long bit = 1UL << (src & 0x1f);
100        int i = src >> 5;
101        unsigned long flags;
102
103	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
104	if (__test_and_clear_bit(src, ppc_lost_interrupts))
105                atomic_dec(&ppc_n_lost_interrupts);
106        out_le32(&pmac_irq_hw[i]->ack, bit);
107        (void)in_le32(&pmac_irq_hw[i]->ack);
108	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
109}
110
111static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
112{
113        unsigned long bit = 1UL << (irq_nr & 0x1f);
114        int i = irq_nr >> 5;
115
116        if ((unsigned)irq_nr >= max_irqs)
117                return;
118
119        /* enable unmasked interrupts */
120        out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
121
122        do {
123                /* make sure mask gets to controller before we
124                   return to user */
125                mb();
126        } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
127                != (ppc_cached_irq_mask[i] & bit));
128
129        /*
130         * Unfortunately, setting the bit in the enable register
131         * when the device interrupt is already on *doesn't* set
132         * the bit in the flag register or request another interrupt.
133         */
134        if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
135		__pmac_retrigger(irq_nr);
136}
137
138/* When an irq gets requested for the first client, if it's an
139 * edge interrupt, we clear any previous one on the controller
140 */
141static unsigned int pmac_startup_irq(struct irq_data *d)
142{
143	unsigned long flags;
144	unsigned int src = irqd_to_hwirq(d);
145        unsigned long bit = 1UL << (src & 0x1f);
146        int i = src >> 5;
147
148	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
149	if (!irqd_is_level_type(d))
150		out_le32(&pmac_irq_hw[i]->ack, bit);
151        __set_bit(src, ppc_cached_irq_mask);
152        __pmac_set_irq_mask(src, 0);
153	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
154
155	return 0;
156}
157
158static void pmac_mask_irq(struct irq_data *d)
159{
160	unsigned long flags;
161	unsigned int src = irqd_to_hwirq(d);
162
163	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
164        __clear_bit(src, ppc_cached_irq_mask);
165        __pmac_set_irq_mask(src, 1);
166	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
167}
168
169static void pmac_unmask_irq(struct irq_data *d)
170{
171	unsigned long flags;
172	unsigned int src = irqd_to_hwirq(d);
173
174	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
175	__set_bit(src, ppc_cached_irq_mask);
176        __pmac_set_irq_mask(src, 0);
177	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
178}
179
180static int pmac_retrigger(struct irq_data *d)
181{
182	unsigned long flags;
183
184	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
185	__pmac_retrigger(irqd_to_hwirq(d));
186	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
187	return 1;
188}
189
190static struct irq_chip pmac_pic = {
191	.name		= "PMAC-PIC",
192	.irq_startup	= pmac_startup_irq,
193	.irq_mask	= pmac_mask_irq,
194	.irq_ack	= pmac_ack_irq,
195	.irq_mask_ack	= pmac_mask_and_ack_irq,
196	.irq_unmask	= pmac_unmask_irq,
197	.irq_retrigger	= pmac_retrigger,
198};
199
200static irqreturn_t gatwick_action(int cpl, void *dev_id)
201{
202	unsigned long flags;
203	int irq, bits;
204	int rc = IRQ_NONE;
205
206	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
207	for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
208		int i = irq >> 5;
209		bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
210		bits |= in_le32(&pmac_irq_hw[i]->level);
211		bits &= ppc_cached_irq_mask[i];
212		if (bits == 0)
213			continue;
214		irq += __ilog2(bits);
215		raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
216		generic_handle_irq(irq);
217		raw_spin_lock_irqsave(&pmac_pic_lock, flags);
218		rc = IRQ_HANDLED;
219	}
220	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
221	return rc;
222}
223
224static unsigned int pmac_pic_get_irq(void)
225{
226	int irq;
227	unsigned long bits = 0;
228	unsigned long flags;
229
230#ifdef CONFIG_PPC_PMAC32_PSURGE
231	/* IPI's are a hack on the powersurge -- Cort */
232	if (smp_processor_id() != 0) {
233		return  psurge_secondary_virq;
234        }
235#endif /* CONFIG_PPC_PMAC32_PSURGE */
236	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
237	for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
238		int i = irq >> 5;
239		bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
240		bits |= in_le32(&pmac_irq_hw[i]->level);
241		bits &= ppc_cached_irq_mask[i];
242		if (bits == 0)
243			continue;
244		irq += __ilog2(bits);
245		break;
246	}
247	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
248	if (unlikely(irq < 0))
249		return 0;
250	return irq_linear_revmap(pmac_pic_host, irq);
251}
252
253static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node,
254			       enum irq_domain_bus_token bus_token)
255{
256	/* We match all, we don't always have a node anyway */
257	return 1;
258}
259
260static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
261			     irq_hw_number_t hw)
262{
263	if (hw >= max_irqs)
264		return -EINVAL;
265
266	/* Mark level interrupts, set delayed disable for edge ones and set
267	 * handlers
268	 */
269	irq_set_status_flags(virq, IRQ_LEVEL);
270	irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
271	return 0;
272}
273
274static const struct irq_domain_ops pmac_pic_host_ops = {
275	.match = pmac_pic_host_match,
276	.map = pmac_pic_host_map,
277	.xlate = irq_domain_xlate_onecell,
278};
279
280static void __init pmac_pic_probe_oldstyle(void)
281{
282        int i;
283        struct device_node *master = NULL;
284	struct device_node *slave = NULL;
285	u8 __iomem *addr;
286	struct resource r;
287
288	/* Set our get_irq function */
289	ppc_md.get_irq = pmac_pic_get_irq;
290
291	/*
292	 * Find the interrupt controller type & node
293	 */
294
295	if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
296		max_irqs = max_real_irqs = 32;
297	} else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
298		max_irqs = max_real_irqs = 32;
299		/* We might have a second cascaded ohare */
300		slave = of_find_node_by_name(NULL, "pci106b,7");
301		if (slave)
302			max_irqs = 64;
303	} else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
304		max_irqs = max_real_irqs = 64;
305
306		/* We might have a second cascaded heathrow */
307
308		/* Compensate for of_node_put() in of_find_node_by_name() */
309		of_node_get(master);
310		slave = of_find_node_by_name(master, "mac-io");
311
312		/* Check ordering of master & slave */
313		if (of_device_is_compatible(master, "gatwick")) {
314			struct device_node *tmp;
315			BUG_ON(slave == NULL);
316			tmp = master;
317			master = slave;
318			slave = tmp;
319		}
320
321		/* We found a slave */
322		if (slave)
323			max_irqs = 128;
324	}
325	BUG_ON(master == NULL);
326
327	/*
328	 * Allocate an irq host
329	 */
330	pmac_pic_host = irq_domain_add_linear(master, max_irqs,
331					      &pmac_pic_host_ops, NULL);
332	BUG_ON(pmac_pic_host == NULL);
333	irq_set_default_host(pmac_pic_host);
334
335	/* Get addresses of first controller if we have a node for it */
336	BUG_ON(of_address_to_resource(master, 0, &r));
337
338	/* Map interrupts of primary controller */
339	addr = (u8 __iomem *) ioremap(r.start, 0x40);
340	i = 0;
341	pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
342		(addr + 0x20);
343	if (max_real_irqs > 32)
344		pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
345			(addr + 0x10);
346	of_node_put(master);
347
348	printk(KERN_INFO "irq: Found primary Apple PIC %pOF for %d irqs\n",
349	       master, max_real_irqs);
350
351	/* Map interrupts of cascaded controller */
352	if (slave && !of_address_to_resource(slave, 0, &r)) {
353		addr = (u8 __iomem *)ioremap(r.start, 0x40);
354		pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
355			(addr + 0x20);
356		if (max_irqs > 64)
357			pmac_irq_hw[i++] =
358				(volatile struct pmac_irq_hw __iomem *)
359				(addr + 0x10);
360		pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
361
362		printk(KERN_INFO "irq: Found slave Apple PIC %pOF for %d irqs"
363		       " cascade: %d\n", slave,
364		       max_irqs - max_real_irqs, pmac_irq_cascade);
365	}
366	of_node_put(slave);
367
368	/* Disable all interrupts in all controllers */
369	for (i = 0; i * 32 < max_irqs; ++i)
370		out_le32(&pmac_irq_hw[i]->enable, 0);
371
372	/* Hookup cascade irq */
373	if (slave && pmac_irq_cascade) {
374		if (request_irq(pmac_irq_cascade, gatwick_action,
375				IRQF_NO_THREAD, "cascade", NULL))
376			pr_err("Failed to register cascade interrupt\n");
377	}
378
379	printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
380#ifdef CONFIG_XMON
381	i = irq_create_mapping(NULL, 20);
382	if (request_irq(i, xmon_irq, IRQF_NO_THREAD, "NMI - XMON", NULL))
383		pr_err("Failed to register NMI-XMON interrupt\n");
384#endif
385}
386
387int of_irq_parse_oldworld(struct device_node *device, int index,
388			struct of_phandle_args *out_irq)
389{
390	const u32 *ints = NULL;
391	int intlen;
392
393	/*
394	 * Old machines just have a list of interrupt numbers
395	 * and no interrupt-controller nodes. We also have dodgy
396	 * cases where the APPL,interrupts property is completely
397	 * missing behind pci-pci bridges and we have to get it
398	 * from the parent (the bridge itself, as apple just wired
399	 * everything together on these)
400	 */
401	while (device) {
402		ints = of_get_property(device, "AAPL,interrupts", &intlen);
403		if (ints != NULL)
404			break;
405		device = device->parent;
406		if (!of_node_is_type(device, "pci"))
407			break;
408	}
409	if (ints == NULL)
410		return -EINVAL;
411	intlen /= sizeof(u32);
412
413	if (index >= intlen)
414		return -EINVAL;
415
416	out_irq->np = NULL;
417	out_irq->args[0] = ints[index];
418	out_irq->args_count = 1;
419
420	return 0;
421}
422#endif /* CONFIG_PPC32 */
423
424static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
425{
426#if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
427	struct device_node* pswitch;
428	int nmi_irq;
429
430	pswitch = of_find_node_by_name(NULL, "programmer-switch");
431	if (pswitch) {
432		nmi_irq = irq_of_parse_and_map(pswitch, 0);
433		if (nmi_irq) {
434			mpic_irq_set_priority(nmi_irq, 9);
435			if (request_irq(nmi_irq, xmon_irq, IRQF_NO_THREAD,
436					"NMI - XMON", NULL))
437				pr_err("Failed to register NMI-XMON interrupt\n");
438		}
439		of_node_put(pswitch);
440	}
441#endif	/* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
442}
443
444static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
445						int master)
446{
447	const char *name = master ? " MPIC 1   " : " MPIC 2   ";
448	struct mpic *mpic;
449	unsigned int flags = master ? 0 : MPIC_SECONDARY;
450
451	pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
452
453	if (of_get_property(np, "big-endian", NULL))
454		flags |= MPIC_BIG_ENDIAN;
455
456	/* Primary Big Endian means HT interrupts. This is quite dodgy
457	 * but works until I find a better way
458	 */
459	if (master && (flags & MPIC_BIG_ENDIAN))
460		flags |= MPIC_U3_HT_IRQS;
461
462	mpic = mpic_alloc(np, 0, flags, 0, 0, name);
463	if (mpic == NULL)
464		return NULL;
465
466	mpic_init(mpic);
467
468	return mpic;
469 }
470
471static int __init pmac_pic_probe_mpic(void)
472{
473	struct mpic *mpic1, *mpic2;
474	struct device_node *np, *master = NULL, *slave = NULL;
475
476	/* We can have up to 2 MPICs cascaded */
477	for_each_node_by_type(np, "open-pic") {
478		if (master == NULL &&
479		    of_get_property(np, "interrupts", NULL) == NULL)
480			master = of_node_get(np);
481		else if (slave == NULL)
482			slave = of_node_get(np);
483		if (master && slave) {
484			of_node_put(np);
485			break;
486		}
487	}
488
489	/* Check for bogus setups */
490	if (master == NULL && slave != NULL) {
491		master = slave;
492		slave = NULL;
493	}
494
495	/* Not found, default to good old pmac pic */
496	if (master == NULL)
497		return -ENODEV;
498
499	/* Set master handler */
500	ppc_md.get_irq = mpic_get_irq;
501
502	/* Setup master */
503	mpic1 = pmac_setup_one_mpic(master, 1);
504	BUG_ON(mpic1 == NULL);
505
506	/* Install NMI if any */
507	pmac_pic_setup_mpic_nmi(mpic1);
508
509	of_node_put(master);
510
511	/* Set up a cascaded controller, if present */
512	if (slave) {
513		mpic2 = pmac_setup_one_mpic(slave, 0);
514		if (mpic2 == NULL)
515			printk(KERN_ERR "Failed to setup slave MPIC\n");
516		of_node_put(slave);
517	}
518
519	return 0;
520}
521
522
523void __init pmac_pic_init(void)
524{
525	/* We configure the OF parsing based on our oldworld vs. newworld
526	 * platform type and whether we were booted by BootX.
527	 */
528#ifdef CONFIG_PPC32
529	if (!pmac_newworld)
530		of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
531	if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
532		of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
533
534	/* If we don't have phandles on a newworld, then try to locate a
535	 * default interrupt controller (happens when booting with BootX).
536	 * We do a first match here, hopefully, that only ever happens on
537	 * machines with one controller.
538	 */
539	if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
540		struct device_node *np;
541
542		for_each_node_with_property(np, "interrupt-controller") {
543			/* Skip /chosen/interrupt-controller */
544			if (of_node_name_eq(np, "chosen"))
545				continue;
546			/* It seems like at least one person wants
547			 * to use BootX on a machine with an AppleKiwi
548			 * controller which happens to pretend to be an
549			 * interrupt controller too. */
550			if (of_node_name_eq(np, "AppleKiwi"))
551				continue;
552			/* I think we found one ! */
553			of_irq_dflt_pic = np;
554			break;
555		}
556	}
557#endif /* CONFIG_PPC32 */
558
559	/* We first try to detect Apple's new Core99 chipset, since mac-io
560	 * is quite different on those machines and contains an IBM MPIC2.
561	 */
562	if (pmac_pic_probe_mpic() == 0)
563		return;
564
565#ifdef CONFIG_PPC32
566	pmac_pic_probe_oldstyle();
567#endif
568}
569
570#if defined(CONFIG_PM) && defined(CONFIG_PPC32)
571/*
572 * These procedures are used in implementing sleep on the powerbooks.
573 * sleep_save_intrs() saves the states of all interrupt enables
574 * and disables all interrupts except for the nominated one.
575 * sleep_restore_intrs() restores the states of all interrupt enables.
576 */
577unsigned long sleep_save_mask[2];
578
579/* This used to be passed by the PMU driver but that link got
580 * broken with the new driver model. We use this tweak for now...
581 * We really want to do things differently though...
582 */
583static int pmacpic_find_viaint(void)
584{
585	int viaint = -1;
586
587#ifdef CONFIG_ADB_PMU
588	struct device_node *np;
589
590	if (pmu_get_model() != PMU_OHARE_BASED)
591		goto not_found;
592	np = of_find_node_by_name(NULL, "via-pmu");
593	if (np == NULL)
594		goto not_found;
595	viaint = irq_of_parse_and_map(np, 0);
596	of_node_put(np);
597
598not_found:
599#endif /* CONFIG_ADB_PMU */
600	return viaint;
601}
602
603static int pmacpic_suspend(void)
604{
605	int viaint = pmacpic_find_viaint();
606
607	sleep_save_mask[0] = ppc_cached_irq_mask[0];
608	sleep_save_mask[1] = ppc_cached_irq_mask[1];
609	ppc_cached_irq_mask[0] = 0;
610	ppc_cached_irq_mask[1] = 0;
611	if (viaint > 0)
612		set_bit(viaint, ppc_cached_irq_mask);
613	out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
614	if (max_real_irqs > 32)
615		out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
616	(void)in_le32(&pmac_irq_hw[0]->event);
617	/* make sure mask gets to controller before we return to caller */
618	mb();
619        (void)in_le32(&pmac_irq_hw[0]->enable);
620
621        return 0;
622}
623
624static void pmacpic_resume(void)
625{
626	int i;
627
628	out_le32(&pmac_irq_hw[0]->enable, 0);
629	if (max_real_irqs > 32)
630		out_le32(&pmac_irq_hw[1]->enable, 0);
631	mb();
632	for (i = 0; i < max_real_irqs; ++i)
633		if (test_bit(i, sleep_save_mask))
634			pmac_unmask_irq(irq_get_irq_data(i));
635}
636
637static struct syscore_ops pmacpic_syscore_ops = {
638	.suspend	= pmacpic_suspend,
639	.resume		= pmacpic_resume,
640};
641
642static int __init init_pmacpic_syscore(void)
643{
644	if (pmac_irq_hw[0])
645		register_syscore_ops(&pmacpic_syscore_ops);
646	return 0;
647}
648
649machine_subsys_initcall(powermac, init_pmacpic_syscore);
650
651#endif /* CONFIG_PM && CONFIG_PPC32 */
652