1// SPDX-License-Identifier: GPL-2.0
2/*
3 *  Copyright (C) 1995  Linus Torvalds
4 *  Adapted from 'alpha' version by Gary Thomas
5 *  Modified by Cort Dougan (cort@cs.nmt.edu)
6 */
7
8/*
9 * bootup setup stuff..
10 */
11
12#include <linux/errno.h>
13#include <linux/sched.h>
14#include <linux/kernel.h>
15#include <linux/mm.h>
16#include <linux/stddef.h>
17#include <linux/unistd.h>
18#include <linux/ptrace.h>
19#include <linux/user.h>
20#include <linux/tty.h>
21#include <linux/major.h>
22#include <linux/interrupt.h>
23#include <linux/reboot.h>
24#include <linux/init.h>
25#include <linux/pci.h>
26#include <generated/utsrelease.h>
27#include <linux/adb.h>
28#include <linux/module.h>
29#include <linux/delay.h>
30#include <linux/console.h>
31#include <linux/seq_file.h>
32#include <linux/root_dev.h>
33#include <linux/initrd.h>
34#include <linux/timer.h>
35
36#include <asm/io.h>
37#include <asm/prom.h>
38#include <asm/pci-bridge.h>
39#include <asm/dma.h>
40#include <asm/machdep.h>
41#include <asm/irq.h>
42#include <asm/hydra.h>
43#include <asm/sections.h>
44#include <asm/time.h>
45#include <asm/i8259.h>
46#include <asm/mpic.h>
47#include <asm/rtas.h>
48#include <asm/xmon.h>
49
50#include "chrp.h"
51#include "gg2.h"
52
53void rtas_indicator_progress(char *, unsigned short);
54
55int _chrp_type;
56EXPORT_SYMBOL(_chrp_type);
57
58static struct mpic *chrp_mpic;
59
60/* Used for doing CHRP event-scans */
61DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
62unsigned long event_scan_interval;
63
64extern unsigned long loops_per_jiffy;
65
66/* To be replaced by RTAS when available */
67static unsigned int __iomem *briq_SPOR;
68
69#ifdef CONFIG_SMP
70extern struct smp_ops_t chrp_smp_ops;
71#endif
72
73static const char *gg2_memtypes[4] = {
74	"FPM", "SDRAM", "EDO", "BEDO"
75};
76static const char *gg2_cachesizes[4] = {
77	"256 KB", "512 KB", "1 MB", "Reserved"
78};
79static const char *gg2_cachetypes[4] = {
80	"Asynchronous", "Reserved", "Flow-Through Synchronous",
81	"Pipelined Synchronous"
82};
83static const char *gg2_cachemodes[4] = {
84	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
85};
86
87static const char *chrp_names[] = {
88	"Unknown",
89	"","","",
90	"Motorola",
91	"IBM or Longtrail",
92	"Genesi Pegasos",
93	"Total Impact Briq"
94};
95
96static void chrp_show_cpuinfo(struct seq_file *m)
97{
98	int i, sdramen;
99	unsigned int t;
100	struct device_node *root;
101	const char *model = "";
102
103	root = of_find_node_by_path("/");
104	if (root)
105		model = of_get_property(root, "model", NULL);
106	seq_printf(m, "machine\t\t: CHRP %s\n", model);
107
108	/* longtrail (goldengate) stuff */
109	if (model && !strncmp(model, "IBM,LongTrail", 13)) {
110		/* VLSI VAS96011/12 `Golden Gate 2' */
111		/* Memory banks */
112		sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
113			   >>31) & 1;
114		for (i = 0; i < (sdramen ? 4 : 6); i++) {
115			t = in_le32(gg2_pci_config_base+
116						 GG2_PCI_DRAM_BANK0+
117						 i*4);
118			if (!(t & 1))
119				continue;
120			switch ((t>>8) & 0x1f) {
121			case 0x1f:
122				model = "4 MB";
123				break;
124			case 0x1e:
125				model = "8 MB";
126				break;
127			case 0x1c:
128				model = "16 MB";
129				break;
130			case 0x18:
131				model = "32 MB";
132				break;
133			case 0x10:
134				model = "64 MB";
135				break;
136			case 0x00:
137				model = "128 MB";
138				break;
139			default:
140				model = "Reserved";
141				break;
142			}
143			seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
144				   gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
145		}
146		/* L2 cache */
147		t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
148		seq_printf(m, "board l2\t: %s %s (%s)\n",
149			   gg2_cachesizes[(t>>7) & 3],
150			   gg2_cachetypes[(t>>2) & 3],
151			   gg2_cachemodes[t & 3]);
152	}
153	of_node_put(root);
154}
155
156/*
157 *  Fixes for the National Semiconductor PC78308VUL SuperI/O
158 *
159 *  Some versions of Open Firmware incorrectly initialize the IRQ settings
160 *  for keyboard and mouse
161 */
162static inline void __init sio_write(u8 val, u8 index)
163{
164	outb(index, 0x15c);
165	outb(val, 0x15d);
166}
167
168static inline u8 __init sio_read(u8 index)
169{
170	outb(index, 0x15c);
171	return inb(0x15d);
172}
173
174static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
175				     u8 type)
176{
177	u8 level0, type0, active;
178
179	/* select logical device */
180	sio_write(device, 0x07);
181	active = sio_read(0x30);
182	level0 = sio_read(0x70);
183	type0 = sio_read(0x71);
184	if (level0 != level || type0 != type || !active) {
185		printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
186		       "remapping to level %d, type %d, active\n",
187		       name, level0, type0, !active ? "in" : "", level, type);
188		sio_write(0x01, 0x30);
189		sio_write(level, 0x70);
190		sio_write(type, 0x71);
191	}
192}
193
194static void __init sio_init(void)
195{
196	struct device_node *root;
197	const char *model;
198
199	root = of_find_node_by_path("/");
200	if (!root)
201		return;
202
203	model = of_get_property(root, "model", NULL);
204	if (model && !strncmp(model, "IBM,LongTrail", 13)) {
205		/* logical device 0 (KBC/Keyboard) */
206		sio_fixup_irq("keyboard", 0, 1, 2);
207		/* select logical device 1 (KBC/Mouse) */
208		sio_fixup_irq("mouse", 1, 12, 2);
209	}
210
211	of_node_put(root);
212}
213
214
215static void __init pegasos_set_l2cr(void)
216{
217	struct device_node *np;
218
219	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
220	if (_chrp_type != _CHRP_Pegasos)
221		return;
222
223	/* Enable L2 cache if needed */
224	np = of_find_node_by_type(NULL, "cpu");
225	if (np != NULL) {
226		const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
227		if (l2cr == NULL) {
228			printk ("Pegasos l2cr : no cpu l2cr property found\n");
229			goto out;
230		}
231		if (!((*l2cr) & 0x80000000)) {
232			printk ("Pegasos l2cr : L2 cache was not active, "
233				"activating\n");
234			_set_L2CR(0);
235			_set_L2CR((*l2cr) | 0x80000000);
236		}
237	}
238out:
239	of_node_put(np);
240}
241
242static void __noreturn briq_restart(char *cmd)
243{
244	local_irq_disable();
245	if (briq_SPOR)
246		out_be32(briq_SPOR, 0);
247	for(;;);
248}
249
250/*
251 * Per default, input/output-device points to the keyboard/screen
252 * If no card is installed, the built-in serial port is used as a fallback.
253 * But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
254 * the the built-in serial node. Instead, a /failsafe node is created.
255 */
256static __init void chrp_init(void)
257{
258	struct device_node *node;
259	const char *property;
260
261	if (strstr(boot_command_line, "console="))
262		return;
263	/* find the boot console from /chosen/stdout */
264	if (!of_chosen)
265		return;
266	node = of_find_node_by_path("/");
267	if (!node)
268		return;
269	property = of_get_property(node, "model", NULL);
270	if (!property)
271		goto out_put;
272	if (strcmp(property, "Pegasos2"))
273		goto out_put;
274	/* this is a Pegasos2 */
275	property = of_get_property(of_chosen, "linux,stdout-path", NULL);
276	if (!property)
277		goto out_put;
278	of_node_put(node);
279	node = of_find_node_by_path(property);
280	if (!node)
281		return;
282	if (!of_node_is_type(node, "serial"))
283		goto out_put;
284	/*
285	 * The 9pin connector is either /failsafe
286	 * or /pci@80000000/isa@C/serial@i2F8
287	 * The optional graphics card has also type 'serial' in VGA mode.
288	 */
289	if (of_node_name_eq(node, "failsafe") || of_node_name_eq(node, "serial"))
290		add_preferred_console("ttyS", 0, NULL);
291out_put:
292	of_node_put(node);
293}
294
295static void __init chrp_setup_arch(void)
296{
297	struct device_node *root = of_find_node_by_path("/");
298	const char *machine = NULL;
299
300	/* init to some ~sane value until calibrate_delay() runs */
301	loops_per_jiffy = 50000000/HZ;
302
303	if (root)
304		machine = of_get_property(root, "model", NULL);
305	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
306		_chrp_type = _CHRP_Pegasos;
307	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
308		_chrp_type = _CHRP_IBM;
309	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
310		_chrp_type = _CHRP_Motorola;
311	} else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
312		_chrp_type = _CHRP_briq;
313		/* Map the SPOR register on briq and change the restart hook */
314		briq_SPOR = ioremap(0xff0000e8, 4);
315		ppc_md.restart = briq_restart;
316	} else {
317		/* Let's assume it is an IBM chrp if all else fails */
318		_chrp_type = _CHRP_IBM;
319	}
320	of_node_put(root);
321	printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
322
323	rtas_initialize();
324	if (rtas_token("display-character") >= 0)
325		ppc_md.progress = rtas_progress;
326
327	/* use RTAS time-of-day routines if available */
328	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
329		ppc_md.get_boot_time	= rtas_get_boot_time;
330		ppc_md.get_rtc_time	= rtas_get_rtc_time;
331		ppc_md.set_rtc_time	= rtas_set_rtc_time;
332	}
333
334	/* On pegasos, enable the L2 cache if not already done by OF */
335	pegasos_set_l2cr();
336
337	/* Lookup PCI host bridges */
338	chrp_find_bridges();
339
340	/*
341	 *  Temporary fixes for PCI devices.
342	 *  -- Geert
343	 */
344	hydra_init();		/* Mac I/O */
345
346	/*
347	 *  Fix the Super I/O configuration
348	 */
349	sio_init();
350
351	pci_create_OF_bus_map();
352
353	/*
354	 * Print the banner, then scroll down so boot progress
355	 * can be printed.  -- Cort
356	 */
357	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
358}
359
360static void chrp_8259_cascade(struct irq_desc *desc)
361{
362	struct irq_chip *chip = irq_desc_get_chip(desc);
363	unsigned int cascade_irq = i8259_irq();
364
365	if (cascade_irq)
366		generic_handle_irq(cascade_irq);
367
368	chip->irq_eoi(&desc->irq_data);
369}
370
371/*
372 * Finds the open-pic node and sets up the mpic driver.
373 */
374static void __init chrp_find_openpic(void)
375{
376	struct device_node *np, *root;
377	int len, i, j;
378	int isu_size;
379	const unsigned int *iranges, *opprop = NULL;
380	int oplen = 0;
381	unsigned long opaddr;
382	int na = 1;
383
384	np = of_find_node_by_type(NULL, "open-pic");
385	if (np == NULL)
386		return;
387	root = of_find_node_by_path("/");
388	if (root) {
389		opprop = of_get_property(root, "platform-open-pic", &oplen);
390		na = of_n_addr_cells(root);
391	}
392	if (opprop && oplen >= na * sizeof(unsigned int)) {
393		opaddr = opprop[na-1];	/* assume 32-bit */
394		oplen /= na * sizeof(unsigned int);
395	} else {
396		struct resource r;
397		if (of_address_to_resource(np, 0, &r)) {
398			goto bail;
399		}
400		opaddr = r.start;
401		oplen = 0;
402	}
403
404	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
405
406	iranges = of_get_property(np, "interrupt-ranges", &len);
407	if (iranges == NULL)
408		len = 0;	/* non-distributed mpic */
409	else
410		len /= 2 * sizeof(unsigned int);
411
412	/*
413	 * The first pair of cells in interrupt-ranges refers to the
414	 * IDU; subsequent pairs refer to the ISUs.
415	 */
416	if (oplen < len) {
417		printk(KERN_ERR "Insufficient addresses for distributed"
418		       " OpenPIC (%d < %d)\n", oplen, len);
419		len = oplen;
420	}
421
422	isu_size = 0;
423	if (len > 0 && iranges[1] != 0) {
424		printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
425		       iranges[0], iranges[0] + iranges[1] - 1);
426	}
427	if (len > 1)
428		isu_size = iranges[3];
429
430	chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET,
431			isu_size, 0, " MPIC    ");
432	if (chrp_mpic == NULL) {
433		printk(KERN_ERR "Failed to allocate MPIC structure\n");
434		goto bail;
435	}
436	j = na - 1;
437	for (i = 1; i < len; ++i) {
438		iranges += 2;
439		j += na;
440		printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
441		       iranges[0], iranges[0] + iranges[1] - 1,
442		       opprop[j]);
443		mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
444	}
445
446	mpic_init(chrp_mpic);
447	ppc_md.get_irq = mpic_get_irq;
448 bail:
449	of_node_put(root);
450	of_node_put(np);
451}
452
453static void __init chrp_find_8259(void)
454{
455	struct device_node *np, *pic = NULL;
456	unsigned long chrp_int_ack = 0;
457	unsigned int cascade_irq;
458
459	/* Look for cascade */
460	for_each_node_by_type(np, "interrupt-controller")
461		if (of_device_is_compatible(np, "chrp,iic")) {
462			pic = np;
463			break;
464		}
465	/* Ok, 8259 wasn't found. We need to handle the case where
466	 * we have a pegasos that claims to be chrp but doesn't have
467	 * a proper interrupt tree
468	 */
469	if (pic == NULL && chrp_mpic != NULL) {
470		printk(KERN_ERR "i8259: Not found in device-tree"
471		       " assuming no legacy interrupts\n");
472		return;
473	}
474
475	/* Look for intack. In a perfect world, we would look for it on
476	 * the ISA bus that holds the 8259 but heh... Works that way. If
477	 * we ever see a problem, we can try to re-use the pSeries code here.
478	 * Also, Pegasos-type platforms don't have a proper node to start
479	 * from anyway
480	 */
481	for_each_node_by_name(np, "pci") {
482		const unsigned int *addrp = of_get_property(np,
483				"8259-interrupt-acknowledge", NULL);
484
485		if (addrp == NULL)
486			continue;
487		chrp_int_ack = addrp[of_n_addr_cells(np)-1];
488		break;
489	}
490	of_node_put(np);
491	if (np == NULL)
492		printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
493		       " address, polling\n");
494
495	i8259_init(pic, chrp_int_ack);
496	if (ppc_md.get_irq == NULL) {
497		ppc_md.get_irq = i8259_irq;
498		irq_set_default_host(i8259_get_host());
499	}
500	if (chrp_mpic != NULL) {
501		cascade_irq = irq_of_parse_and_map(pic, 0);
502		if (!cascade_irq)
503			printk(KERN_ERR "i8259: failed to map cascade irq\n");
504		else
505			irq_set_chained_handler(cascade_irq,
506						chrp_8259_cascade);
507	}
508}
509
510static void __init chrp_init_IRQ(void)
511{
512#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
513	struct device_node *kbd;
514#endif
515	chrp_find_openpic();
516	chrp_find_8259();
517
518#ifdef CONFIG_SMP
519	/* Pegasos has no MPIC, those ops would make it crash. It might be an
520	 * option to move setting them to after we probe the PIC though
521	 */
522	if (chrp_mpic != NULL)
523		smp_ops = &chrp_smp_ops;
524#endif /* CONFIG_SMP */
525
526	if (_chrp_type == _CHRP_Pegasos)
527		ppc_md.get_irq        = i8259_irq;
528
529#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
530	/* see if there is a keyboard in the device tree
531	   with a parent of type "adb" */
532	for_each_node_by_name(kbd, "keyboard")
533		if (of_node_is_type(kbd->parent, "adb"))
534			break;
535	of_node_put(kbd);
536	if (kbd) {
537		if (request_irq(HYDRA_INT_ADB_NMI, xmon_irq, 0, "XMON break",
538				NULL))
539			pr_err("Failed to register XMON break interrupt\n");
540	}
541#endif
542}
543
544static void __init
545chrp_init2(void)
546{
547#if IS_ENABLED(CONFIG_NVRAM)
548	chrp_nvram_init();
549#endif
550
551	request_region(0x20,0x20,"pic1");
552	request_region(0xa0,0x20,"pic2");
553	request_region(0x00,0x20,"dma1");
554	request_region(0x40,0x20,"timer");
555	request_region(0x80,0x10,"dma page reg");
556	request_region(0xc0,0x20,"dma2");
557
558	if (ppc_md.progress)
559		ppc_md.progress("  Have fun!    ", 0x7777);
560}
561
562static int __init chrp_probe(void)
563{
564	const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
565						"device_type", NULL);
566 	if (dtype == NULL)
567 		return 0;
568 	if (strcmp(dtype, "chrp"))
569		return 0;
570
571	DMA_MODE_READ = 0x44;
572	DMA_MODE_WRITE = 0x48;
573
574	pm_power_off = rtas_power_off;
575
576	chrp_init();
577
578	return 1;
579}
580
581define_machine(chrp) {
582	.name			= "CHRP",
583	.probe			= chrp_probe,
584	.setup_arch		= chrp_setup_arch,
585	.init			= chrp_init2,
586	.show_cpuinfo		= chrp_show_cpuinfo,
587	.init_IRQ		= chrp_init_IRQ,
588	.restart		= rtas_restart,
589	.halt			= rtas_halt,
590	.time_init		= chrp_time_init,
591	.set_rtc_time		= chrp_set_rtc_time,
592	.get_rtc_time		= chrp_get_rtc_time,
593	.calibrate_decr		= generic_calibrate_decr,
594	.phys_mem_access_prot	= pci_phys_mem_access_prot,
595};
596