18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * Copyright (C) 1997 Geert Uytterhoeven 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * This file is based on the following documentation: 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * The VAS96011/12 Chipset, Data Book, Edition 1.0 98c2ecf20Sopenharmony_ci * VLSI Technology, Inc. 108c2ecf20Sopenharmony_ci * 118c2ecf20Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General Public 128c2ecf20Sopenharmony_ci * License. See the file COPYING in the main directory of this archive 138c2ecf20Sopenharmony_ci * for more details. 148c2ecf20Sopenharmony_ci */ 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#ifndef _ASMPPC_GG2_H 178c2ecf20Sopenharmony_ci#define _ASMPPC_GG2_H 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci /* 208c2ecf20Sopenharmony_ci * Memory Map (CHRP mode) 218c2ecf20Sopenharmony_ci */ 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci#define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ 248c2ecf20Sopenharmony_ci#define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ 258c2ecf20Sopenharmony_ci#define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ 268c2ecf20Sopenharmony_ci#define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ 278c2ecf20Sopenharmony_ci#define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ 288c2ecf20Sopenharmony_ci /* special PCI cycles */ 298c2ecf20Sopenharmony_ci#define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ 308c2ecf20Sopenharmony_ci#define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci /* 348c2ecf20Sopenharmony_ci * GG2 specific PCI Registers 358c2ecf20Sopenharmony_ci */ 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ciextern void __iomem *gg2_pci_config_base; /* kernel virtual address */ 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci#define GG2_PCI_BUSNO 0x40 /* Bus number */ 408c2ecf20Sopenharmony_ci#define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ 418c2ecf20Sopenharmony_ci#define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ 428c2ecf20Sopenharmony_ci#define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ 438c2ecf20Sopenharmony_ci#define GG2_PCI_ADDR_MAP 0x5c /* Address map */ 448c2ecf20Sopenharmony_ci#define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ 458c2ecf20Sopenharmony_ci#define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ 468c2ecf20Sopenharmony_ci#define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ 478c2ecf20Sopenharmony_ci#define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ 488c2ecf20Sopenharmony_ci#define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ 498c2ecf20Sopenharmony_ci#define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ 508c2ecf20Sopenharmony_ci#define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ 518c2ecf20Sopenharmony_ci#define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ 528c2ecf20Sopenharmony_ci#define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ 538c2ecf20Sopenharmony_ci#define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ 548c2ecf20Sopenharmony_ci#define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ 558c2ecf20Sopenharmony_ci#define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ 568c2ecf20Sopenharmony_ci#define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ 578c2ecf20Sopenharmony_ci#define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ 588c2ecf20Sopenharmony_ci#define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ 598c2ecf20Sopenharmony_ci /* Cleared when read */ 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci#endif /* _ASMPPC_GG2_H */ 62