1// SPDX-License-Identifier: GPL-2.0 2/* 3 * General Purpose functions for the global management of the 4 * Communication Processor Module. 5 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) 6 * 7 * In addition to the individual control of the communication 8 * channels, there are a few functions that globally affect the 9 * communication processor. 10 * 11 * Buffer descriptors must be allocated from the dual ported memory 12 * space. The allocator for that is here. When the communication 13 * process is reset, we reclaim the memory available. There is 14 * currently no deallocator for this memory. 15 * The amount of space available is platform dependent. On the 16 * MBX, the EPPC software loads additional microcode into the 17 * communication processor, and uses some of the DP ram for this 18 * purpose. Current, the first 512 bytes and the last 256 bytes of 19 * memory are used. Right now I am conservative and only use the 20 * memory that can never be used for microcode. If there are 21 * applications that require more DP ram, we can expand the boundaries 22 * but then we have to be careful of any downloaded microcode. 23 */ 24#include <linux/errno.h> 25#include <linux/sched.h> 26#include <linux/kernel.h> 27#include <linux/dma-mapping.h> 28#include <linux/param.h> 29#include <linux/string.h> 30#include <linux/mm.h> 31#include <linux/interrupt.h> 32#include <linux/irq.h> 33#include <linux/module.h> 34#include <linux/spinlock.h> 35#include <linux/slab.h> 36#include <asm/page.h> 37#include <asm/8xx_immap.h> 38#include <asm/cpm1.h> 39#include <asm/io.h> 40#include <asm/rheap.h> 41#include <asm/prom.h> 42#include <asm/cpm.h> 43 44#include <asm/fs_pd.h> 45 46#ifdef CONFIG_8xx_GPIO 47#include <linux/of_gpio.h> 48#endif 49 50#define CPM_MAP_SIZE (0x4000) 51 52cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */ 53immap_t __iomem *mpc8xx_immr = (void __iomem *)VIRT_IMMR_BASE; 54static cpic8xx_t __iomem *cpic_reg; 55 56static struct irq_domain *cpm_pic_host; 57 58static void cpm_mask_irq(struct irq_data *d) 59{ 60 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); 61 62 clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); 63} 64 65static void cpm_unmask_irq(struct irq_data *d) 66{ 67 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); 68 69 setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); 70} 71 72static void cpm_end_irq(struct irq_data *d) 73{ 74 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); 75 76 out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec)); 77} 78 79static struct irq_chip cpm_pic = { 80 .name = "CPM PIC", 81 .irq_mask = cpm_mask_irq, 82 .irq_unmask = cpm_unmask_irq, 83 .irq_eoi = cpm_end_irq, 84}; 85 86int cpm_get_irq(void) 87{ 88 int cpm_vec; 89 90 /* 91 * Get the vector by setting the ACK bit and then reading 92 * the register. 93 */ 94 out_be16(&cpic_reg->cpic_civr, 1); 95 cpm_vec = in_be16(&cpic_reg->cpic_civr); 96 cpm_vec >>= 11; 97 98 return irq_linear_revmap(cpm_pic_host, cpm_vec); 99} 100 101static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq, 102 irq_hw_number_t hw) 103{ 104 pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); 105 106 irq_set_status_flags(virq, IRQ_LEVEL); 107 irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); 108 return 0; 109} 110 111/* 112 * The CPM can generate the error interrupt when there is a race condition 113 * between generating and masking interrupts. All we have to do is ACK it 114 * and return. This is a no-op function so we don't need any special 115 * tests in the interrupt handler. 116 */ 117static irqreturn_t cpm_error_interrupt(int irq, void *dev) 118{ 119 return IRQ_HANDLED; 120} 121 122static const struct irq_domain_ops cpm_pic_host_ops = { 123 .map = cpm_pic_host_map, 124}; 125 126unsigned int __init cpm_pic_init(void) 127{ 128 struct device_node *np = NULL; 129 struct resource res; 130 unsigned int sirq = 0, hwirq, eirq; 131 int ret; 132 133 pr_debug("cpm_pic_init\n"); 134 135 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic"); 136 if (np == NULL) 137 np = of_find_compatible_node(NULL, "cpm-pic", "CPM"); 138 if (np == NULL) { 139 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n"); 140 return sirq; 141 } 142 143 ret = of_address_to_resource(np, 0, &res); 144 if (ret) 145 goto end; 146 147 cpic_reg = ioremap(res.start, resource_size(&res)); 148 if (cpic_reg == NULL) 149 goto end; 150 151 sirq = irq_of_parse_and_map(np, 0); 152 if (!sirq) 153 goto end; 154 155 /* Initialize the CPM interrupt controller. */ 156 hwirq = (unsigned int)virq_to_hw(sirq); 157 out_be32(&cpic_reg->cpic_cicr, 158 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | 159 ((hwirq/2) << 13) | CICR_HP_MASK); 160 161 out_be32(&cpic_reg->cpic_cimr, 0); 162 163 cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL); 164 if (cpm_pic_host == NULL) { 165 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n"); 166 sirq = 0; 167 goto end; 168 } 169 170 /* Install our own error handler. */ 171 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1"); 172 if (np == NULL) 173 np = of_find_node_by_type(NULL, "cpm"); 174 if (np == NULL) { 175 printk(KERN_ERR "CPM PIC init: can not find cpm node\n"); 176 goto end; 177 } 178 179 eirq = irq_of_parse_and_map(np, 0); 180 if (!eirq) 181 goto end; 182 183 if (request_irq(eirq, cpm_error_interrupt, IRQF_NO_THREAD, "error", 184 NULL)) 185 printk(KERN_ERR "Could not allocate CPM error IRQ!"); 186 187 setbits32(&cpic_reg->cpic_cicr, CICR_IEN); 188 189end: 190 of_node_put(np); 191 return sirq; 192} 193 194void __init cpm_reset(void) 195{ 196 sysconf8xx_t __iomem *siu_conf; 197 198 cpmp = &mpc8xx_immr->im_cpm; 199 200#ifndef CONFIG_PPC_EARLY_DEBUG_CPM 201 /* Perform a reset. */ 202 out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); 203 204 /* Wait for it. */ 205 while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG); 206#endif 207 208#ifdef CONFIG_UCODE_PATCH 209 cpm_load_patch(cpmp); 210#endif 211 212 /* 213 * Set SDMA Bus Request priority 5. 214 * On 860T, this also enables FEC priority 6. I am not sure 215 * this is what we really want for some applications, but the 216 * manual recommends it. 217 * Bit 25, FAM can also be set to use FEC aggressive mode (860T). 218 */ 219 siu_conf = immr_map(im_siu_conf); 220 if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */ 221 out_be32(&siu_conf->sc_sdcr, 0x40); 222 else 223 out_be32(&siu_conf->sc_sdcr, 1); 224 immr_unmap(siu_conf); 225} 226 227static DEFINE_SPINLOCK(cmd_lock); 228 229#define MAX_CR_CMD_LOOPS 10000 230 231int cpm_command(u32 command, u8 opcode) 232{ 233 int i, ret; 234 unsigned long flags; 235 236 if (command & 0xffffff0f) 237 return -EINVAL; 238 239 spin_lock_irqsave(&cmd_lock, flags); 240 241 ret = 0; 242 out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8)); 243 for (i = 0; i < MAX_CR_CMD_LOOPS; i++) 244 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) 245 goto out; 246 247 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__); 248 ret = -EIO; 249out: 250 spin_unlock_irqrestore(&cmd_lock, flags); 251 return ret; 252} 253EXPORT_SYMBOL(cpm_command); 254 255/* 256 * Set a baud rate generator. This needs lots of work. There are 257 * four BRGs, any of which can be wired to any channel. 258 * The internal baud rate clock is the system clock divided by 16. 259 * This assumes the baudrate is 16x oversampled by the uart. 260 */ 261#define BRG_INT_CLK (get_brgfreq()) 262#define BRG_UART_CLK (BRG_INT_CLK/16) 263#define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16) 264 265void 266cpm_setbrg(uint brg, uint rate) 267{ 268 u32 __iomem *bp; 269 270 /* This is good enough to get SMCs running..... */ 271 bp = &cpmp->cp_brgc1; 272 bp += brg; 273 /* 274 * The BRG has a 12-bit counter. For really slow baud rates (or 275 * really fast processors), we may have to further divide by 16. 276 */ 277 if (((BRG_UART_CLK / rate) - 1) < 4096) 278 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN); 279 else 280 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) | 281 CPM_BRG_EN | CPM_BRG_DIV16); 282} 283EXPORT_SYMBOL(cpm_setbrg); 284 285struct cpm_ioport16 { 286 __be16 dir, par, odr_sor, dat, intr; 287 __be16 res[3]; 288}; 289 290struct cpm_ioport32b { 291 __be32 dir, par, odr, dat; 292}; 293 294struct cpm_ioport32e { 295 __be32 dir, par, sor, odr, dat; 296}; 297 298static void __init cpm1_set_pin32(int port, int pin, int flags) 299{ 300 struct cpm_ioport32e __iomem *iop; 301 pin = 1 << (31 - pin); 302 303 if (port == CPM_PORTB) 304 iop = (struct cpm_ioport32e __iomem *) 305 &mpc8xx_immr->im_cpm.cp_pbdir; 306 else 307 iop = (struct cpm_ioport32e __iomem *) 308 &mpc8xx_immr->im_cpm.cp_pedir; 309 310 if (flags & CPM_PIN_OUTPUT) 311 setbits32(&iop->dir, pin); 312 else 313 clrbits32(&iop->dir, pin); 314 315 if (!(flags & CPM_PIN_GPIO)) 316 setbits32(&iop->par, pin); 317 else 318 clrbits32(&iop->par, pin); 319 320 if (port == CPM_PORTB) { 321 if (flags & CPM_PIN_OPENDRAIN) 322 setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); 323 else 324 clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); 325 } 326 327 if (port == CPM_PORTE) { 328 if (flags & CPM_PIN_SECONDARY) 329 setbits32(&iop->sor, pin); 330 else 331 clrbits32(&iop->sor, pin); 332 333 if (flags & CPM_PIN_OPENDRAIN) 334 setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); 335 else 336 clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); 337 } 338} 339 340static void __init cpm1_set_pin16(int port, int pin, int flags) 341{ 342 struct cpm_ioport16 __iomem *iop = 343 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport; 344 345 pin = 1 << (15 - pin); 346 347 if (port != 0) 348 iop += port - 1; 349 350 if (flags & CPM_PIN_OUTPUT) 351 setbits16(&iop->dir, pin); 352 else 353 clrbits16(&iop->dir, pin); 354 355 if (!(flags & CPM_PIN_GPIO)) 356 setbits16(&iop->par, pin); 357 else 358 clrbits16(&iop->par, pin); 359 360 if (port == CPM_PORTA) { 361 if (flags & CPM_PIN_OPENDRAIN) 362 setbits16(&iop->odr_sor, pin); 363 else 364 clrbits16(&iop->odr_sor, pin); 365 } 366 if (port == CPM_PORTC) { 367 if (flags & CPM_PIN_SECONDARY) 368 setbits16(&iop->odr_sor, pin); 369 else 370 clrbits16(&iop->odr_sor, pin); 371 if (flags & CPM_PIN_FALLEDGE) 372 setbits16(&iop->intr, pin); 373 else 374 clrbits16(&iop->intr, pin); 375 } 376} 377 378void __init cpm1_set_pin(enum cpm_port port, int pin, int flags) 379{ 380 if (port == CPM_PORTB || port == CPM_PORTE) 381 cpm1_set_pin32(port, pin, flags); 382 else 383 cpm1_set_pin16(port, pin, flags); 384} 385 386int __init cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode) 387{ 388 int shift; 389 int i, bits = 0; 390 u32 __iomem *reg; 391 u32 mask = 7; 392 393 u8 clk_map[][3] = { 394 {CPM_CLK_SCC1, CPM_BRG1, 0}, 395 {CPM_CLK_SCC1, CPM_BRG2, 1}, 396 {CPM_CLK_SCC1, CPM_BRG3, 2}, 397 {CPM_CLK_SCC1, CPM_BRG4, 3}, 398 {CPM_CLK_SCC1, CPM_CLK1, 4}, 399 {CPM_CLK_SCC1, CPM_CLK2, 5}, 400 {CPM_CLK_SCC1, CPM_CLK3, 6}, 401 {CPM_CLK_SCC1, CPM_CLK4, 7}, 402 403 {CPM_CLK_SCC2, CPM_BRG1, 0}, 404 {CPM_CLK_SCC2, CPM_BRG2, 1}, 405 {CPM_CLK_SCC2, CPM_BRG3, 2}, 406 {CPM_CLK_SCC2, CPM_BRG4, 3}, 407 {CPM_CLK_SCC2, CPM_CLK1, 4}, 408 {CPM_CLK_SCC2, CPM_CLK2, 5}, 409 {CPM_CLK_SCC2, CPM_CLK3, 6}, 410 {CPM_CLK_SCC2, CPM_CLK4, 7}, 411 412 {CPM_CLK_SCC3, CPM_BRG1, 0}, 413 {CPM_CLK_SCC3, CPM_BRG2, 1}, 414 {CPM_CLK_SCC3, CPM_BRG3, 2}, 415 {CPM_CLK_SCC3, CPM_BRG4, 3}, 416 {CPM_CLK_SCC3, CPM_CLK5, 4}, 417 {CPM_CLK_SCC3, CPM_CLK6, 5}, 418 {CPM_CLK_SCC3, CPM_CLK7, 6}, 419 {CPM_CLK_SCC3, CPM_CLK8, 7}, 420 421 {CPM_CLK_SCC4, CPM_BRG1, 0}, 422 {CPM_CLK_SCC4, CPM_BRG2, 1}, 423 {CPM_CLK_SCC4, CPM_BRG3, 2}, 424 {CPM_CLK_SCC4, CPM_BRG4, 3}, 425 {CPM_CLK_SCC4, CPM_CLK5, 4}, 426 {CPM_CLK_SCC4, CPM_CLK6, 5}, 427 {CPM_CLK_SCC4, CPM_CLK7, 6}, 428 {CPM_CLK_SCC4, CPM_CLK8, 7}, 429 430 {CPM_CLK_SMC1, CPM_BRG1, 0}, 431 {CPM_CLK_SMC1, CPM_BRG2, 1}, 432 {CPM_CLK_SMC1, CPM_BRG3, 2}, 433 {CPM_CLK_SMC1, CPM_BRG4, 3}, 434 {CPM_CLK_SMC1, CPM_CLK1, 4}, 435 {CPM_CLK_SMC1, CPM_CLK2, 5}, 436 {CPM_CLK_SMC1, CPM_CLK3, 6}, 437 {CPM_CLK_SMC1, CPM_CLK4, 7}, 438 439 {CPM_CLK_SMC2, CPM_BRG1, 0}, 440 {CPM_CLK_SMC2, CPM_BRG2, 1}, 441 {CPM_CLK_SMC2, CPM_BRG3, 2}, 442 {CPM_CLK_SMC2, CPM_BRG4, 3}, 443 {CPM_CLK_SMC2, CPM_CLK5, 4}, 444 {CPM_CLK_SMC2, CPM_CLK6, 5}, 445 {CPM_CLK_SMC2, CPM_CLK7, 6}, 446 {CPM_CLK_SMC2, CPM_CLK8, 7}, 447 }; 448 449 switch (target) { 450 case CPM_CLK_SCC1: 451 reg = &mpc8xx_immr->im_cpm.cp_sicr; 452 shift = 0; 453 break; 454 455 case CPM_CLK_SCC2: 456 reg = &mpc8xx_immr->im_cpm.cp_sicr; 457 shift = 8; 458 break; 459 460 case CPM_CLK_SCC3: 461 reg = &mpc8xx_immr->im_cpm.cp_sicr; 462 shift = 16; 463 break; 464 465 case CPM_CLK_SCC4: 466 reg = &mpc8xx_immr->im_cpm.cp_sicr; 467 shift = 24; 468 break; 469 470 case CPM_CLK_SMC1: 471 reg = &mpc8xx_immr->im_cpm.cp_simode; 472 shift = 12; 473 break; 474 475 case CPM_CLK_SMC2: 476 reg = &mpc8xx_immr->im_cpm.cp_simode; 477 shift = 28; 478 break; 479 480 default: 481 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n"); 482 return -EINVAL; 483 } 484 485 for (i = 0; i < ARRAY_SIZE(clk_map); i++) { 486 if (clk_map[i][0] == target && clk_map[i][1] == clock) { 487 bits = clk_map[i][2]; 488 break; 489 } 490 } 491 492 if (i == ARRAY_SIZE(clk_map)) { 493 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n"); 494 return -EINVAL; 495 } 496 497 bits <<= shift; 498 mask <<= shift; 499 500 if (reg == &mpc8xx_immr->im_cpm.cp_sicr) { 501 if (mode == CPM_CLK_RTX) { 502 bits |= bits << 3; 503 mask |= mask << 3; 504 } else if (mode == CPM_CLK_RX) { 505 bits <<= 3; 506 mask <<= 3; 507 } 508 } 509 510 out_be32(reg, (in_be32(reg) & ~mask) | bits); 511 512 return 0; 513} 514 515/* 516 * GPIO LIB API implementation 517 */ 518#ifdef CONFIG_8xx_GPIO 519 520struct cpm1_gpio16_chip { 521 struct of_mm_gpio_chip mm_gc; 522 spinlock_t lock; 523 524 /* shadowed data register to clear/set bits safely */ 525 u16 cpdata; 526 527 /* IRQ associated with Pins when relevant */ 528 int irq[16]; 529}; 530 531static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc) 532{ 533 struct cpm1_gpio16_chip *cpm1_gc = 534 container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc); 535 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 536 537 cpm1_gc->cpdata = in_be16(&iop->dat); 538} 539 540static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio) 541{ 542 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 543 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 544 u16 pin_mask; 545 546 pin_mask = 1 << (15 - gpio); 547 548 return !!(in_be16(&iop->dat) & pin_mask); 549} 550 551static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask, 552 int value) 553{ 554 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 555 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 556 557 if (value) 558 cpm1_gc->cpdata |= pin_mask; 559 else 560 cpm1_gc->cpdata &= ~pin_mask; 561 562 out_be16(&iop->dat, cpm1_gc->cpdata); 563} 564 565static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value) 566{ 567 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 568 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 569 unsigned long flags; 570 u16 pin_mask = 1 << (15 - gpio); 571 572 spin_lock_irqsave(&cpm1_gc->lock, flags); 573 574 __cpm1_gpio16_set(mm_gc, pin_mask, value); 575 576 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 577} 578 579static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio) 580{ 581 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 582 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 583 584 return cpm1_gc->irq[gpio] ? : -ENXIO; 585} 586 587static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 588{ 589 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 590 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 591 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 592 unsigned long flags; 593 u16 pin_mask = 1 << (15 - gpio); 594 595 spin_lock_irqsave(&cpm1_gc->lock, flags); 596 597 setbits16(&iop->dir, pin_mask); 598 __cpm1_gpio16_set(mm_gc, pin_mask, val); 599 600 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 601 602 return 0; 603} 604 605static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio) 606{ 607 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 608 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 609 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 610 unsigned long flags; 611 u16 pin_mask = 1 << (15 - gpio); 612 613 spin_lock_irqsave(&cpm1_gc->lock, flags); 614 615 clrbits16(&iop->dir, pin_mask); 616 617 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 618 619 return 0; 620} 621 622int cpm1_gpiochip_add16(struct device *dev) 623{ 624 struct device_node *np = dev->of_node; 625 struct cpm1_gpio16_chip *cpm1_gc; 626 struct of_mm_gpio_chip *mm_gc; 627 struct gpio_chip *gc; 628 u16 mask; 629 630 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); 631 if (!cpm1_gc) 632 return -ENOMEM; 633 634 spin_lock_init(&cpm1_gc->lock); 635 636 if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) { 637 int i, j; 638 639 for (i = 0, j = 0; i < 16; i++) 640 if (mask & (1 << (15 - i))) 641 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++); 642 } 643 644 mm_gc = &cpm1_gc->mm_gc; 645 gc = &mm_gc->gc; 646 647 mm_gc->save_regs = cpm1_gpio16_save_regs; 648 gc->ngpio = 16; 649 gc->direction_input = cpm1_gpio16_dir_in; 650 gc->direction_output = cpm1_gpio16_dir_out; 651 gc->get = cpm1_gpio16_get; 652 gc->set = cpm1_gpio16_set; 653 gc->to_irq = cpm1_gpio16_to_irq; 654 gc->parent = dev; 655 gc->owner = THIS_MODULE; 656 657 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc); 658} 659 660struct cpm1_gpio32_chip { 661 struct of_mm_gpio_chip mm_gc; 662 spinlock_t lock; 663 664 /* shadowed data register to clear/set bits safely */ 665 u32 cpdata; 666}; 667 668static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) 669{ 670 struct cpm1_gpio32_chip *cpm1_gc = 671 container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc); 672 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 673 674 cpm1_gc->cpdata = in_be32(&iop->dat); 675} 676 677static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio) 678{ 679 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 680 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 681 u32 pin_mask; 682 683 pin_mask = 1 << (31 - gpio); 684 685 return !!(in_be32(&iop->dat) & pin_mask); 686} 687 688static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, 689 int value) 690{ 691 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 692 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 693 694 if (value) 695 cpm1_gc->cpdata |= pin_mask; 696 else 697 cpm1_gc->cpdata &= ~pin_mask; 698 699 out_be32(&iop->dat, cpm1_gc->cpdata); 700} 701 702static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 703{ 704 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 705 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 706 unsigned long flags; 707 u32 pin_mask = 1 << (31 - gpio); 708 709 spin_lock_irqsave(&cpm1_gc->lock, flags); 710 711 __cpm1_gpio32_set(mm_gc, pin_mask, value); 712 713 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 714} 715 716static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 717{ 718 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 719 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 720 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 721 unsigned long flags; 722 u32 pin_mask = 1 << (31 - gpio); 723 724 spin_lock_irqsave(&cpm1_gc->lock, flags); 725 726 setbits32(&iop->dir, pin_mask); 727 __cpm1_gpio32_set(mm_gc, pin_mask, val); 728 729 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 730 731 return 0; 732} 733 734static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 735{ 736 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 737 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 738 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 739 unsigned long flags; 740 u32 pin_mask = 1 << (31 - gpio); 741 742 spin_lock_irqsave(&cpm1_gc->lock, flags); 743 744 clrbits32(&iop->dir, pin_mask); 745 746 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 747 748 return 0; 749} 750 751int cpm1_gpiochip_add32(struct device *dev) 752{ 753 struct device_node *np = dev->of_node; 754 struct cpm1_gpio32_chip *cpm1_gc; 755 struct of_mm_gpio_chip *mm_gc; 756 struct gpio_chip *gc; 757 758 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); 759 if (!cpm1_gc) 760 return -ENOMEM; 761 762 spin_lock_init(&cpm1_gc->lock); 763 764 mm_gc = &cpm1_gc->mm_gc; 765 gc = &mm_gc->gc; 766 767 mm_gc->save_regs = cpm1_gpio32_save_regs; 768 gc->ngpio = 32; 769 gc->direction_input = cpm1_gpio32_dir_in; 770 gc->direction_output = cpm1_gpio32_dir_out; 771 gc->get = cpm1_gpio32_get; 772 gc->set = cpm1_gpio32_set; 773 gc->parent = dev; 774 gc->owner = THIS_MODULE; 775 776 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc); 777} 778 779#endif /* CONFIG_8xx_GPIO */ 780