18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * Author: Roy Zang <tie-fei.zang@freescale.com>
68c2ecf20Sopenharmony_ci *
78c2ecf20Sopenharmony_ci * Description:
88c2ecf20Sopenharmony_ci * P1023 RDB Board Setup
98c2ecf20Sopenharmony_ci */
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci#include <linux/kernel.h>
128c2ecf20Sopenharmony_ci#include <linux/init.h>
138c2ecf20Sopenharmony_ci#include <linux/errno.h>
148c2ecf20Sopenharmony_ci#include <linux/pci.h>
158c2ecf20Sopenharmony_ci#include <linux/delay.h>
168c2ecf20Sopenharmony_ci#include <linux/module.h>
178c2ecf20Sopenharmony_ci#include <linux/fsl_devices.h>
188c2ecf20Sopenharmony_ci#include <linux/of_platform.h>
198c2ecf20Sopenharmony_ci#include <linux/of_device.h>
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci#include <asm/time.h>
228c2ecf20Sopenharmony_ci#include <asm/machdep.h>
238c2ecf20Sopenharmony_ci#include <asm/pci-bridge.h>
248c2ecf20Sopenharmony_ci#include <mm/mmu_decl.h>
258c2ecf20Sopenharmony_ci#include <asm/prom.h>
268c2ecf20Sopenharmony_ci#include <asm/udbg.h>
278c2ecf20Sopenharmony_ci#include <asm/mpic.h>
288c2ecf20Sopenharmony_ci#include "smp.h"
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci#include <sysdev/fsl_soc.h>
318c2ecf20Sopenharmony_ci#include <sysdev/fsl_pci.h>
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ci#include "mpc85xx.h"
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci/* ************************************************************************
368c2ecf20Sopenharmony_ci *
378c2ecf20Sopenharmony_ci * Setup the architecture
388c2ecf20Sopenharmony_ci *
398c2ecf20Sopenharmony_ci */
408c2ecf20Sopenharmony_cistatic void __init mpc85xx_rdb_setup_arch(void)
418c2ecf20Sopenharmony_ci{
428c2ecf20Sopenharmony_ci	struct device_node *np;
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ci	if (ppc_md.progress)
458c2ecf20Sopenharmony_ci		ppc_md.progress("p1023_rdb_setup_arch()", 0);
468c2ecf20Sopenharmony_ci
478c2ecf20Sopenharmony_ci	/* Map BCSR area */
488c2ecf20Sopenharmony_ci	np = of_find_node_by_name(NULL, "bcsr");
498c2ecf20Sopenharmony_ci	if (np != NULL) {
508c2ecf20Sopenharmony_ci		static u8 __iomem *bcsr_regs;
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ci		bcsr_regs = of_iomap(np, 0);
538c2ecf20Sopenharmony_ci		of_node_put(np);
548c2ecf20Sopenharmony_ci
558c2ecf20Sopenharmony_ci		if (!bcsr_regs) {
568c2ecf20Sopenharmony_ci			printk(KERN_ERR
578c2ecf20Sopenharmony_ci			       "BCSR: Failed to map bcsr register space\n");
588c2ecf20Sopenharmony_ci			return;
598c2ecf20Sopenharmony_ci		} else {
608c2ecf20Sopenharmony_ci#define BCSR15_I2C_BUS0_SEG_CLR		0x07
618c2ecf20Sopenharmony_ci#define BCSR15_I2C_BUS0_SEG2		0x02
628c2ecf20Sopenharmony_ci/*
638c2ecf20Sopenharmony_ci * Note: Accessing exclusively i2c devices.
648c2ecf20Sopenharmony_ci *
658c2ecf20Sopenharmony_ci * The i2c controller selects initially ID EEPROM in the u-boot;
668c2ecf20Sopenharmony_ci * but if menu configuration selects RTC support in the kernel,
678c2ecf20Sopenharmony_ci * the i2c controller switches to select RTC chip in the kernel.
688c2ecf20Sopenharmony_ci */
698c2ecf20Sopenharmony_ci#ifdef CONFIG_RTC_CLASS
708c2ecf20Sopenharmony_ci			/* Enable RTC chip on the segment #2 of i2c */
718c2ecf20Sopenharmony_ci			clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR);
728c2ecf20Sopenharmony_ci			setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2);
738c2ecf20Sopenharmony_ci#endif
748c2ecf20Sopenharmony_ci
758c2ecf20Sopenharmony_ci			iounmap(bcsr_regs);
768c2ecf20Sopenharmony_ci		}
778c2ecf20Sopenharmony_ci	}
788c2ecf20Sopenharmony_ci
798c2ecf20Sopenharmony_ci	mpc85xx_smp_init();
808c2ecf20Sopenharmony_ci
818c2ecf20Sopenharmony_ci	fsl_pci_assign_primary();
828c2ecf20Sopenharmony_ci}
838c2ecf20Sopenharmony_ci
848c2ecf20Sopenharmony_cimachine_arch_initcall(p1023_rdb, mpc85xx_common_publish_devices);
858c2ecf20Sopenharmony_ci
868c2ecf20Sopenharmony_cistatic void __init mpc85xx_rdb_pic_init(void)
878c2ecf20Sopenharmony_ci{
888c2ecf20Sopenharmony_ci	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
898c2ecf20Sopenharmony_ci		MPIC_SINGLE_DEST_CPU,
908c2ecf20Sopenharmony_ci		0, 256, " OpenPIC  ");
918c2ecf20Sopenharmony_ci
928c2ecf20Sopenharmony_ci	BUG_ON(mpic == NULL);
938c2ecf20Sopenharmony_ci
948c2ecf20Sopenharmony_ci	mpic_init(mpic);
958c2ecf20Sopenharmony_ci}
968c2ecf20Sopenharmony_ci
978c2ecf20Sopenharmony_cistatic int __init p1023_rdb_probe(void)
988c2ecf20Sopenharmony_ci{
998c2ecf20Sopenharmony_ci	return of_machine_is_compatible("fsl,P1023RDB");
1008c2ecf20Sopenharmony_ci
1018c2ecf20Sopenharmony_ci}
1028c2ecf20Sopenharmony_ci
1038c2ecf20Sopenharmony_cidefine_machine(p1023_rdb) {
1048c2ecf20Sopenharmony_ci	.name			= "P1023 RDB",
1058c2ecf20Sopenharmony_ci	.probe			= p1023_rdb_probe,
1068c2ecf20Sopenharmony_ci	.setup_arch		= mpc85xx_rdb_setup_arch,
1078c2ecf20Sopenharmony_ci	.init_IRQ		= mpc85xx_rdb_pic_init,
1088c2ecf20Sopenharmony_ci	.get_irq		= mpic_get_irq,
1098c2ecf20Sopenharmony_ci	.calibrate_decr		= generic_calibrate_decr,
1108c2ecf20Sopenharmony_ci	.progress		= udbg_progress,
1118c2ecf20Sopenharmony_ci#ifdef CONFIG_PCI
1128c2ecf20Sopenharmony_ci	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
1138c2ecf20Sopenharmony_ci	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
1148c2ecf20Sopenharmony_ci#endif
1158c2ecf20Sopenharmony_ci};
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