18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Common PowerQUICC II code.
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * Author: Scott Wood <scottwood@freescale.com>
68c2ecf20Sopenharmony_ci * Copyright (c) 2007 Freescale Semiconductor
78c2ecf20Sopenharmony_ci *
88c2ecf20Sopenharmony_ci * Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
98c2ecf20Sopenharmony_ci * pq2_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
108c2ecf20Sopenharmony_ci * Copyright (c) 2006 MontaVista Software, Inc.
118c2ecf20Sopenharmony_ci */
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ci#include <linux/kprobes.h>
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci#include <asm/cpm2.h>
168c2ecf20Sopenharmony_ci#include <asm/io.h>
178c2ecf20Sopenharmony_ci#include <asm/pci-bridge.h>
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci#include <platforms/82xx/pq2.h>
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci#define RMR_CSRE 0x00000001
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_civoid __noreturn pq2_restart(char *cmd)
248c2ecf20Sopenharmony_ci{
258c2ecf20Sopenharmony_ci	local_irq_disable();
268c2ecf20Sopenharmony_ci	setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci	/* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
298c2ecf20Sopenharmony_ci	mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
308c2ecf20Sopenharmony_ci	in_8(&cpm2_immr->im_clkrst.res[0]);
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci	panic("Restart failed\n");
338c2ecf20Sopenharmony_ci}
348c2ecf20Sopenharmony_ciNOKPROBE_SYMBOL(pq2_restart)
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ci#ifdef CONFIG_PCI
378c2ecf20Sopenharmony_cistatic int pq2_pci_exclude_device(struct pci_controller *hose,
388c2ecf20Sopenharmony_ci                                  u_char bus, u8 devfn)
398c2ecf20Sopenharmony_ci{
408c2ecf20Sopenharmony_ci	if (bus == 0 && PCI_SLOT(devfn) == 0)
418c2ecf20Sopenharmony_ci		return PCIBIOS_DEVICE_NOT_FOUND;
428c2ecf20Sopenharmony_ci	else
438c2ecf20Sopenharmony_ci		return PCIBIOS_SUCCESSFUL;
448c2ecf20Sopenharmony_ci}
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_cistatic void __init pq2_pci_add_bridge(struct device_node *np)
478c2ecf20Sopenharmony_ci{
488c2ecf20Sopenharmony_ci	struct pci_controller *hose;
498c2ecf20Sopenharmony_ci	struct resource r;
508c2ecf20Sopenharmony_ci
518c2ecf20Sopenharmony_ci	if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b)
528c2ecf20Sopenharmony_ci		goto err;
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci	pci_add_flags(PCI_REASSIGN_ALL_BUS);
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci	hose = pcibios_alloc_controller(np);
578c2ecf20Sopenharmony_ci	if (!hose)
588c2ecf20Sopenharmony_ci		return;
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_ci	hose->dn = np;
618c2ecf20Sopenharmony_ci
628c2ecf20Sopenharmony_ci	setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0);
638c2ecf20Sopenharmony_ci	pci_process_bridge_OF_ranges(hose, np, 1);
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_ci	return;
668c2ecf20Sopenharmony_ci
678c2ecf20Sopenharmony_cierr:
688c2ecf20Sopenharmony_ci	printk(KERN_ERR "No valid PCI reg property in device tree\n");
698c2ecf20Sopenharmony_ci}
708c2ecf20Sopenharmony_ci
718c2ecf20Sopenharmony_civoid __init pq2_init_pci(void)
728c2ecf20Sopenharmony_ci{
738c2ecf20Sopenharmony_ci	struct device_node *np;
748c2ecf20Sopenharmony_ci
758c2ecf20Sopenharmony_ci	ppc_md.pci_exclude_device = pq2_pci_exclude_device;
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_ci	for_each_compatible_node(np, NULL, "fsl,pq2-pci")
788c2ecf20Sopenharmony_ci		pq2_pci_add_bridge(np);
798c2ecf20Sopenharmony_ci}
808c2ecf20Sopenharmony_ci#endif
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