1/* 2 * PCI / PCI-X / PCI-Express support for 4xx parts 3 * 4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. 5 * 6 * Most PCI Express code is coming from Stefan Roese implementation for 7 * arch/ppc in the Denx tree, slightly reworked by me. 8 * 9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 10 * 11 * Some of that comes itself from a previous implementation for 440SPE only 12 * by Roland Dreier: 13 * 14 * Copyright (c) 2005 Cisco Systems. All rights reserved. 15 * Roland Dreier <rolandd@cisco.com> 16 * 17 */ 18 19#undef DEBUG 20 21#include <linux/kernel.h> 22#include <linux/pci.h> 23#include <linux/init.h> 24#include <linux/of.h> 25#include <linux/delay.h> 26#include <linux/slab.h> 27 28#include <asm/io.h> 29#include <asm/pci-bridge.h> 30#include <asm/machdep.h> 31#include <asm/dcr.h> 32#include <asm/dcr-regs.h> 33#include <mm/mmu_decl.h> 34 35#include "pci.h" 36 37static int dma_offset_set; 38 39#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) 40#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) 41 42#define RES_TO_U32_LOW(val) \ 43 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val)) 44#define RES_TO_U32_HIGH(val) \ 45 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0)) 46 47static inline int ppc440spe_revA(void) 48{ 49 /* Catch both 440SPe variants, with and without RAID6 support */ 50 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) 51 return 1; 52 else 53 return 0; 54} 55 56static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev) 57{ 58 struct pci_controller *hose; 59 int i; 60 61 if (dev->devfn != 0 || dev->bus->self != NULL) 62 return; 63 64 hose = pci_bus_to_host(dev->bus); 65 if (hose == NULL) 66 return; 67 68 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") && 69 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") && 70 !of_device_is_compatible(hose->dn, "ibm,plb-pci")) 71 return; 72 73 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") || 74 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) { 75 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM; 76 } 77 78 /* Hide the PCI host BARs from the kernel as their content doesn't 79 * fit well in the resource management 80 */ 81 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 82 dev->resource[i].start = dev->resource[i].end = 0; 83 dev->resource[i].flags = 0; 84 } 85 86 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n", 87 pci_name(dev)); 88} 89DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge); 90 91static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose, 92 void __iomem *reg, 93 struct resource *res) 94{ 95 u64 size; 96 const u32 *ranges; 97 int rlen; 98 int pna = of_n_addr_cells(hose->dn); 99 int np = pna + 5; 100 101 /* Default */ 102 res->start = 0; 103 size = 0x80000000; 104 res->end = size - 1; 105 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 106 107 /* Get dma-ranges property */ 108 ranges = of_get_property(hose->dn, "dma-ranges", &rlen); 109 if (ranges == NULL) 110 goto out; 111 112 /* Walk it */ 113 while ((rlen -= np * 4) >= 0) { 114 u32 pci_space = ranges[0]; 115 u64 pci_addr = of_read_number(ranges + 1, 2); 116 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3); 117 size = of_read_number(ranges + pna + 3, 2); 118 ranges += np; 119 if (cpu_addr == OF_BAD_ADDR || size == 0) 120 continue; 121 122 /* We only care about memory */ 123 if ((pci_space & 0x03000000) != 0x02000000) 124 continue; 125 126 /* We currently only support memory at 0, and pci_addr 127 * within 32 bits space 128 */ 129 if (cpu_addr != 0 || pci_addr > 0xffffffff) { 130 printk(KERN_WARNING "%pOF: Ignored unsupported dma range" 131 " 0x%016llx...0x%016llx -> 0x%016llx\n", 132 hose->dn, 133 pci_addr, pci_addr + size - 1, cpu_addr); 134 continue; 135 } 136 137 /* Check if not prefetchable */ 138 if (!(pci_space & 0x40000000)) 139 res->flags &= ~IORESOURCE_PREFETCH; 140 141 142 /* Use that */ 143 res->start = pci_addr; 144 /* Beware of 32 bits resources */ 145 if (sizeof(resource_size_t) == sizeof(u32) && 146 (pci_addr + size) > 0x100000000ull) 147 res->end = 0xffffffff; 148 else 149 res->end = res->start + size - 1; 150 break; 151 } 152 153 /* We only support one global DMA offset */ 154 if (dma_offset_set && pci_dram_offset != res->start) { 155 printk(KERN_ERR "%pOF: dma-ranges(s) mismatch\n", hose->dn); 156 return -ENXIO; 157 } 158 159 /* Check that we can fit all of memory as we don't support 160 * DMA bounce buffers 161 */ 162 if (size < total_memory) { 163 printk(KERN_ERR "%pOF: dma-ranges too small " 164 "(size=%llx total_memory=%llx)\n", 165 hose->dn, size, (u64)total_memory); 166 return -ENXIO; 167 } 168 169 /* Check we are a power of 2 size and that base is a multiple of size*/ 170 if ((size & (size - 1)) != 0 || 171 (res->start & (size - 1)) != 0) { 172 printk(KERN_ERR "%pOF: dma-ranges unaligned\n", hose->dn); 173 return -ENXIO; 174 } 175 176 /* Check that we are fully contained within 32 bits space if we are not 177 * running on a 460sx or 476fpe which have 64 bit bus addresses. 178 */ 179 if (res->end > 0xffffffff && 180 !(of_device_is_compatible(hose->dn, "ibm,plb-pciex-460sx") 181 || of_device_is_compatible(hose->dn, "ibm,plb-pciex-476fpe"))) { 182 printk(KERN_ERR "%pOF: dma-ranges outside of 32 bits space\n", 183 hose->dn); 184 return -ENXIO; 185 } 186 out: 187 dma_offset_set = 1; 188 pci_dram_offset = res->start; 189 hose->dma_window_base_cur = res->start; 190 hose->dma_window_size = resource_size(res); 191 192 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n", 193 pci_dram_offset); 194 printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n", 195 (unsigned long long)hose->dma_window_base_cur); 196 printk(KERN_INFO "DMA window size 0x%016llx\n", 197 (unsigned long long)hose->dma_window_size); 198 return 0; 199} 200 201/* 202 * 4xx PCI 2.x part 203 */ 204 205static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose, 206 void __iomem *reg, 207 u64 plb_addr, 208 u64 pci_addr, 209 u64 size, 210 unsigned int flags, 211 int index) 212{ 213 u32 ma, pcila, pciha; 214 215 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low 216 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit 217 * address are actually hard wired to a value that appears to depend 218 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx. 219 * 220 * The trick here is we just crop those top bits and ignore them when 221 * programming the chip. That means the device-tree has to be right 222 * for the specific part used (we don't print a warning if it's wrong 223 * but on the other hand, you'll crash quickly enough), but at least 224 * this code should work whatever the hard coded value is 225 */ 226 plb_addr &= 0xffffffffull; 227 228 /* Note: Due to the above hack, the test below doesn't actually test 229 * if you address is above 4G, but it tests that address and 230 * (address + size) are both contained in the same 4G 231 */ 232 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || 233 size < 0x1000 || (plb_addr & (size - 1)) != 0) { 234 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn); 235 return -1; 236 } 237 ma = (0xffffffffu << ilog2(size)) | 1; 238 if (flags & IORESOURCE_PREFETCH) 239 ma |= 2; 240 241 pciha = RES_TO_U32_HIGH(pci_addr); 242 pcila = RES_TO_U32_LOW(pci_addr); 243 244 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index)); 245 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index)); 246 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index)); 247 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index)); 248 249 return 0; 250} 251 252static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose, 253 void __iomem *reg) 254{ 255 int i, j, found_isa_hole = 0; 256 257 /* Setup outbound memory windows */ 258 for (i = j = 0; i < 3; i++) { 259 struct resource *res = &hose->mem_resources[i]; 260 resource_size_t offset = hose->mem_offset[i]; 261 262 /* we only care about memory windows */ 263 if (!(res->flags & IORESOURCE_MEM)) 264 continue; 265 if (j > 2) { 266 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn); 267 break; 268 } 269 270 /* Configure the resource */ 271 if (ppc4xx_setup_one_pci_PMM(hose, reg, 272 res->start, 273 res->start - offset, 274 resource_size(res), 275 res->flags, 276 j) == 0) { 277 j++; 278 279 /* If the resource PCI address is 0 then we have our 280 * ISA memory hole 281 */ 282 if (res->start == offset) 283 found_isa_hole = 1; 284 } 285 } 286 287 /* Handle ISA memory hole if not already covered */ 288 if (j <= 2 && !found_isa_hole && hose->isa_mem_size) 289 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, 290 hose->isa_mem_size, 0, j) == 0) 291 printk(KERN_INFO "%pOF: Legacy ISA memory support enabled\n", 292 hose->dn); 293} 294 295static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose, 296 void __iomem *reg, 297 const struct resource *res) 298{ 299 resource_size_t size = resource_size(res); 300 u32 sa; 301 302 /* Calculate window size */ 303 sa = (0xffffffffu << ilog2(size)) | 1; 304 sa |= 0x1; 305 306 /* RAM is always at 0 local for now */ 307 writel(0, reg + PCIL0_PTM1LA); 308 writel(sa, reg + PCIL0_PTM1MS); 309 310 /* Map on PCI side */ 311 early_write_config_dword(hose, hose->first_busno, 0, 312 PCI_BASE_ADDRESS_1, res->start); 313 early_write_config_dword(hose, hose->first_busno, 0, 314 PCI_BASE_ADDRESS_2, 0x00000000); 315 early_write_config_word(hose, hose->first_busno, 0, 316 PCI_COMMAND, 0x0006); 317} 318 319static void __init ppc4xx_probe_pci_bridge(struct device_node *np) 320{ 321 /* NYI */ 322 struct resource rsrc_cfg; 323 struct resource rsrc_reg; 324 struct resource dma_window; 325 struct pci_controller *hose = NULL; 326 void __iomem *reg = NULL; 327 const int *bus_range; 328 int primary = 0; 329 330 /* Check if device is enabled */ 331 if (!of_device_is_available(np)) { 332 printk(KERN_INFO "%pOF: Port disabled via device-tree\n", np); 333 return; 334 } 335 336 /* Fetch config space registers address */ 337 if (of_address_to_resource(np, 0, &rsrc_cfg)) { 338 printk(KERN_ERR "%pOF: Can't get PCI config register base !", 339 np); 340 return; 341 } 342 /* Fetch host bridge internal registers address */ 343 if (of_address_to_resource(np, 3, &rsrc_reg)) { 344 printk(KERN_ERR "%pOF: Can't get PCI internal register base !", 345 np); 346 return; 347 } 348 349 /* Check if primary bridge */ 350 if (of_get_property(np, "primary", NULL)) 351 primary = 1; 352 353 /* Get bus range if any */ 354 bus_range = of_get_property(np, "bus-range", NULL); 355 356 /* Map registers */ 357 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg)); 358 if (reg == NULL) { 359 printk(KERN_ERR "%pOF: Can't map registers !", np); 360 goto fail; 361 } 362 363 /* Allocate the host controller data structure */ 364 hose = pcibios_alloc_controller(np); 365 if (!hose) 366 goto fail; 367 368 hose->first_busno = bus_range ? bus_range[0] : 0x0; 369 hose->last_busno = bus_range ? bus_range[1] : 0xff; 370 371 /* Setup config space */ 372 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0); 373 374 /* Disable all windows */ 375 writel(0, reg + PCIL0_PMM0MA); 376 writel(0, reg + PCIL0_PMM1MA); 377 writel(0, reg + PCIL0_PMM2MA); 378 writel(0, reg + PCIL0_PTM1MS); 379 writel(0, reg + PCIL0_PTM2MS); 380 381 /* Parse outbound mapping resources */ 382 pci_process_bridge_OF_ranges(hose, np, primary); 383 384 /* Parse inbound mapping resources */ 385 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) 386 goto fail; 387 388 /* Configure outbound ranges POMs */ 389 ppc4xx_configure_pci_PMMs(hose, reg); 390 391 /* Configure inbound ranges PIMs */ 392 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window); 393 394 /* We don't need the registers anymore */ 395 iounmap(reg); 396 return; 397 398 fail: 399 if (hose) 400 pcibios_free_controller(hose); 401 if (reg) 402 iounmap(reg); 403} 404 405/* 406 * 4xx PCI-X part 407 */ 408 409static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose, 410 void __iomem *reg, 411 u64 plb_addr, 412 u64 pci_addr, 413 u64 size, 414 unsigned int flags, 415 int index) 416{ 417 u32 lah, lal, pciah, pcial, sa; 418 419 if (!is_power_of_2(size) || size < 0x1000 || 420 (plb_addr & (size - 1)) != 0) { 421 printk(KERN_WARNING "%pOF: Resource out of range\n", 422 hose->dn); 423 return -1; 424 } 425 426 /* Calculate register values */ 427 lah = RES_TO_U32_HIGH(plb_addr); 428 lal = RES_TO_U32_LOW(plb_addr); 429 pciah = RES_TO_U32_HIGH(pci_addr); 430 pcial = RES_TO_U32_LOW(pci_addr); 431 sa = (0xffffffffu << ilog2(size)) | 0x1; 432 433 /* Program register values */ 434 if (index == 0) { 435 writel(lah, reg + PCIX0_POM0LAH); 436 writel(lal, reg + PCIX0_POM0LAL); 437 writel(pciah, reg + PCIX0_POM0PCIAH); 438 writel(pcial, reg + PCIX0_POM0PCIAL); 439 writel(sa, reg + PCIX0_POM0SA); 440 } else { 441 writel(lah, reg + PCIX0_POM1LAH); 442 writel(lal, reg + PCIX0_POM1LAL); 443 writel(pciah, reg + PCIX0_POM1PCIAH); 444 writel(pcial, reg + PCIX0_POM1PCIAL); 445 writel(sa, reg + PCIX0_POM1SA); 446 } 447 448 return 0; 449} 450 451static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose, 452 void __iomem *reg) 453{ 454 int i, j, found_isa_hole = 0; 455 456 /* Setup outbound memory windows */ 457 for (i = j = 0; i < 3; i++) { 458 struct resource *res = &hose->mem_resources[i]; 459 resource_size_t offset = hose->mem_offset[i]; 460 461 /* we only care about memory windows */ 462 if (!(res->flags & IORESOURCE_MEM)) 463 continue; 464 if (j > 1) { 465 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn); 466 break; 467 } 468 469 /* Configure the resource */ 470 if (ppc4xx_setup_one_pcix_POM(hose, reg, 471 res->start, 472 res->start - offset, 473 resource_size(res), 474 res->flags, 475 j) == 0) { 476 j++; 477 478 /* If the resource PCI address is 0 then we have our 479 * ISA memory hole 480 */ 481 if (res->start == offset) 482 found_isa_hole = 1; 483 } 484 } 485 486 /* Handle ISA memory hole if not already covered */ 487 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) 488 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, 489 hose->isa_mem_size, 0, j) == 0) 490 printk(KERN_INFO "%pOF: Legacy ISA memory support enabled\n", 491 hose->dn); 492} 493 494static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose, 495 void __iomem *reg, 496 const struct resource *res, 497 int big_pim, 498 int enable_msi_hole) 499{ 500 resource_size_t size = resource_size(res); 501 u32 sa; 502 503 /* RAM is always at 0 */ 504 writel(0x00000000, reg + PCIX0_PIM0LAH); 505 writel(0x00000000, reg + PCIX0_PIM0LAL); 506 507 /* Calculate window size */ 508 sa = (0xffffffffu << ilog2(size)) | 1; 509 sa |= 0x1; 510 if (res->flags & IORESOURCE_PREFETCH) 511 sa |= 0x2; 512 if (enable_msi_hole) 513 sa |= 0x4; 514 writel(sa, reg + PCIX0_PIM0SA); 515 if (big_pim) 516 writel(0xffffffff, reg + PCIX0_PIM0SAH); 517 518 /* Map on PCI side */ 519 writel(0x00000000, reg + PCIX0_BAR0H); 520 writel(res->start, reg + PCIX0_BAR0L); 521 writew(0x0006, reg + PCIX0_COMMAND); 522} 523 524static void __init ppc4xx_probe_pcix_bridge(struct device_node *np) 525{ 526 struct resource rsrc_cfg; 527 struct resource rsrc_reg; 528 struct resource dma_window; 529 struct pci_controller *hose = NULL; 530 void __iomem *reg = NULL; 531 const int *bus_range; 532 int big_pim = 0, msi = 0, primary = 0; 533 534 /* Fetch config space registers address */ 535 if (of_address_to_resource(np, 0, &rsrc_cfg)) { 536 printk(KERN_ERR "%pOF: Can't get PCI-X config register base !", 537 np); 538 return; 539 } 540 /* Fetch host bridge internal registers address */ 541 if (of_address_to_resource(np, 3, &rsrc_reg)) { 542 printk(KERN_ERR "%pOF: Can't get PCI-X internal register base !", 543 np); 544 return; 545 } 546 547 /* Check if it supports large PIMs (440GX) */ 548 if (of_get_property(np, "large-inbound-windows", NULL)) 549 big_pim = 1; 550 551 /* Check if we should enable MSIs inbound hole */ 552 if (of_get_property(np, "enable-msi-hole", NULL)) 553 msi = 1; 554 555 /* Check if primary bridge */ 556 if (of_get_property(np, "primary", NULL)) 557 primary = 1; 558 559 /* Get bus range if any */ 560 bus_range = of_get_property(np, "bus-range", NULL); 561 562 /* Map registers */ 563 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg)); 564 if (reg == NULL) { 565 printk(KERN_ERR "%pOF: Can't map registers !", np); 566 goto fail; 567 } 568 569 /* Allocate the host controller data structure */ 570 hose = pcibios_alloc_controller(np); 571 if (!hose) 572 goto fail; 573 574 hose->first_busno = bus_range ? bus_range[0] : 0x0; 575 hose->last_busno = bus_range ? bus_range[1] : 0xff; 576 577 /* Setup config space */ 578 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 579 PPC_INDIRECT_TYPE_SET_CFG_TYPE); 580 581 /* Disable all windows */ 582 writel(0, reg + PCIX0_POM0SA); 583 writel(0, reg + PCIX0_POM1SA); 584 writel(0, reg + PCIX0_POM2SA); 585 writel(0, reg + PCIX0_PIM0SA); 586 writel(0, reg + PCIX0_PIM1SA); 587 writel(0, reg + PCIX0_PIM2SA); 588 if (big_pim) { 589 writel(0, reg + PCIX0_PIM0SAH); 590 writel(0, reg + PCIX0_PIM2SAH); 591 } 592 593 /* Parse outbound mapping resources */ 594 pci_process_bridge_OF_ranges(hose, np, primary); 595 596 /* Parse inbound mapping resources */ 597 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) 598 goto fail; 599 600 /* Configure outbound ranges POMs */ 601 ppc4xx_configure_pcix_POMs(hose, reg); 602 603 /* Configure inbound ranges PIMs */ 604 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi); 605 606 /* We don't need the registers anymore */ 607 iounmap(reg); 608 return; 609 610 fail: 611 if (hose) 612 pcibios_free_controller(hose); 613 if (reg) 614 iounmap(reg); 615} 616 617#ifdef CONFIG_PPC4xx_PCI_EXPRESS 618 619/* 620 * 4xx PCI-Express part 621 * 622 * We support 3 parts currently based on the compatible property: 623 * 624 * ibm,plb-pciex-440spe 625 * ibm,plb-pciex-405ex 626 * ibm,plb-pciex-460ex 627 * 628 * Anything else will be rejected for now as they are all subtly 629 * different unfortunately. 630 * 631 */ 632 633#define MAX_PCIE_BUS_MAPPED 0x40 634 635struct ppc4xx_pciex_port 636{ 637 struct pci_controller *hose; 638 struct device_node *node; 639 unsigned int index; 640 int endpoint; 641 int link; 642 int has_ibpre; 643 unsigned int sdr_base; 644 dcr_host_t dcrs; 645 struct resource cfg_space; 646 struct resource utl_regs; 647 void __iomem *utl_base; 648}; 649 650static struct ppc4xx_pciex_port *ppc4xx_pciex_ports; 651static unsigned int ppc4xx_pciex_port_count; 652 653struct ppc4xx_pciex_hwops 654{ 655 bool want_sdr; 656 int (*core_init)(struct device_node *np); 657 int (*port_init_hw)(struct ppc4xx_pciex_port *port); 658 int (*setup_utl)(struct ppc4xx_pciex_port *port); 659 void (*check_link)(struct ppc4xx_pciex_port *port); 660}; 661 662static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops; 663 664static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port, 665 unsigned int sdr_offset, 666 unsigned int mask, 667 unsigned int value, 668 int timeout_ms) 669{ 670 u32 val; 671 672 while(timeout_ms--) { 673 val = mfdcri(SDR0, port->sdr_base + sdr_offset); 674 if ((val & mask) == value) { 675 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n", 676 port->index, sdr_offset, timeout_ms, val); 677 return 0; 678 } 679 msleep(1); 680 } 681 return -1; 682} 683 684static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port) 685{ 686 /* Wait for reset to complete */ 687 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) { 688 printk(KERN_WARNING "PCIE%d: PGRST failed\n", 689 port->index); 690 return -1; 691 } 692 return 0; 693} 694 695 696static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port) 697{ 698 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); 699 700 /* Check for card presence detect if supported, if not, just wait for 701 * link unconditionally. 702 * 703 * note that we don't fail if there is no link, we just filter out 704 * config space accesses. That way, it will be easier to implement 705 * hotplug later on. 706 */ 707 if (!port->has_ibpre || 708 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, 709 1 << 28, 1 << 28, 100)) { 710 printk(KERN_INFO 711 "PCIE%d: Device detected, waiting for link...\n", 712 port->index); 713 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, 714 0x1000, 0x1000, 2000)) 715 printk(KERN_WARNING 716 "PCIE%d: Link up failed\n", port->index); 717 else { 718 printk(KERN_INFO 719 "PCIE%d: link is up !\n", port->index); 720 port->link = 1; 721 } 722 } else 723 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index); 724} 725 726#ifdef CONFIG_44x 727 728/* Check various reset bits of the 440SPe PCIe core */ 729static int __init ppc440spe_pciex_check_reset(struct device_node *np) 730{ 731 u32 valPE0, valPE1, valPE2; 732 int err = 0; 733 734 /* SDR0_PEGPLLLCT1 reset */ 735 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) { 736 /* 737 * the PCIe core was probably already initialised 738 * by firmware - let's re-reset RCSSET regs 739 * 740 * -- Shouldn't we also re-reset the whole thing ? -- BenH 741 */ 742 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n"); 743 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); 744 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); 745 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); 746 } 747 748 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET); 749 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET); 750 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET); 751 752 /* SDR0_PExRCSSET rstgu */ 753 if (!(valPE0 & 0x01000000) || 754 !(valPE1 & 0x01000000) || 755 !(valPE2 & 0x01000000)) { 756 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n"); 757 err = -1; 758 } 759 760 /* SDR0_PExRCSSET rstdl */ 761 if (!(valPE0 & 0x00010000) || 762 !(valPE1 & 0x00010000) || 763 !(valPE2 & 0x00010000)) { 764 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n"); 765 err = -1; 766 } 767 768 /* SDR0_PExRCSSET rstpyn */ 769 if ((valPE0 & 0x00001000) || 770 (valPE1 & 0x00001000) || 771 (valPE2 & 0x00001000)) { 772 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n"); 773 err = -1; 774 } 775 776 /* SDR0_PExRCSSET hldplb */ 777 if ((valPE0 & 0x10000000) || 778 (valPE1 & 0x10000000) || 779 (valPE2 & 0x10000000)) { 780 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n"); 781 err = -1; 782 } 783 784 /* SDR0_PExRCSSET rdy */ 785 if ((valPE0 & 0x00100000) || 786 (valPE1 & 0x00100000) || 787 (valPE2 & 0x00100000)) { 788 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n"); 789 err = -1; 790 } 791 792 /* SDR0_PExRCSSET shutdown */ 793 if ((valPE0 & 0x00000100) || 794 (valPE1 & 0x00000100) || 795 (valPE2 & 0x00000100)) { 796 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n"); 797 err = -1; 798 } 799 800 return err; 801} 802 803/* Global PCIe core initializations for 440SPe core */ 804static int __init ppc440spe_pciex_core_init(struct device_node *np) 805{ 806 int time_out = 20; 807 808 /* Set PLL clock receiver to LVPECL */ 809 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); 810 811 /* Shouldn't we do all the calibration stuff etc... here ? */ 812 if (ppc440spe_pciex_check_reset(np)) 813 return -ENXIO; 814 815 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) { 816 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration " 817 "failed (0x%08x)\n", 818 mfdcri(SDR0, PESDR0_PLLLCT2)); 819 return -1; 820 } 821 822 /* De-assert reset of PCIe PLL, wait for lock */ 823 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); 824 udelay(3); 825 826 while (time_out) { 827 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) { 828 time_out--; 829 udelay(1); 830 } else 831 break; 832 } 833 if (!time_out) { 834 printk(KERN_INFO "PCIE: VCO output not locked\n"); 835 return -1; 836 } 837 838 pr_debug("PCIE initialization OK\n"); 839 840 return 3; 841} 842 843static int __init ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 844{ 845 u32 val = 1 << 24; 846 847 if (port->endpoint) 848 val = PTYPE_LEGACY_ENDPOINT << 20; 849 else 850 val = PTYPE_ROOT_PORT << 20; 851 852 if (port->index == 0) 853 val |= LNKW_X8 << 12; 854 else 855 val |= LNKW_X4 << 12; 856 857 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); 858 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); 859 if (ppc440spe_revA()) 860 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); 861 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); 862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); 863 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); 864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); 865 if (port->index == 0) { 866 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, 867 0x35000000); 868 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, 869 0x35000000); 870 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, 871 0x35000000); 872 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, 873 0x35000000); 874 } 875 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 876 (1 << 24) | (1 << 16), 1 << 12); 877 878 return ppc4xx_pciex_port_reset_sdr(port); 879} 880 881static int __init ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 882{ 883 return ppc440spe_pciex_init_port_hw(port); 884} 885 886static int __init ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 887{ 888 int rc = ppc440spe_pciex_init_port_hw(port); 889 890 port->has_ibpre = 1; 891 892 return rc; 893} 894 895static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port) 896{ 897 /* XXX Check what that value means... I hate magic */ 898 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); 899 900 /* 901 * Set buffer allocations and then assert VRB and TXE. 902 */ 903 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); 904 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); 905 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); 906 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); 907 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); 908 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); 909 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); 910 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); 911 912 return 0; 913} 914 915static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port) 916{ 917 /* Report CRS to the operating system */ 918 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); 919 920 return 0; 921} 922 923static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata = 924{ 925 .want_sdr = true, 926 .core_init = ppc440spe_pciex_core_init, 927 .port_init_hw = ppc440speA_pciex_init_port_hw, 928 .setup_utl = ppc440speA_pciex_init_utl, 929 .check_link = ppc4xx_pciex_check_link_sdr, 930}; 931 932static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = 933{ 934 .want_sdr = true, 935 .core_init = ppc440spe_pciex_core_init, 936 .port_init_hw = ppc440speB_pciex_init_port_hw, 937 .setup_utl = ppc440speB_pciex_init_utl, 938 .check_link = ppc4xx_pciex_check_link_sdr, 939}; 940 941static int __init ppc460ex_pciex_core_init(struct device_node *np) 942{ 943 /* Nothing to do, return 2 ports */ 944 return 2; 945} 946 947static int __init ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 948{ 949 u32 val; 950 u32 utlset1; 951 952 if (port->endpoint) 953 val = PTYPE_LEGACY_ENDPOINT << 20; 954 else 955 val = PTYPE_ROOT_PORT << 20; 956 957 if (port->index == 0) { 958 val |= LNKW_X1 << 12; 959 utlset1 = 0x20000000; 960 } else { 961 val |= LNKW_X4 << 12; 962 utlset1 = 0x20101101; 963 } 964 965 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); 966 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); 967 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); 968 969 switch (port->index) { 970 case 0: 971 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); 972 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); 973 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); 974 975 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); 976 break; 977 978 case 1: 979 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230); 980 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); 981 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); 982 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); 983 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130); 984 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130); 985 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130); 986 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130); 987 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); 988 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); 989 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); 990 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006); 991 992 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000); 993 break; 994 } 995 996 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 997 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 998 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); 999 1000 /* Poll for PHY reset */ 1001 /* XXX FIXME add timeout */ 1002 switch (port->index) { 1003 case 0: 1004 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1)) 1005 udelay(10); 1006 break; 1007 case 1: 1008 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1)) 1009 udelay(10); 1010 break; 1011 } 1012 1013 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 1014 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & 1015 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | 1016 PESDRx_RCSSET_RSTPYN); 1017 1018 port->has_ibpre = 1; 1019 1020 return ppc4xx_pciex_port_reset_sdr(port); 1021} 1022 1023static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port) 1024{ 1025 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); 1026 1027 /* 1028 * Set buffer allocations and then assert VRB and TXE. 1029 */ 1030 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); 1031 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); 1032 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); 1033 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); 1034 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); 1035 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); 1036 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); 1037 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); 1038 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); 1039 1040 return 0; 1041} 1042 1043static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata = 1044{ 1045 .want_sdr = true, 1046 .core_init = ppc460ex_pciex_core_init, 1047 .port_init_hw = ppc460ex_pciex_init_port_hw, 1048 .setup_utl = ppc460ex_pciex_init_utl, 1049 .check_link = ppc4xx_pciex_check_link_sdr, 1050}; 1051 1052static int __init apm821xx_pciex_core_init(struct device_node *np) 1053{ 1054 /* Return the number of pcie port */ 1055 return 1; 1056} 1057 1058static int __init apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 1059{ 1060 u32 val; 1061 1062 /* 1063 * Do a software reset on PCIe ports. 1064 * This code is to fix the issue that pci drivers doesn't re-assign 1065 * bus number for PCIE devices after Uboot 1066 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000 1067 * PT quad port, SAS LSI 1064E) 1068 */ 1069 1070 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); 1071 mdelay(10); 1072 1073 if (port->endpoint) 1074 val = PTYPE_LEGACY_ENDPOINT << 20; 1075 else 1076 val = PTYPE_ROOT_PORT << 20; 1077 1078 val |= LNKW_X1 << 12; 1079 1080 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); 1081 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); 1082 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); 1083 1084 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); 1085 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); 1086 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); 1087 1088 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); 1089 mdelay(50); 1090 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); 1091 1092 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 1093 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1094 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); 1095 1096 /* Poll for PHY reset */ 1097 val = PESDR0_460EX_RSTSTA - port->sdr_base; 1098 if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) { 1099 printk(KERN_WARNING "%s: PCIE: Can't reset PHY\n", __func__); 1100 return -EBUSY; 1101 } else { 1102 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 1103 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & 1104 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | 1105 PESDRx_RCSSET_RSTPYN); 1106 1107 port->has_ibpre = 1; 1108 return 0; 1109 } 1110} 1111 1112static struct ppc4xx_pciex_hwops apm821xx_pcie_hwops __initdata = { 1113 .want_sdr = true, 1114 .core_init = apm821xx_pciex_core_init, 1115 .port_init_hw = apm821xx_pciex_init_port_hw, 1116 .setup_utl = ppc460ex_pciex_init_utl, 1117 .check_link = ppc4xx_pciex_check_link_sdr, 1118}; 1119 1120static int __init ppc460sx_pciex_core_init(struct device_node *np) 1121{ 1122 /* HSS drive amplitude */ 1123 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211); 1124 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211); 1125 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211); 1126 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211); 1127 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211); 1128 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211); 1129 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211); 1130 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211); 1131 1132 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211); 1133 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211); 1134 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211); 1135 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211); 1136 1137 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211); 1138 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211); 1139 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211); 1140 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211); 1141 1142 /* HSS TX pre-emphasis */ 1143 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987); 1144 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987); 1145 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987); 1146 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987); 1147 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987); 1148 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987); 1149 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987); 1150 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987); 1151 1152 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987); 1153 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987); 1154 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987); 1155 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987); 1156 1157 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987); 1158 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987); 1159 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987); 1160 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987); 1161 1162 /* HSS TX calibration control */ 1163 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222); 1164 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000); 1165 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000); 1166 1167 /* HSS TX slew control */ 1168 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF); 1169 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000); 1170 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000); 1171 1172 /* Set HSS PRBS enabled */ 1173 mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130); 1174 mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130); 1175 1176 udelay(100); 1177 1178 /* De-assert PLLRESET */ 1179 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0); 1180 1181 /* Reset DL, UTL, GPL before configuration */ 1182 mtdcri(SDR0, PESDR0_460SX_RCSSET, 1183 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); 1184 mtdcri(SDR0, PESDR1_460SX_RCSSET, 1185 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); 1186 mtdcri(SDR0, PESDR2_460SX_RCSSET, 1187 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); 1188 1189 udelay(100); 1190 1191 /* 1192 * If bifurcation is not enabled, u-boot would have disabled the 1193 * third PCIe port 1194 */ 1195 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) == 1196 0x00000001)) { 1197 printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n"); 1198 printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n"); 1199 return 3; 1200 } 1201 1202 printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n"); 1203 return 2; 1204} 1205 1206static int __init ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 1207{ 1208 1209 if (port->endpoint) 1210 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, 1211 0x01000000, 0); 1212 else 1213 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, 1214 0, 0x01000000); 1215 1216 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 1217 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL), 1218 PESDRx_RCSSET_RSTPYN); 1219 1220 port->has_ibpre = 1; 1221 1222 return ppc4xx_pciex_port_reset_sdr(port); 1223} 1224 1225static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port) 1226{ 1227 /* Max 128 Bytes */ 1228 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); 1229 /* Assert VRB and TXE - per datasheet turn off addr validation */ 1230 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000); 1231 return 0; 1232} 1233 1234static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port) 1235{ 1236 void __iomem *mbase; 1237 int attempt = 50; 1238 1239 port->link = 0; 1240 1241 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); 1242 if (mbase == NULL) { 1243 printk(KERN_ERR "%pOF: Can't map internal config space !", 1244 port->node); 1245 return; 1246 } 1247 1248 while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA) 1249 & PECFG_460SX_DLLSTA_LINKUP))) { 1250 attempt--; 1251 mdelay(10); 1252 } 1253 if (attempt) 1254 port->link = 1; 1255 iounmap(mbase); 1256} 1257 1258static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = { 1259 .want_sdr = true, 1260 .core_init = ppc460sx_pciex_core_init, 1261 .port_init_hw = ppc460sx_pciex_init_port_hw, 1262 .setup_utl = ppc460sx_pciex_init_utl, 1263 .check_link = ppc460sx_pciex_check_link, 1264}; 1265 1266#endif /* CONFIG_44x */ 1267 1268#ifdef CONFIG_40x 1269 1270static int __init ppc405ex_pciex_core_init(struct device_node *np) 1271{ 1272 /* Nothing to do, return 2 ports */ 1273 return 2; 1274} 1275 1276static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port) 1277{ 1278 /* Assert the PE0_PHY reset */ 1279 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); 1280 msleep(1); 1281 1282 /* deassert the PE0_hotreset */ 1283 if (port->endpoint) 1284 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); 1285 else 1286 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); 1287 1288 /* poll for phy !reset */ 1289 /* XXX FIXME add timeout */ 1290 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000)) 1291 ; 1292 1293 /* deassert the PE0_gpl_utl_reset */ 1294 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); 1295} 1296 1297static int __init ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 1298{ 1299 u32 val; 1300 1301 if (port->endpoint) 1302 val = PTYPE_LEGACY_ENDPOINT; 1303 else 1304 val = PTYPE_ROOT_PORT; 1305 1306 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, 1307 1 << 24 | val << 20 | LNKW_X1 << 12); 1308 1309 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); 1310 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); 1311 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); 1312 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); 1313 1314 /* 1315 * Only reset the PHY when no link is currently established. 1316 * This is for the Atheros PCIe board which has problems to establish 1317 * the link (again) after this PHY reset. All other currently tested 1318 * PCIe boards don't show this problem. 1319 * This has to be re-tested and fixed in a later release! 1320 */ 1321 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); 1322 if (!(val & 0x00001000)) 1323 ppc405ex_pcie_phy_reset(port); 1324 1325 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ 1326 1327 port->has_ibpre = 1; 1328 1329 return ppc4xx_pciex_port_reset_sdr(port); 1330} 1331 1332static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port) 1333{ 1334 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); 1335 1336 /* 1337 * Set buffer allocations and then assert VRB and TXE. 1338 */ 1339 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000); 1340 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); 1341 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); 1342 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000); 1343 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); 1344 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); 1345 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); 1346 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); 1347 1348 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); 1349 1350 return 0; 1351} 1352 1353static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata = 1354{ 1355 .want_sdr = true, 1356 .core_init = ppc405ex_pciex_core_init, 1357 .port_init_hw = ppc405ex_pciex_init_port_hw, 1358 .setup_utl = ppc405ex_pciex_init_utl, 1359 .check_link = ppc4xx_pciex_check_link_sdr, 1360}; 1361 1362#endif /* CONFIG_40x */ 1363 1364#ifdef CONFIG_476FPE 1365static int __init ppc_476fpe_pciex_core_init(struct device_node *np) 1366{ 1367 return 4; 1368} 1369 1370static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port) 1371{ 1372 u32 timeout_ms = 20; 1373 u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT); 1374 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000, 1375 0x1000); 1376 1377 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); 1378 1379 if (mbase == NULL) { 1380 printk(KERN_WARNING "PCIE%d: failed to get cfg space\n", 1381 port->index); 1382 return; 1383 } 1384 1385 while (timeout_ms--) { 1386 val = in_le32(mbase + PECFG_TLDLP); 1387 1388 if ((val & mask) == mask) 1389 break; 1390 msleep(10); 1391 } 1392 1393 if (val & PECFG_TLDLP_PRESENT) { 1394 printk(KERN_INFO "PCIE%d: link is up !\n", port->index); 1395 port->link = 1; 1396 } else 1397 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index); 1398 1399 iounmap(mbase); 1400} 1401 1402static struct ppc4xx_pciex_hwops ppc_476fpe_pcie_hwops __initdata = 1403{ 1404 .core_init = ppc_476fpe_pciex_core_init, 1405 .check_link = ppc_476fpe_pciex_check_link, 1406}; 1407#endif /* CONFIG_476FPE */ 1408 1409/* Check that the core has been initied and if not, do it */ 1410static int __init ppc4xx_pciex_check_core_init(struct device_node *np) 1411{ 1412 static int core_init; 1413 int count = -ENODEV; 1414 1415 if (core_init++) 1416 return 0; 1417 1418#ifdef CONFIG_44x 1419 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) { 1420 if (ppc440spe_revA()) 1421 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops; 1422 else 1423 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops; 1424 } 1425 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) 1426 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops; 1427 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx")) 1428 ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops; 1429 if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx")) 1430 ppc4xx_pciex_hwops = &apm821xx_pcie_hwops; 1431#endif /* CONFIG_44x */ 1432#ifdef CONFIG_40x 1433 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) 1434 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops; 1435#endif 1436#ifdef CONFIG_476FPE 1437 if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe") 1438 || of_device_is_compatible(np, "ibm,plb-pciex-476gtr")) 1439 ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops; 1440#endif 1441 if (ppc4xx_pciex_hwops == NULL) { 1442 printk(KERN_WARNING "PCIE: unknown host type %pOF\n", np); 1443 return -ENODEV; 1444 } 1445 1446 count = ppc4xx_pciex_hwops->core_init(np); 1447 if (count > 0) { 1448 ppc4xx_pciex_ports = 1449 kcalloc(count, sizeof(struct ppc4xx_pciex_port), 1450 GFP_KERNEL); 1451 if (ppc4xx_pciex_ports) { 1452 ppc4xx_pciex_port_count = count; 1453 return 0; 1454 } 1455 printk(KERN_WARNING "PCIE: failed to allocate ports array\n"); 1456 return -ENOMEM; 1457 } 1458 return -ENODEV; 1459} 1460 1461static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port) 1462{ 1463 /* We map PCI Express configuration based on the reg property */ 1464 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, 1465 RES_TO_U32_HIGH(port->cfg_space.start)); 1466 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, 1467 RES_TO_U32_LOW(port->cfg_space.start)); 1468 1469 /* XXX FIXME: Use size from reg property. For now, map 512M */ 1470 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); 1471 1472 /* We map UTL registers based on the reg property */ 1473 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, 1474 RES_TO_U32_HIGH(port->utl_regs.start)); 1475 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, 1476 RES_TO_U32_LOW(port->utl_regs.start)); 1477 1478 /* XXX FIXME: Use size from reg property */ 1479 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); 1480 1481 /* Disable all other outbound windows */ 1482 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); 1483 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); 1484 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); 1485 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); 1486} 1487 1488static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) 1489{ 1490 int rc = 0; 1491 1492 /* Init HW */ 1493 if (ppc4xx_pciex_hwops->port_init_hw) 1494 rc = ppc4xx_pciex_hwops->port_init_hw(port); 1495 if (rc != 0) 1496 return rc; 1497 1498 /* 1499 * Initialize mapping: disable all regions and configure 1500 * CFG and REG regions based on resources in the device tree 1501 */ 1502 ppc4xx_pciex_port_init_mapping(port); 1503 1504 if (ppc4xx_pciex_hwops->check_link) 1505 ppc4xx_pciex_hwops->check_link(port); 1506 1507 /* 1508 * Map UTL 1509 */ 1510 port->utl_base = ioremap(port->utl_regs.start, 0x100); 1511 BUG_ON(port->utl_base == NULL); 1512 1513 /* 1514 * Setup UTL registers --BenH. 1515 */ 1516 if (ppc4xx_pciex_hwops->setup_utl) 1517 ppc4xx_pciex_hwops->setup_utl(port); 1518 1519 /* 1520 * Check for VC0 active or PLL Locked and assert RDY. 1521 */ 1522 if (port->sdr_base) { 1523 if (of_device_is_compatible(port->node, 1524 "ibm,plb-pciex-460sx")){ 1525 if (port->link && ppc4xx_pciex_wait_on_sdr(port, 1526 PESDRn_RCSSTS, 1527 1 << 12, 1 << 12, 5000)) { 1528 printk(KERN_INFO "PCIE%d: PLL not locked\n", 1529 port->index); 1530 port->link = 0; 1531 } 1532 } else if (port->link && 1533 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1534 1 << 16, 1 << 16, 5000)) { 1535 printk(KERN_INFO "PCIE%d: VC0 not active\n", 1536 port->index); 1537 port->link = 0; 1538 } 1539 1540 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); 1541 } 1542 1543 msleep(100); 1544 1545 return 0; 1546} 1547 1548static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port, 1549 struct pci_bus *bus, 1550 unsigned int devfn) 1551{ 1552 static int message; 1553 1554 /* Endpoint can not generate upstream(remote) config cycles */ 1555 if (port->endpoint && bus->number != port->hose->first_busno) 1556 return PCIBIOS_DEVICE_NOT_FOUND; 1557 1558 /* Check we are within the mapped range */ 1559 if (bus->number > port->hose->last_busno) { 1560 if (!message) { 1561 printk(KERN_WARNING "Warning! Probing bus %u" 1562 " out of range !\n", bus->number); 1563 message++; 1564 } 1565 return PCIBIOS_DEVICE_NOT_FOUND; 1566 } 1567 1568 /* The root complex has only one device / function */ 1569 if (bus->number == port->hose->first_busno && devfn != 0) 1570 return PCIBIOS_DEVICE_NOT_FOUND; 1571 1572 /* The other side of the RC has only one device as well */ 1573 if (bus->number == (port->hose->first_busno + 1) && 1574 PCI_SLOT(devfn) != 0) 1575 return PCIBIOS_DEVICE_NOT_FOUND; 1576 1577 /* Check if we have a link */ 1578 if ((bus->number != port->hose->first_busno) && !port->link) 1579 return PCIBIOS_DEVICE_NOT_FOUND; 1580 1581 return 0; 1582} 1583 1584static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port, 1585 struct pci_bus *bus, 1586 unsigned int devfn) 1587{ 1588 int relbus; 1589 1590 /* Remove the casts when we finally remove the stupid volatile 1591 * in struct pci_controller 1592 */ 1593 if (bus->number == port->hose->first_busno) 1594 return (void __iomem *)port->hose->cfg_addr; 1595 1596 relbus = bus->number - (port->hose->first_busno + 1); 1597 return (void __iomem *)port->hose->cfg_data + 1598 ((relbus << 20) | (devfn << 12)); 1599} 1600 1601static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, 1602 int offset, int len, u32 *val) 1603{ 1604 struct pci_controller *hose = pci_bus_to_host(bus); 1605 struct ppc4xx_pciex_port *port = 1606 &ppc4xx_pciex_ports[hose->indirect_type]; 1607 void __iomem *addr; 1608 u32 gpl_cfg; 1609 1610 BUG_ON(hose != port->hose); 1611 1612 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) 1613 return PCIBIOS_DEVICE_NOT_FOUND; 1614 1615 addr = ppc4xx_pciex_get_config_base(port, bus, devfn); 1616 1617 /* 1618 * Reading from configuration space of non-existing device can 1619 * generate transaction errors. For the read duration we suppress 1620 * assertion of machine check exceptions to avoid those. 1621 */ 1622 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); 1623 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); 1624 1625 /* Make sure no CRS is recorded */ 1626 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); 1627 1628 switch (len) { 1629 case 1: 1630 *val = in_8((u8 *)(addr + offset)); 1631 break; 1632 case 2: 1633 *val = in_le16((u16 *)(addr + offset)); 1634 break; 1635 default: 1636 *val = in_le32((u32 *)(addr + offset)); 1637 break; 1638 } 1639 1640 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" 1641 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", 1642 bus->number, hose->first_busno, hose->last_busno, 1643 devfn, offset, len, addr + offset, *val); 1644 1645 /* Check for CRS (440SPe rev B does that for us but heh ..) */ 1646 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { 1647 pr_debug("Got CRS !\n"); 1648 if (len != 4 || offset != 0) 1649 return PCIBIOS_DEVICE_NOT_FOUND; 1650 *val = 0xffff0001; 1651 } 1652 1653 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); 1654 1655 return PCIBIOS_SUCCESSFUL; 1656} 1657 1658static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn, 1659 int offset, int len, u32 val) 1660{ 1661 struct pci_controller *hose = pci_bus_to_host(bus); 1662 struct ppc4xx_pciex_port *port = 1663 &ppc4xx_pciex_ports[hose->indirect_type]; 1664 void __iomem *addr; 1665 u32 gpl_cfg; 1666 1667 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) 1668 return PCIBIOS_DEVICE_NOT_FOUND; 1669 1670 addr = ppc4xx_pciex_get_config_base(port, bus, devfn); 1671 1672 /* 1673 * Reading from configuration space of non-existing device can 1674 * generate transaction errors. For the read duration we suppress 1675 * assertion of machine check exceptions to avoid those. 1676 */ 1677 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); 1678 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); 1679 1680 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" 1681 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", 1682 bus->number, hose->first_busno, hose->last_busno, 1683 devfn, offset, len, addr + offset, val); 1684 1685 switch (len) { 1686 case 1: 1687 out_8((u8 *)(addr + offset), val); 1688 break; 1689 case 2: 1690 out_le16((u16 *)(addr + offset), val); 1691 break; 1692 default: 1693 out_le32((u32 *)(addr + offset), val); 1694 break; 1695 } 1696 1697 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); 1698 1699 return PCIBIOS_SUCCESSFUL; 1700} 1701 1702static struct pci_ops ppc4xx_pciex_pci_ops = 1703{ 1704 .read = ppc4xx_pciex_read_config, 1705 .write = ppc4xx_pciex_write_config, 1706}; 1707 1708static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port, 1709 struct pci_controller *hose, 1710 void __iomem *mbase, 1711 u64 plb_addr, 1712 u64 pci_addr, 1713 u64 size, 1714 unsigned int flags, 1715 int index) 1716{ 1717 u32 lah, lal, pciah, pcial, sa; 1718 1719 if (!is_power_of_2(size) || 1720 (index < 2 && size < 0x100000) || 1721 (index == 2 && size < 0x100) || 1722 (plb_addr & (size - 1)) != 0) { 1723 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn); 1724 return -1; 1725 } 1726 1727 /* Calculate register values */ 1728 lah = RES_TO_U32_HIGH(plb_addr); 1729 lal = RES_TO_U32_LOW(plb_addr); 1730 pciah = RES_TO_U32_HIGH(pci_addr); 1731 pcial = RES_TO_U32_LOW(pci_addr); 1732 sa = (0xffffffffu << ilog2(size)) | 0x1; 1733 1734 /* Program register values */ 1735 switch (index) { 1736 case 0: 1737 out_le32(mbase + PECFG_POM0LAH, pciah); 1738 out_le32(mbase + PECFG_POM0LAL, pcial); 1739 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah); 1740 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal); 1741 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); 1742 /*Enabled and single region */ 1743 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) 1744 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 1745 sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT 1746 | DCRO_PEGPL_OMRxMSKL_VAL); 1747 else if (of_device_is_compatible( 1748 port->node, "ibm,plb-pciex-476fpe") || 1749 of_device_is_compatible( 1750 port->node, "ibm,plb-pciex-476gtr")) 1751 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 1752 sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT 1753 | DCRO_PEGPL_OMRxMSKL_VAL); 1754 else 1755 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 1756 sa | DCRO_PEGPL_OMR1MSKL_UOT 1757 | DCRO_PEGPL_OMRxMSKL_VAL); 1758 break; 1759 case 1: 1760 out_le32(mbase + PECFG_POM1LAH, pciah); 1761 out_le32(mbase + PECFG_POM1LAL, pcial); 1762 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); 1763 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); 1764 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); 1765 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 1766 sa | DCRO_PEGPL_OMRxMSKL_VAL); 1767 break; 1768 case 2: 1769 out_le32(mbase + PECFG_POM2LAH, pciah); 1770 out_le32(mbase + PECFG_POM2LAL, pcial); 1771 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah); 1772 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal); 1773 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); 1774 /* Note that 3 here means enabled | IO space !!! */ 1775 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 1776 sa | DCRO_PEGPL_OMR3MSKL_IO 1777 | DCRO_PEGPL_OMRxMSKL_VAL); 1778 break; 1779 } 1780 1781 return 0; 1782} 1783 1784static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port, 1785 struct pci_controller *hose, 1786 void __iomem *mbase) 1787{ 1788 int i, j, found_isa_hole = 0; 1789 1790 /* Setup outbound memory windows */ 1791 for (i = j = 0; i < 3; i++) { 1792 struct resource *res = &hose->mem_resources[i]; 1793 resource_size_t offset = hose->mem_offset[i]; 1794 1795 /* we only care about memory windows */ 1796 if (!(res->flags & IORESOURCE_MEM)) 1797 continue; 1798 if (j > 1) { 1799 printk(KERN_WARNING "%pOF: Too many ranges\n", 1800 port->node); 1801 break; 1802 } 1803 1804 /* Configure the resource */ 1805 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, 1806 res->start, 1807 res->start - offset, 1808 resource_size(res), 1809 res->flags, 1810 j) == 0) { 1811 j++; 1812 1813 /* If the resource PCI address is 0 then we have our 1814 * ISA memory hole 1815 */ 1816 if (res->start == offset) 1817 found_isa_hole = 1; 1818 } 1819 } 1820 1821 /* Handle ISA memory hole if not already covered */ 1822 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) 1823 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, 1824 hose->isa_mem_phys, 0, 1825 hose->isa_mem_size, 0, j) == 0) 1826 printk(KERN_INFO "%pOF: Legacy ISA memory support enabled\n", 1827 hose->dn); 1828 1829 /* Configure IO, always 64K starting at 0. We hard wire it to 64K ! 1830 * Note also that it -has- to be region index 2 on this HW 1831 */ 1832 if (hose->io_resource.flags & IORESOURCE_IO) 1833 ppc4xx_setup_one_pciex_POM(port, hose, mbase, 1834 hose->io_base_phys, 0, 1835 0x10000, IORESOURCE_IO, 2); 1836} 1837 1838static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port, 1839 struct pci_controller *hose, 1840 void __iomem *mbase, 1841 struct resource *res) 1842{ 1843 resource_size_t size = resource_size(res); 1844 u64 sa; 1845 1846 if (port->endpoint) { 1847 resource_size_t ep_addr = 0; 1848 resource_size_t ep_size = 32 << 20; 1849 1850 /* Currently we map a fixed 64MByte window to PLB address 1851 * 0 (SDRAM). This should probably be configurable via a dts 1852 * property. 1853 */ 1854 1855 /* Calculate window size */ 1856 sa = (0xffffffffffffffffull << ilog2(ep_size)); 1857 1858 /* Setup BAR0 */ 1859 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); 1860 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) | 1861 PCI_BASE_ADDRESS_MEM_TYPE_64); 1862 1863 /* Disable BAR1 & BAR2 */ 1864 out_le32(mbase + PECFG_BAR1MPA, 0); 1865 out_le32(mbase + PECFG_BAR2HMPA, 0); 1866 out_le32(mbase + PECFG_BAR2LMPA, 0); 1867 1868 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa)); 1869 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa)); 1870 1871 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr)); 1872 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr)); 1873 } else { 1874 /* Calculate window size */ 1875 sa = (0xffffffffffffffffull << ilog2(size)); 1876 if (res->flags & IORESOURCE_PREFETCH) 1877 sa |= PCI_BASE_ADDRESS_MEM_PREFETCH; 1878 1879 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") || 1880 of_device_is_compatible( 1881 port->node, "ibm,plb-pciex-476fpe") || 1882 of_device_is_compatible( 1883 port->node, "ibm,plb-pciex-476gtr")) 1884 sa |= PCI_BASE_ADDRESS_MEM_TYPE_64; 1885 1886 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); 1887 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa)); 1888 1889 /* The setup of the split looks weird to me ... let's see 1890 * if it works 1891 */ 1892 out_le32(mbase + PECFG_PIM0LAL, 0x00000000); 1893 out_le32(mbase + PECFG_PIM0LAH, 0x00000000); 1894 out_le32(mbase + PECFG_PIM1LAL, 0x00000000); 1895 out_le32(mbase + PECFG_PIM1LAH, 0x00000000); 1896 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); 1897 out_le32(mbase + PECFG_PIM01SAL, 0x00000000); 1898 1899 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start)); 1900 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start)); 1901 } 1902 1903 /* Enable inbound mapping */ 1904 out_le32(mbase + PECFG_PIMEN, 0x1); 1905 1906 /* Enable I/O, Mem, and Busmaster cycles */ 1907 out_le16(mbase + PCI_COMMAND, 1908 in_le16(mbase + PCI_COMMAND) | 1909 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 1910} 1911 1912static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port) 1913{ 1914 struct resource dma_window; 1915 struct pci_controller *hose = NULL; 1916 const int *bus_range; 1917 int primary = 0, busses; 1918 void __iomem *mbase = NULL, *cfg_data = NULL; 1919 const u32 *pval; 1920 u32 val; 1921 1922 /* Check if primary bridge */ 1923 if (of_get_property(port->node, "primary", NULL)) 1924 primary = 1; 1925 1926 /* Get bus range if any */ 1927 bus_range = of_get_property(port->node, "bus-range", NULL); 1928 1929 /* Allocate the host controller data structure */ 1930 hose = pcibios_alloc_controller(port->node); 1931 if (!hose) 1932 goto fail; 1933 1934 /* We stick the port number in "indirect_type" so the config space 1935 * ops can retrieve the port data structure easily 1936 */ 1937 hose->indirect_type = port->index; 1938 1939 /* Get bus range */ 1940 hose->first_busno = bus_range ? bus_range[0] : 0x0; 1941 hose->last_busno = bus_range ? bus_range[1] : 0xff; 1942 1943 /* Because of how big mapping the config space is (1M per bus), we 1944 * limit how many busses we support. In the long run, we could replace 1945 * that with something akin to kmap_atomic instead. We set aside 1 bus 1946 * for the host itself too. 1947 */ 1948 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */ 1949 if (busses > MAX_PCIE_BUS_MAPPED) { 1950 busses = MAX_PCIE_BUS_MAPPED; 1951 hose->last_busno = hose->first_busno + busses; 1952 } 1953 1954 if (!port->endpoint) { 1955 /* Only map the external config space in cfg_data for 1956 * PCIe root-complexes. External space is 1M per bus 1957 */ 1958 cfg_data = ioremap(port->cfg_space.start + 1959 (hose->first_busno + 1) * 0x100000, 1960 busses * 0x100000); 1961 if (cfg_data == NULL) { 1962 printk(KERN_ERR "%pOF: Can't map external config space !", 1963 port->node); 1964 goto fail; 1965 } 1966 hose->cfg_data = cfg_data; 1967 } 1968 1969 /* Always map the host config space in cfg_addr. 1970 * Internal space is 4K 1971 */ 1972 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); 1973 if (mbase == NULL) { 1974 printk(KERN_ERR "%pOF: Can't map internal config space !", 1975 port->node); 1976 goto fail; 1977 } 1978 hose->cfg_addr = mbase; 1979 1980 pr_debug("PCIE %pOF, bus %d..%d\n", port->node, 1981 hose->first_busno, hose->last_busno); 1982 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n", 1983 hose->cfg_addr, hose->cfg_data); 1984 1985 /* Setup config space */ 1986 hose->ops = &ppc4xx_pciex_pci_ops; 1987 port->hose = hose; 1988 mbase = (void __iomem *)hose->cfg_addr; 1989 1990 if (!port->endpoint) { 1991 /* 1992 * Set bus numbers on our root port 1993 */ 1994 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno); 1995 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1); 1996 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno); 1997 } 1998 1999 /* 2000 * OMRs are already reset, also disable PIMs 2001 */ 2002 out_le32(mbase + PECFG_PIMEN, 0); 2003 2004 /* Parse outbound mapping resources */ 2005 pci_process_bridge_OF_ranges(hose, port->node, primary); 2006 2007 /* Parse inbound mapping resources */ 2008 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0) 2009 goto fail; 2010 2011 /* Configure outbound ranges POMs */ 2012 ppc4xx_configure_pciex_POMs(port, hose, mbase); 2013 2014 /* Configure inbound ranges PIMs */ 2015 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window); 2016 2017 /* The root complex doesn't show up if we don't set some vendor 2018 * and device IDs into it. The defaults below are the same bogus 2019 * one that the initial code in arch/ppc had. This can be 2020 * overwritten by setting the "vendor-id/device-id" properties 2021 * in the pciex node. 2022 */ 2023 2024 /* Get the (optional) vendor-/device-id from the device-tree */ 2025 pval = of_get_property(port->node, "vendor-id", NULL); 2026 if (pval) { 2027 val = *pval; 2028 } else { 2029 if (!port->endpoint) 2030 val = 0xaaa0 + port->index; 2031 else 2032 val = 0xeee0 + port->index; 2033 } 2034 out_le16(mbase + 0x200, val); 2035 2036 pval = of_get_property(port->node, "device-id", NULL); 2037 if (pval) { 2038 val = *pval; 2039 } else { 2040 if (!port->endpoint) 2041 val = 0xbed0 + port->index; 2042 else 2043 val = 0xfed0 + port->index; 2044 } 2045 out_le16(mbase + 0x202, val); 2046 2047 /* Enable Bus master, memory, and io space */ 2048 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) 2049 out_le16(mbase + 0x204, 0x7); 2050 2051 if (!port->endpoint) { 2052 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ 2053 out_le32(mbase + 0x208, 0x06040001); 2054 2055 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n", 2056 port->index); 2057 } else { 2058 /* Set Class Code to Processor/PPC */ 2059 out_le32(mbase + 0x208, 0x0b200001); 2060 2061 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n", 2062 port->index); 2063 } 2064 2065 return; 2066 fail: 2067 if (hose) 2068 pcibios_free_controller(hose); 2069 if (cfg_data) 2070 iounmap(cfg_data); 2071 if (mbase) 2072 iounmap(mbase); 2073} 2074 2075static void __init ppc4xx_probe_pciex_bridge(struct device_node *np) 2076{ 2077 struct ppc4xx_pciex_port *port; 2078 const u32 *pval; 2079 int portno; 2080 unsigned int dcrs; 2081 2082 /* First, proceed to core initialization as we assume there's 2083 * only one PCIe core in the system 2084 */ 2085 if (ppc4xx_pciex_check_core_init(np)) 2086 return; 2087 2088 /* Get the port number from the device-tree */ 2089 pval = of_get_property(np, "port", NULL); 2090 if (pval == NULL) { 2091 printk(KERN_ERR "PCIE: Can't find port number for %pOF\n", np); 2092 return; 2093 } 2094 portno = *pval; 2095 if (portno >= ppc4xx_pciex_port_count) { 2096 printk(KERN_ERR "PCIE: port number out of range for %pOF\n", 2097 np); 2098 return; 2099 } 2100 port = &ppc4xx_pciex_ports[portno]; 2101 port->index = portno; 2102 2103 /* 2104 * Check if device is enabled 2105 */ 2106 if (!of_device_is_available(np)) { 2107 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index); 2108 return; 2109 } 2110 2111 port->node = of_node_get(np); 2112 if (ppc4xx_pciex_hwops->want_sdr) { 2113 pval = of_get_property(np, "sdr-base", NULL); 2114 if (pval == NULL) { 2115 printk(KERN_ERR "PCIE: missing sdr-base for %pOF\n", 2116 np); 2117 return; 2118 } 2119 port->sdr_base = *pval; 2120 } 2121 2122 /* Check if device_type property is set to "pci" or "pci-endpoint". 2123 * Resulting from this setup this PCIe port will be configured 2124 * as root-complex or as endpoint. 2125 */ 2126 if (of_node_is_type(port->node, "pci-endpoint")) { 2127 port->endpoint = 1; 2128 } else if (of_node_is_type(port->node, "pci")) { 2129 port->endpoint = 0; 2130 } else { 2131 printk(KERN_ERR "PCIE: missing or incorrect device_type for %pOF\n", 2132 np); 2133 return; 2134 } 2135 2136 /* Fetch config space registers address */ 2137 if (of_address_to_resource(np, 0, &port->cfg_space)) { 2138 printk(KERN_ERR "%pOF: Can't get PCI-E config space !", np); 2139 return; 2140 } 2141 /* Fetch host bridge internal registers address */ 2142 if (of_address_to_resource(np, 1, &port->utl_regs)) { 2143 printk(KERN_ERR "%pOF: Can't get UTL register base !", np); 2144 return; 2145 } 2146 2147 /* Map DCRs */ 2148 dcrs = dcr_resource_start(np, 0); 2149 if (dcrs == 0) { 2150 printk(KERN_ERR "%pOF: Can't get DCR register base !", np); 2151 return; 2152 } 2153 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); 2154 2155 /* Initialize the port specific registers */ 2156 if (ppc4xx_pciex_port_init(port)) { 2157 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index); 2158 return; 2159 } 2160 2161 /* Setup the linux hose data structure */ 2162 ppc4xx_pciex_port_setup_hose(port); 2163} 2164 2165#endif /* CONFIG_PPC4xx_PCI_EXPRESS */ 2166 2167static int __init ppc4xx_pci_find_bridges(void) 2168{ 2169 struct device_node *np; 2170 2171 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); 2172 2173#ifdef CONFIG_PPC4xx_PCI_EXPRESS 2174 for_each_compatible_node(np, NULL, "ibm,plb-pciex") 2175 ppc4xx_probe_pciex_bridge(np); 2176#endif 2177 for_each_compatible_node(np, NULL, "ibm,plb-pcix") 2178 ppc4xx_probe_pcix_bridge(np); 2179 for_each_compatible_node(np, NULL, "ibm,plb-pci") 2180 ppc4xx_probe_pci_bridge(np); 2181 2182 return 0; 2183} 2184arch_initcall(ppc4xx_pci_find_bridges); 2185 2186