18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * PPC476 board specific routines
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * Copyright 2010 Torez Smith, IBM Corporation.
68c2ecf20Sopenharmony_ci *
78c2ecf20Sopenharmony_ci * Based on earlier code:
88c2ecf20Sopenharmony_ci *    Matt Porter <mporter@kernel.crashing.org>
98c2ecf20Sopenharmony_ci *    Copyright 2002-2005 MontaVista Software Inc.
108c2ecf20Sopenharmony_ci *
118c2ecf20Sopenharmony_ci *    Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
128c2ecf20Sopenharmony_ci *    Copyright (c) 2003-2005 Zultys Technologies
138c2ecf20Sopenharmony_ci *
148c2ecf20Sopenharmony_ci *    Rewritten and ported to the merged powerpc tree:
158c2ecf20Sopenharmony_ci *    Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
168c2ecf20Sopenharmony_ci */
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ci#include <linux/init.h>
198c2ecf20Sopenharmony_ci#include <linux/of_platform.h>
208c2ecf20Sopenharmony_ci#include <linux/rtc.h>
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ci#include <asm/machdep.h>
238c2ecf20Sopenharmony_ci#include <asm/prom.h>
248c2ecf20Sopenharmony_ci#include <asm/udbg.h>
258c2ecf20Sopenharmony_ci#include <asm/time.h>
268c2ecf20Sopenharmony_ci#include <asm/uic.h>
278c2ecf20Sopenharmony_ci#include <asm/ppc4xx.h>
288c2ecf20Sopenharmony_ci#include <asm/mpic.h>
298c2ecf20Sopenharmony_ci#include <asm/mmu.h>
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_cistatic const struct of_device_id iss4xx_of_bus[] __initconst = {
328c2ecf20Sopenharmony_ci	{ .compatible = "ibm,plb4", },
338c2ecf20Sopenharmony_ci	{ .compatible = "ibm,plb6", },
348c2ecf20Sopenharmony_ci	{ .compatible = "ibm,opb", },
358c2ecf20Sopenharmony_ci	{ .compatible = "ibm,ebc", },
368c2ecf20Sopenharmony_ci	{},
378c2ecf20Sopenharmony_ci};
388c2ecf20Sopenharmony_ci
398c2ecf20Sopenharmony_cistatic int __init iss4xx_device_probe(void)
408c2ecf20Sopenharmony_ci{
418c2ecf20Sopenharmony_ci	of_platform_bus_probe(NULL, iss4xx_of_bus, NULL);
428c2ecf20Sopenharmony_ci	of_instantiate_rtc();
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ci	return 0;
458c2ecf20Sopenharmony_ci}
468c2ecf20Sopenharmony_cimachine_device_initcall(iss4xx, iss4xx_device_probe);
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci/* We can have either UICs or MPICs */
498c2ecf20Sopenharmony_cistatic void __init iss4xx_init_irq(void)
508c2ecf20Sopenharmony_ci{
518c2ecf20Sopenharmony_ci	struct device_node *np;
528c2ecf20Sopenharmony_ci
538c2ecf20Sopenharmony_ci	/* Find top level interrupt controller */
548c2ecf20Sopenharmony_ci	for_each_node_with_property(np, "interrupt-controller") {
558c2ecf20Sopenharmony_ci		if (of_get_property(np, "interrupts", NULL) == NULL)
568c2ecf20Sopenharmony_ci			break;
578c2ecf20Sopenharmony_ci	}
588c2ecf20Sopenharmony_ci	if (np == NULL)
598c2ecf20Sopenharmony_ci		panic("Can't find top level interrupt controller");
608c2ecf20Sopenharmony_ci
618c2ecf20Sopenharmony_ci	/* Check type and do appropriate initialization */
628c2ecf20Sopenharmony_ci	if (of_device_is_compatible(np, "ibm,uic")) {
638c2ecf20Sopenharmony_ci		uic_init_tree();
648c2ecf20Sopenharmony_ci		ppc_md.get_irq = uic_get_irq;
658c2ecf20Sopenharmony_ci#ifdef CONFIG_MPIC
668c2ecf20Sopenharmony_ci	} else if (of_device_is_compatible(np, "chrp,open-pic")) {
678c2ecf20Sopenharmony_ci		/* The MPIC driver will get everything it needs from the
688c2ecf20Sopenharmony_ci		 * device-tree, just pass 0 to all arguments
698c2ecf20Sopenharmony_ci		 */
708c2ecf20Sopenharmony_ci		struct mpic *mpic = mpic_alloc(np, 0, MPIC_NO_RESET, 0, 0, " MPIC     ");
718c2ecf20Sopenharmony_ci		BUG_ON(mpic == NULL);
728c2ecf20Sopenharmony_ci		mpic_init(mpic);
738c2ecf20Sopenharmony_ci		ppc_md.get_irq = mpic_get_irq;
748c2ecf20Sopenharmony_ci#endif
758c2ecf20Sopenharmony_ci	} else
768c2ecf20Sopenharmony_ci		panic("Unrecognized top level interrupt controller");
778c2ecf20Sopenharmony_ci}
788c2ecf20Sopenharmony_ci
798c2ecf20Sopenharmony_ci#ifdef CONFIG_SMP
808c2ecf20Sopenharmony_cistatic void smp_iss4xx_setup_cpu(int cpu)
818c2ecf20Sopenharmony_ci{
828c2ecf20Sopenharmony_ci	mpic_setup_this_cpu();
838c2ecf20Sopenharmony_ci}
848c2ecf20Sopenharmony_ci
858c2ecf20Sopenharmony_cistatic int smp_iss4xx_kick_cpu(int cpu)
868c2ecf20Sopenharmony_ci{
878c2ecf20Sopenharmony_ci	struct device_node *cpunode = of_get_cpu_node(cpu, NULL);
888c2ecf20Sopenharmony_ci	const u64 *spin_table_addr_prop;
898c2ecf20Sopenharmony_ci	u32 *spin_table;
908c2ecf20Sopenharmony_ci	extern void start_secondary_47x(void);
918c2ecf20Sopenharmony_ci
928c2ecf20Sopenharmony_ci	BUG_ON(cpunode == NULL);
938c2ecf20Sopenharmony_ci
948c2ecf20Sopenharmony_ci	/* Assume spin table. We could test for the enable-method in
958c2ecf20Sopenharmony_ci	 * the device-tree but currently there's little point as it's
968c2ecf20Sopenharmony_ci	 * our only supported method
978c2ecf20Sopenharmony_ci	 */
988c2ecf20Sopenharmony_ci	spin_table_addr_prop = of_get_property(cpunode, "cpu-release-addr",
998c2ecf20Sopenharmony_ci					       NULL);
1008c2ecf20Sopenharmony_ci	if (spin_table_addr_prop == NULL) {
1018c2ecf20Sopenharmony_ci		pr_err("CPU%d: Can't start, missing cpu-release-addr !\n", cpu);
1028c2ecf20Sopenharmony_ci		return -ENOENT;
1038c2ecf20Sopenharmony_ci	}
1048c2ecf20Sopenharmony_ci
1058c2ecf20Sopenharmony_ci	/* Assume it's mapped as part of the linear mapping. This is a bit
1068c2ecf20Sopenharmony_ci	 * fishy but will work fine for now
1078c2ecf20Sopenharmony_ci	 */
1088c2ecf20Sopenharmony_ci	spin_table = (u32 *)__va(*spin_table_addr_prop);
1098c2ecf20Sopenharmony_ci	pr_debug("CPU%d: Spin table mapped at %p\n", cpu, spin_table);
1108c2ecf20Sopenharmony_ci
1118c2ecf20Sopenharmony_ci	spin_table[3] = cpu;
1128c2ecf20Sopenharmony_ci	smp_wmb();
1138c2ecf20Sopenharmony_ci	spin_table[1] = __pa(start_secondary_47x);
1148c2ecf20Sopenharmony_ci	mb();
1158c2ecf20Sopenharmony_ci
1168c2ecf20Sopenharmony_ci	return 0;
1178c2ecf20Sopenharmony_ci}
1188c2ecf20Sopenharmony_ci
1198c2ecf20Sopenharmony_cistatic struct smp_ops_t iss_smp_ops = {
1208c2ecf20Sopenharmony_ci	.probe		= smp_mpic_probe,
1218c2ecf20Sopenharmony_ci	.message_pass	= smp_mpic_message_pass,
1228c2ecf20Sopenharmony_ci	.setup_cpu	= smp_iss4xx_setup_cpu,
1238c2ecf20Sopenharmony_ci	.kick_cpu	= smp_iss4xx_kick_cpu,
1248c2ecf20Sopenharmony_ci	.give_timebase	= smp_generic_give_timebase,
1258c2ecf20Sopenharmony_ci	.take_timebase	= smp_generic_take_timebase,
1268c2ecf20Sopenharmony_ci};
1278c2ecf20Sopenharmony_ci
1288c2ecf20Sopenharmony_cistatic void __init iss4xx_smp_init(void)
1298c2ecf20Sopenharmony_ci{
1308c2ecf20Sopenharmony_ci	if (mmu_has_feature(MMU_FTR_TYPE_47x))
1318c2ecf20Sopenharmony_ci		smp_ops = &iss_smp_ops;
1328c2ecf20Sopenharmony_ci}
1338c2ecf20Sopenharmony_ci
1348c2ecf20Sopenharmony_ci#else /* CONFIG_SMP */
1358c2ecf20Sopenharmony_cistatic void __init iss4xx_smp_init(void) { }
1368c2ecf20Sopenharmony_ci#endif /* CONFIG_SMP */
1378c2ecf20Sopenharmony_ci
1388c2ecf20Sopenharmony_cistatic void __init iss4xx_setup_arch(void)
1398c2ecf20Sopenharmony_ci{
1408c2ecf20Sopenharmony_ci	iss4xx_smp_init();
1418c2ecf20Sopenharmony_ci}
1428c2ecf20Sopenharmony_ci
1438c2ecf20Sopenharmony_ci/*
1448c2ecf20Sopenharmony_ci * Called very early, MMU is off, device-tree isn't unflattened
1458c2ecf20Sopenharmony_ci */
1468c2ecf20Sopenharmony_cistatic int __init iss4xx_probe(void)
1478c2ecf20Sopenharmony_ci{
1488c2ecf20Sopenharmony_ci	if (!of_machine_is_compatible("ibm,iss-4xx"))
1498c2ecf20Sopenharmony_ci		return 0;
1508c2ecf20Sopenharmony_ci
1518c2ecf20Sopenharmony_ci	return 1;
1528c2ecf20Sopenharmony_ci}
1538c2ecf20Sopenharmony_ci
1548c2ecf20Sopenharmony_cidefine_machine(iss4xx) {
1558c2ecf20Sopenharmony_ci	.name			= "ISS-4xx",
1568c2ecf20Sopenharmony_ci	.probe			= iss4xx_probe,
1578c2ecf20Sopenharmony_ci	.progress		= udbg_progress,
1588c2ecf20Sopenharmony_ci	.init_IRQ		= iss4xx_init_irq,
1598c2ecf20Sopenharmony_ci	.setup_arch		= iss4xx_setup_arch,
1608c2ecf20Sopenharmony_ci	.restart		= ppc4xx_reset_system,
1618c2ecf20Sopenharmony_ci	.calibrate_decr		= generic_calibrate_decr,
1628c2ecf20Sopenharmony_ci};
163