1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Performance counter support for POWER9 processors.
4 *
5 * Copyright 2009 Paul Mackerras, IBM Corporation.
6 * Copyright 2013 Michael Ellerman, IBM Corporation.
7 * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
8 */
9
10#define pr_fmt(fmt)	"power9-pmu: " fmt
11
12#include "isa207-common.h"
13
14/*
15 * Raw event encoding for Power9:
16 *
17 *        60        56        52        48        44        40        36        32
18 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
19 *   | | [ ]                       [ ] [      thresh_cmp     ]   [  thresh_ctl   ]
20 *   | |  |                         |                                     |
21 *   | |  *- IFM (Linux)            |	               thresh start/stop -*
22 *   | *- BHRB (Linux)              *sm
23 *   *- EBB (Linux)
24 *
25 *        28        24        20        16        12         8         4         0
26 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
27 *   [   ] [  sample ]   [cache]   [ pmc ]   [unit ]   []    m   [    pmcxsel    ]
28 *     |        |           |                          |     |
29 *     |        |           |                          |     *- mark
30 *     |        |           *- L1/L2/L3 cache_sel      |
31 *     |        |                                      |
32 *     |        *- sampling mode for marked events     *- combine
33 *     |
34 *     *- thresh_sel
35 *
36 * Below uses IBM bit numbering.
37 *
38 * MMCR1[x:y] = unit    (PMCxUNIT)
39 * MMCR1[24]   = pmc1combine[0]
40 * MMCR1[25]   = pmc1combine[1]
41 * MMCR1[26]   = pmc2combine[0]
42 * MMCR1[27]   = pmc2combine[1]
43 * MMCR1[28]   = pmc3combine[0]
44 * MMCR1[29]   = pmc3combine[1]
45 * MMCR1[30]   = pmc4combine[0]
46 * MMCR1[31]   = pmc4combine[1]
47 *
48 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
49 *	MMCR1[20:27] = thresh_ctl
50 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
51 *	MMCR1[20:27] = thresh_ctl
52 * else
53 *	MMCRA[48:55] = thresh_ctl   (THRESH START/END)
54 *
55 * if thresh_sel:
56 *	MMCRA[45:47] = thresh_sel
57 *
58 * if thresh_cmp:
59 *	MMCRA[9:11] = thresh_cmp[0:2]
60 *	MMCRA[12:18] = thresh_cmp[3:9]
61 *
62 * MMCR1[16] = cache_sel[2]
63 * MMCR1[17] = cache_sel[3]
64 *
65 * if mark:
66 *	MMCRA[63]    = 1		(SAMPLE_ENABLE)
67 *	MMCRA[57:59] = sample[0:2]	(RAND_SAMP_ELIG)
68 *	MMCRA[61:62] = sample[3:4]	(RAND_SAMP_MODE)
69 *
70 * if EBB and BHRB:
71 *	MMCRA[32:33] = IFM
72 *
73 * MMCRA[SDAR_MODE]  = sm
74 */
75
76/*
77 * Some power9 event codes.
78 */
79#define EVENT(_name, _code)	_name = _code,
80
81enum {
82#include "power9-events-list.h"
83};
84
85#undef EVENT
86
87/* MMCRA IFM bits - POWER9 */
88#define POWER9_MMCRA_IFM1		0x0000000040000000UL
89#define POWER9_MMCRA_IFM2		0x0000000080000000UL
90#define POWER9_MMCRA_IFM3		0x00000000C0000000UL
91#define POWER9_MMCRA_BHRB_MASK		0x00000000C0000000UL
92
93extern u64 PERF_REG_EXTENDED_MASK;
94
95/* Nasty Power9 specific hack */
96#define PVR_POWER9_CUMULUS		0x00002000
97
98/* PowerISA v2.07 format attribute structure*/
99extern struct attribute_group isa207_pmu_format_group;
100
101int p9_dd21_bl_ev[] = {
102	PM_MRK_ST_DONE_L2,
103	PM_RADIX_PWC_L1_HIT,
104	PM_FLOP_CMPL,
105	PM_MRK_NTF_FIN,
106	PM_RADIX_PWC_L2_HIT,
107	PM_IFETCH_THROTTLE,
108	PM_MRK_L2_TM_ST_ABORT_SISTER,
109	PM_RADIX_PWC_L3_HIT,
110	PM_RUN_CYC_SMT2_MODE,
111	PM_TM_TX_PASS_RUN_INST,
112	PM_DISP_HELD_SYNC_HOLD,
113};
114
115int p9_dd22_bl_ev[] = {
116	PM_DTLB_MISS_16G,
117	PM_DERAT_MISS_2M,
118	PM_DTLB_MISS_2M,
119	PM_MRK_DTLB_MISS_1G,
120	PM_DTLB_MISS_4K,
121	PM_DERAT_MISS_1G,
122	PM_MRK_DERAT_MISS_2M,
123	PM_MRK_DTLB_MISS_4K,
124	PM_MRK_DTLB_MISS_16G,
125	PM_DTLB_MISS_64K,
126	PM_MRK_DERAT_MISS_1G,
127	PM_MRK_DTLB_MISS_64K,
128	PM_DISP_HELD_SYNC_HOLD,
129	PM_DTLB_MISS_16M,
130	PM_DTLB_MISS_1G,
131	PM_MRK_DTLB_MISS_16M,
132};
133
134/* Table of alternatives, sorted by column 0 */
135static const unsigned int power9_event_alternatives[][MAX_ALT] = {
136	{ PM_BR_2PATH,			PM_BR_2PATH_ALT },
137	{ PM_INST_DISP,			PM_INST_DISP_ALT },
138	{ PM_RUN_CYC_ALT,               PM_RUN_CYC },
139	{ PM_LD_MISS_L1,                PM_LD_MISS_L1_ALT },
140	{ PM_RUN_INST_CMPL_ALT,         PM_RUN_INST_CMPL },
141};
142
143static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
144{
145	int num_alt = 0;
146
147	num_alt = isa207_get_alternatives(event, alt,
148					  ARRAY_SIZE(power9_event_alternatives), flags,
149					  power9_event_alternatives);
150
151	return num_alt;
152}
153
154GENERIC_EVENT_ATTR(cpu-cycles,			PM_CYC);
155GENERIC_EVENT_ATTR(stalled-cycles-frontend,	PM_ICT_NOSLOT_CYC);
156GENERIC_EVENT_ATTR(stalled-cycles-backend,	PM_CMPLU_STALL);
157GENERIC_EVENT_ATTR(instructions,		PM_INST_CMPL);
158GENERIC_EVENT_ATTR(branch-instructions,		PM_BR_CMPL);
159GENERIC_EVENT_ATTR(branch-misses,		PM_BR_MPRED_CMPL);
160GENERIC_EVENT_ATTR(cache-references,		PM_LD_REF_L1);
161GENERIC_EVENT_ATTR(cache-misses,		PM_LD_MISS_L1_FIN);
162GENERIC_EVENT_ATTR(mem-loads,			MEM_LOADS);
163GENERIC_EVENT_ATTR(mem-stores,			MEM_STORES);
164
165CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1_FIN);
166CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
167CACHE_EVENT_ATTR(L1-dcache-prefetches,		PM_L1_PREF);
168CACHE_EVENT_ATTR(L1-dcache-store-misses,	PM_ST_MISS_L1);
169CACHE_EVENT_ATTR(L1-icache-load-misses,		PM_L1_ICACHE_MISS);
170CACHE_EVENT_ATTR(L1-icache-loads,		PM_INST_FROM_L1);
171CACHE_EVENT_ATTR(L1-icache-prefetches,		PM_IC_PREF_WRITE);
172CACHE_EVENT_ATTR(LLC-load-misses,		PM_DATA_FROM_L3MISS);
173CACHE_EVENT_ATTR(LLC-loads,			PM_DATA_FROM_L3);
174CACHE_EVENT_ATTR(LLC-prefetches,		PM_L3_PREF_ALL);
175CACHE_EVENT_ATTR(branch-load-misses,		PM_BR_MPRED_CMPL);
176CACHE_EVENT_ATTR(branch-loads,			PM_BR_CMPL);
177CACHE_EVENT_ATTR(dTLB-load-misses,		PM_DTLB_MISS);
178CACHE_EVENT_ATTR(iTLB-load-misses,		PM_ITLB_MISS);
179
180static struct attribute *power9_events_attr[] = {
181	GENERIC_EVENT_PTR(PM_CYC),
182	GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
183	GENERIC_EVENT_PTR(PM_CMPLU_STALL),
184	GENERIC_EVENT_PTR(PM_INST_CMPL),
185	GENERIC_EVENT_PTR(PM_BR_CMPL),
186	GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
187	GENERIC_EVENT_PTR(PM_LD_REF_L1),
188	GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
189	GENERIC_EVENT_PTR(MEM_LOADS),
190	GENERIC_EVENT_PTR(MEM_STORES),
191	CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
192	CACHE_EVENT_PTR(PM_LD_REF_L1),
193	CACHE_EVENT_PTR(PM_L1_PREF),
194	CACHE_EVENT_PTR(PM_ST_MISS_L1),
195	CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
196	CACHE_EVENT_PTR(PM_INST_FROM_L1),
197	CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
198	CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
199	CACHE_EVENT_PTR(PM_DATA_FROM_L3),
200	CACHE_EVENT_PTR(PM_L3_PREF_ALL),
201	CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
202	CACHE_EVENT_PTR(PM_BR_CMPL),
203	CACHE_EVENT_PTR(PM_DTLB_MISS),
204	CACHE_EVENT_PTR(PM_ITLB_MISS),
205	NULL
206};
207
208static struct attribute_group power9_pmu_events_group = {
209	.name = "events",
210	.attrs = power9_events_attr,
211};
212
213PMU_FORMAT_ATTR(event,		"config:0-51");
214PMU_FORMAT_ATTR(pmcxsel,	"config:0-7");
215PMU_FORMAT_ATTR(mark,		"config:8");
216PMU_FORMAT_ATTR(combine,	"config:10-11");
217PMU_FORMAT_ATTR(unit,		"config:12-15");
218PMU_FORMAT_ATTR(pmc,		"config:16-19");
219PMU_FORMAT_ATTR(cache_sel,	"config:20-23");
220PMU_FORMAT_ATTR(sample_mode,	"config:24-28");
221PMU_FORMAT_ATTR(thresh_sel,	"config:29-31");
222PMU_FORMAT_ATTR(thresh_stop,	"config:32-35");
223PMU_FORMAT_ATTR(thresh_start,	"config:36-39");
224PMU_FORMAT_ATTR(thresh_cmp,	"config:40-49");
225PMU_FORMAT_ATTR(sdar_mode,	"config:50-51");
226
227static struct attribute *power9_pmu_format_attr[] = {
228	&format_attr_event.attr,
229	&format_attr_pmcxsel.attr,
230	&format_attr_mark.attr,
231	&format_attr_combine.attr,
232	&format_attr_unit.attr,
233	&format_attr_pmc.attr,
234	&format_attr_cache_sel.attr,
235	&format_attr_sample_mode.attr,
236	&format_attr_thresh_sel.attr,
237	&format_attr_thresh_stop.attr,
238	&format_attr_thresh_start.attr,
239	&format_attr_thresh_cmp.attr,
240	&format_attr_sdar_mode.attr,
241	NULL,
242};
243
244static struct attribute_group power9_pmu_format_group = {
245	.name = "format",
246	.attrs = power9_pmu_format_attr,
247};
248
249static const struct attribute_group *power9_pmu_attr_groups[] = {
250	&power9_pmu_format_group,
251	&power9_pmu_events_group,
252	NULL,
253};
254
255static int power9_generic_events[] = {
256	[PERF_COUNT_HW_CPU_CYCLES] =			PM_CYC,
257	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =	PM_ICT_NOSLOT_CYC,
258	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =	PM_CMPLU_STALL,
259	[PERF_COUNT_HW_INSTRUCTIONS] =			PM_INST_CMPL,
260	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =		PM_BR_CMPL,
261	[PERF_COUNT_HW_BRANCH_MISSES] =			PM_BR_MPRED_CMPL,
262	[PERF_COUNT_HW_CACHE_REFERENCES] =		PM_LD_REF_L1,
263	[PERF_COUNT_HW_CACHE_MISSES] =			PM_LD_MISS_L1_FIN,
264};
265
266static u64 power9_bhrb_filter_map(u64 branch_sample_type)
267{
268	u64 pmu_bhrb_filter = 0;
269
270	/* BHRB and regular PMU events share the same privilege state
271	 * filter configuration. BHRB is always recorded along with a
272	 * regular PMU event. As the privilege state filter is handled
273	 * in the basic PMC configuration of the accompanying regular
274	 * PMU event, we ignore any separate BHRB specific request.
275	 */
276
277	/* No branch filter requested */
278	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
279		return pmu_bhrb_filter;
280
281	/* Invalid branch filter options - HW does not support */
282	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
283		return -1;
284
285	if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
286		return -1;
287
288	if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
289		return -1;
290
291	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
292		pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
293		return pmu_bhrb_filter;
294	}
295
296	/* Every thing else is unsupported */
297	return -1;
298}
299
300static void power9_config_bhrb(u64 pmu_bhrb_filter)
301{
302	pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK;
303
304	/* Enable BHRB filter in PMU */
305	mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
306}
307
308#define C(x)	PERF_COUNT_HW_CACHE_##x
309
310/*
311 * Table of generalized cache-related events.
312 * 0 means not supported, -1 means nonsensical, other values
313 * are event codes.
314 */
315static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
316	[ C(L1D) ] = {
317		[ C(OP_READ) ] = {
318			[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
319			[ C(RESULT_MISS)   ] = PM_LD_MISS_L1_FIN,
320		},
321		[ C(OP_WRITE) ] = {
322			[ C(RESULT_ACCESS) ] = 0,
323			[ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
324		},
325		[ C(OP_PREFETCH) ] = {
326			[ C(RESULT_ACCESS) ] = PM_L1_PREF,
327			[ C(RESULT_MISS)   ] = 0,
328		},
329	},
330	[ C(L1I) ] = {
331		[ C(OP_READ) ] = {
332			[ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
333			[ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
334		},
335		[ C(OP_WRITE) ] = {
336			[ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
337			[ C(RESULT_MISS)   ] = -1,
338		},
339		[ C(OP_PREFETCH) ] = {
340			[ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
341			[ C(RESULT_MISS)   ] = 0,
342		},
343	},
344	[ C(LL) ] = {
345		[ C(OP_READ) ] = {
346			[ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
347			[ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
348		},
349		[ C(OP_WRITE) ] = {
350			[ C(RESULT_ACCESS) ] = 0,
351			[ C(RESULT_MISS)   ] = 0,
352		},
353		[ C(OP_PREFETCH) ] = {
354			[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
355			[ C(RESULT_MISS)   ] = 0,
356		},
357	},
358	[ C(DTLB) ] = {
359		[ C(OP_READ) ] = {
360			[ C(RESULT_ACCESS) ] = 0,
361			[ C(RESULT_MISS)   ] = PM_DTLB_MISS,
362		},
363		[ C(OP_WRITE) ] = {
364			[ C(RESULT_ACCESS) ] = -1,
365			[ C(RESULT_MISS)   ] = -1,
366		},
367		[ C(OP_PREFETCH) ] = {
368			[ C(RESULT_ACCESS) ] = -1,
369			[ C(RESULT_MISS)   ] = -1,
370		},
371	},
372	[ C(ITLB) ] = {
373		[ C(OP_READ) ] = {
374			[ C(RESULT_ACCESS) ] = 0,
375			[ C(RESULT_MISS)   ] = PM_ITLB_MISS,
376		},
377		[ C(OP_WRITE) ] = {
378			[ C(RESULT_ACCESS) ] = -1,
379			[ C(RESULT_MISS)   ] = -1,
380		},
381		[ C(OP_PREFETCH) ] = {
382			[ C(RESULT_ACCESS) ] = -1,
383			[ C(RESULT_MISS)   ] = -1,
384		},
385	},
386	[ C(BPU) ] = {
387		[ C(OP_READ) ] = {
388			[ C(RESULT_ACCESS) ] = PM_BR_CMPL,
389			[ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
390		},
391		[ C(OP_WRITE) ] = {
392			[ C(RESULT_ACCESS) ] = -1,
393			[ C(RESULT_MISS)   ] = -1,
394		},
395		[ C(OP_PREFETCH) ] = {
396			[ C(RESULT_ACCESS) ] = -1,
397			[ C(RESULT_MISS)   ] = -1,
398		},
399	},
400	[ C(NODE) ] = {
401		[ C(OP_READ) ] = {
402			[ C(RESULT_ACCESS) ] = -1,
403			[ C(RESULT_MISS)   ] = -1,
404		},
405		[ C(OP_WRITE) ] = {
406			[ C(RESULT_ACCESS) ] = -1,
407			[ C(RESULT_MISS)   ] = -1,
408		},
409		[ C(OP_PREFETCH) ] = {
410			[ C(RESULT_ACCESS) ] = -1,
411			[ C(RESULT_MISS)   ] = -1,
412		},
413	},
414};
415
416#undef C
417
418static struct power_pmu power9_pmu = {
419	.name			= "POWER9",
420	.n_counter		= MAX_PMU_COUNTERS,
421	.add_fields		= ISA207_ADD_FIELDS,
422	.test_adder		= ISA207_TEST_ADDER,
423	.group_constraint_mask	= CNST_CACHE_PMC4_MASK,
424	.group_constraint_val	= CNST_CACHE_PMC4_VAL,
425	.compute_mmcr		= isa207_compute_mmcr,
426	.config_bhrb		= power9_config_bhrb,
427	.bhrb_filter_map	= power9_bhrb_filter_map,
428	.get_constraint		= isa207_get_constraint,
429	.get_alternatives	= power9_get_alternatives,
430	.get_mem_data_src	= isa207_get_mem_data_src,
431	.get_mem_weight		= isa207_get_mem_weight,
432	.disable_pmc		= isa207_disable_pmc,
433	.flags			= PPMU_HAS_SIER | PPMU_ARCH_207S,
434	.n_generic		= ARRAY_SIZE(power9_generic_events),
435	.generic_events		= power9_generic_events,
436	.cache_events		= &power9_cache_events,
437	.attr_groups		= power9_pmu_attr_groups,
438	.bhrb_nr		= 32,
439	.capabilities           = PERF_PMU_CAP_EXTENDED_REGS,
440};
441
442int init_power9_pmu(void)
443{
444	int rc = 0;
445	unsigned int pvr = mfspr(SPRN_PVR);
446
447	/* Comes from cpu_specs[] */
448	if (!cur_cpu_spec->oprofile_cpu_type ||
449	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
450		return -ENODEV;
451
452	/* Blacklist events */
453	if (!(pvr & PVR_POWER9_CUMULUS)) {
454		if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) {
455			power9_pmu.blacklist_ev = p9_dd21_bl_ev;
456			power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev);
457		} else if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 2)) {
458			power9_pmu.blacklist_ev = p9_dd22_bl_ev;
459			power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd22_bl_ev);
460		}
461	}
462
463	/* Set the PERF_REG_EXTENDED_MASK here */
464	PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_300;
465
466	rc = register_power_pmu(&power9_pmu);
467	if (rc)
468		return rc;
469
470	/* Tell userspace that EBB is supported */
471	cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
472
473	return 0;
474}
475