18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Performance counter support for POWER10 processors. 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright 2020 Madhavan Srinivasan, IBM Corporation. 68c2ecf20Sopenharmony_ci * Copyright 2020 Athira Rajeev, IBM Corporation. 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci/* 108c2ecf20Sopenharmony_ci * Power10 event codes. 118c2ecf20Sopenharmony_ci */ 128c2ecf20Sopenharmony_ciEVENT(PM_RUN_CYC, 0x600f4); 138c2ecf20Sopenharmony_ciEVENT(PM_DISP_STALL_CYC, 0x100f8); 148c2ecf20Sopenharmony_ciEVENT(PM_EXEC_STALL, 0x30008); 158c2ecf20Sopenharmony_ciEVENT(PM_RUN_INST_CMPL, 0x500fa); 168c2ecf20Sopenharmony_ciEVENT(PM_BR_CMPL, 0x4d05e); 178c2ecf20Sopenharmony_ciEVENT(PM_BR_MPRED_CMPL, 0x400f6); 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci/* All L1 D cache load references counted at finish, gated by reject */ 208c2ecf20Sopenharmony_ciEVENT(PM_LD_REF_L1, 0x100fc); 218c2ecf20Sopenharmony_ci/* Load Missed L1 */ 228c2ecf20Sopenharmony_ciEVENT(PM_LD_MISS_L1, 0x3e054); 238c2ecf20Sopenharmony_ci/* Store Missed L1 */ 248c2ecf20Sopenharmony_ciEVENT(PM_ST_MISS_L1, 0x300f0); 258c2ecf20Sopenharmony_ci/* L1 cache data prefetches */ 268c2ecf20Sopenharmony_ciEVENT(PM_LD_PREFETCH_CACHE_LINE_MISS, 0x1002c); 278c2ecf20Sopenharmony_ci/* Demand iCache Miss */ 288c2ecf20Sopenharmony_ciEVENT(PM_L1_ICACHE_MISS, 0x200fc); 298c2ecf20Sopenharmony_ci/* Instruction fetches from L1 */ 308c2ecf20Sopenharmony_ciEVENT(PM_INST_FROM_L1, 0x04080); 318c2ecf20Sopenharmony_ci/* Instruction Demand sectors wriittent into IL1 */ 328c2ecf20Sopenharmony_ciEVENT(PM_INST_FROM_L1MISS, 0x03f00000001c040); 338c2ecf20Sopenharmony_ci/* Instruction prefetch written into IL1 */ 348c2ecf20Sopenharmony_ciEVENT(PM_IC_PREF_REQ, 0x040a0); 358c2ecf20Sopenharmony_ci/* The data cache was reloaded from local core's L3 due to a demand load */ 368c2ecf20Sopenharmony_ciEVENT(PM_DATA_FROM_L3, 0x01340000001c040); 378c2ecf20Sopenharmony_ci/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 388c2ecf20Sopenharmony_ciEVENT(PM_DATA_FROM_L3MISS, 0x300fe); 398c2ecf20Sopenharmony_ci/* Data PTEG reload */ 408c2ecf20Sopenharmony_ciEVENT(PM_DTLB_MISS, 0x300fc); 418c2ecf20Sopenharmony_ci/* ITLB Reloaded */ 428c2ecf20Sopenharmony_ciEVENT(PM_ITLB_MISS, 0x400fc); 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ciEVENT(PM_RUN_CYC_ALT, 0x0001e); 458c2ecf20Sopenharmony_ciEVENT(PM_RUN_INST_CMPL_ALT, 0x00002); 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci/* 488c2ecf20Sopenharmony_ci * Memory Access Events 498c2ecf20Sopenharmony_ci * 508c2ecf20Sopenharmony_ci * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) 518c2ecf20Sopenharmony_ci * To enable capturing of memory profiling, these MMCRA bits 528c2ecf20Sopenharmony_ci * needs to be programmed and corresponding raw event format 538c2ecf20Sopenharmony_ci * encoding. 548c2ecf20Sopenharmony_ci * 558c2ecf20Sopenharmony_ci * MMCRA bits encoding needed are 568c2ecf20Sopenharmony_ci * SM (Sampling Mode) 578c2ecf20Sopenharmony_ci * EM (Eligibility for Random Sampling) 588c2ecf20Sopenharmony_ci * TECE (Threshold Event Counter Event) 598c2ecf20Sopenharmony_ci * TS (Threshold Start Event) 608c2ecf20Sopenharmony_ci * TE (Threshold End Event) 618c2ecf20Sopenharmony_ci * 628c2ecf20Sopenharmony_ci * Corresponding Raw Encoding bits: 638c2ecf20Sopenharmony_ci * sample [EM,SM] 648c2ecf20Sopenharmony_ci * thresh_sel (TECE) 658c2ecf20Sopenharmony_ci * thresh start (TS) 668c2ecf20Sopenharmony_ci * thresh end (TE) 678c2ecf20Sopenharmony_ci */ 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_ciEVENT(MEM_LOADS, 0x35340401e0); 708c2ecf20Sopenharmony_ciEVENT(MEM_STORES, 0x353c0401e0); 71