1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Common Performance counter support functions for PowerISA v2.07 processors. 4 * 5 * Copyright 2009 Paul Mackerras, IBM Corporation. 6 * Copyright 2013 Michael Ellerman, IBM Corporation. 7 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 8 */ 9#include "isa207-common.h" 10 11PMU_FORMAT_ATTR(event, "config:0-49"); 12PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 13PMU_FORMAT_ATTR(mark, "config:8"); 14PMU_FORMAT_ATTR(combine, "config:11"); 15PMU_FORMAT_ATTR(unit, "config:12-15"); 16PMU_FORMAT_ATTR(pmc, "config:16-19"); 17PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 18PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 19PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 20PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 21PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 22PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 23 24struct attribute *isa207_pmu_format_attr[] = { 25 &format_attr_event.attr, 26 &format_attr_pmcxsel.attr, 27 &format_attr_mark.attr, 28 &format_attr_combine.attr, 29 &format_attr_unit.attr, 30 &format_attr_pmc.attr, 31 &format_attr_cache_sel.attr, 32 &format_attr_sample_mode.attr, 33 &format_attr_thresh_sel.attr, 34 &format_attr_thresh_stop.attr, 35 &format_attr_thresh_start.attr, 36 &format_attr_thresh_cmp.attr, 37 NULL, 38}; 39 40struct attribute_group isa207_pmu_format_group = { 41 .name = "format", 42 .attrs = isa207_pmu_format_attr, 43}; 44 45static inline bool event_is_fab_match(u64 event) 46{ 47 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ 48 event &= 0xff0fe; 49 50 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ 51 return (event == 0x30056 || event == 0x4f052); 52} 53 54static bool is_event_valid(u64 event) 55{ 56 u64 valid_mask = EVENT_VALID_MASK; 57 58 if (cpu_has_feature(CPU_FTR_ARCH_31)) 59 valid_mask = p10_EVENT_VALID_MASK; 60 else if (cpu_has_feature(CPU_FTR_ARCH_300)) 61 valid_mask = p9_EVENT_VALID_MASK; 62 63 return !(event & ~valid_mask); 64} 65 66static inline bool is_event_marked(u64 event) 67{ 68 if (event & EVENT_IS_MARKED) 69 return true; 70 71 return false; 72} 73 74static unsigned long sdar_mod_val(u64 event) 75{ 76 if (cpu_has_feature(CPU_FTR_ARCH_31)) 77 return p10_SDAR_MODE(event); 78 79 return p9_SDAR_MODE(event); 80} 81 82static void mmcra_sdar_mode(u64 event, unsigned long *mmcra) 83{ 84 /* 85 * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in 86 * continous sampling mode. 87 * 88 * Incase of Power8: 89 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling 90 * mode and will be un-changed when setting MMCRA[63] (Marked events). 91 * 92 * Incase of Power9/power10: 93 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'), 94 * or if group already have any marked events. 95 * For rest 96 * MMCRA[SDAR_MODE] will be set from event code. 97 * If sdar_mode from event is zero, default to 0b01. Hardware 98 * requires that we set a non-zero value. 99 */ 100 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 101 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE)) 102 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES; 103 else if (sdar_mod_val(event)) 104 *mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT; 105 else 106 *mmcra |= MMCRA_SDAR_MODE_DCACHE; 107 } else 108 *mmcra |= MMCRA_SDAR_MODE_TLB; 109} 110 111static u64 thresh_cmp_val(u64 value) 112{ 113 if (cpu_has_feature(CPU_FTR_ARCH_300)) 114 return value << p9_MMCRA_THR_CMP_SHIFT; 115 116 return value << MMCRA_THR_CMP_SHIFT; 117} 118 119static unsigned long combine_from_event(u64 event) 120{ 121 if (cpu_has_feature(CPU_FTR_ARCH_300)) 122 return p9_EVENT_COMBINE(event); 123 124 return EVENT_COMBINE(event); 125} 126 127static unsigned long combine_shift(unsigned long pmc) 128{ 129 if (cpu_has_feature(CPU_FTR_ARCH_300)) 130 return p9_MMCR1_COMBINE_SHIFT(pmc); 131 132 return MMCR1_COMBINE_SHIFT(pmc); 133} 134 135static inline bool event_is_threshold(u64 event) 136{ 137 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 138} 139 140static bool is_thresh_cmp_valid(u64 event) 141{ 142 unsigned int cmp, exp; 143 144 /* 145 * Check the mantissa upper two bits are not zero, unless the 146 * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 147 * Power10: thresh_cmp is replaced by l2_l3 event select. 148 */ 149 if (cpu_has_feature(CPU_FTR_ARCH_31)) 150 return false; 151 152 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 153 exp = cmp >> 7; 154 155 if (exp && (cmp & 0x60) == 0) 156 return false; 157 158 return true; 159} 160 161static unsigned int dc_ic_rld_quad_l1_sel(u64 event) 162{ 163 unsigned int cache; 164 165 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK; 166 return cache; 167} 168 169static inline u64 isa207_find_source(u64 idx, u32 sub_idx) 170{ 171 u64 ret = PERF_MEM_NA; 172 173 switch(idx) { 174 case 0: 175 /* Nothing to do */ 176 break; 177 case 1: 178 ret = PH(LVL, L1); 179 break; 180 case 2: 181 ret = PH(LVL, L2); 182 break; 183 case 3: 184 ret = PH(LVL, L3); 185 break; 186 case 4: 187 if (sub_idx <= 1) 188 ret = PH(LVL, LOC_RAM); 189 else if (sub_idx > 1 && sub_idx <= 2) 190 ret = PH(LVL, REM_RAM1); 191 else 192 ret = PH(LVL, REM_RAM2); 193 ret |= P(SNOOP, HIT); 194 break; 195 case 5: 196 ret = PH(LVL, REM_CCE1); 197 if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4)) 198 ret |= P(SNOOP, HIT); 199 else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5)) 200 ret |= P(SNOOP, HITM); 201 break; 202 case 6: 203 ret = PH(LVL, REM_CCE2); 204 if ((sub_idx == 0) || (sub_idx == 2)) 205 ret |= P(SNOOP, HIT); 206 else if ((sub_idx == 1) || (sub_idx == 3)) 207 ret |= P(SNOOP, HITM); 208 break; 209 case 7: 210 ret = PM(LVL, L1); 211 break; 212 } 213 214 return ret; 215} 216 217void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags, 218 struct pt_regs *regs) 219{ 220 u64 idx; 221 u32 sub_idx; 222 u64 sier; 223 u64 val; 224 225 /* Skip if no SIER support */ 226 if (!(flags & PPMU_HAS_SIER)) { 227 dsrc->val = 0; 228 return; 229 } 230 231 sier = mfspr(SPRN_SIER); 232 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 233 if (val == 1 || val == 2) { 234 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT; 235 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT; 236 237 dsrc->val = isa207_find_source(idx, sub_idx); 238 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE); 239 } 240} 241 242void isa207_get_mem_weight(u64 *weight) 243{ 244 u64 mmcra = mfspr(SPRN_MMCRA); 245 u64 exp = MMCRA_THR_CTR_EXP(mmcra); 246 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra); 247 u64 sier = mfspr(SPRN_SIER); 248 u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 249 250 if (cpu_has_feature(CPU_FTR_ARCH_31)) 251 mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); 252 253 if (val == 0 || val == 7) 254 *weight = 0; 255 else 256 *weight = mantissa << (2 * exp); 257} 258 259int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) 260{ 261 unsigned int unit, pmc, cache, ebb; 262 unsigned long mask, value; 263 264 mask = value = 0; 265 266 if (!is_event_valid(event)) 267 return -1; 268 269 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 270 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 271 if (cpu_has_feature(CPU_FTR_ARCH_31)) 272 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 273 p10_EVENT_CACHE_SEL_MASK; 274 else 275 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 276 EVENT_CACHE_SEL_MASK; 277 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; 278 279 if (pmc) { 280 u64 base_event; 281 282 if (pmc > 6) 283 return -1; 284 285 /* Ignore Linux defined bits when checking event below */ 286 base_event = event & ~EVENT_LINUX_MASK; 287 288 if (pmc >= 5 && base_event != 0x500fa && 289 base_event != 0x600f4) 290 return -1; 291 292 mask |= CNST_PMC_MASK(pmc); 293 value |= CNST_PMC_VAL(pmc); 294 295 /* 296 * PMC5 and PMC6 are used to count cycles and instructions and 297 * they do not support most of the constraint bits. Add a check 298 * to exclude PMC5/6 from most of the constraints except for 299 * EBB/BHRB. 300 */ 301 if (pmc >= 5) 302 goto ebb_bhrb; 303 } 304 305 if (pmc <= 4) { 306 /* 307 * Add to number of counters in use. Note this includes events with 308 * a PMC of 0 - they still need a PMC, it's just assigned later. 309 * Don't count events on PMC 5 & 6, there is only one valid event 310 * on each of those counters, and they are handled above. 311 */ 312 mask |= CNST_NC_MASK; 313 value |= CNST_NC_VAL; 314 } 315 316 if (unit >= 6 && unit <= 9) { 317 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 318 if (unit == 6) { 319 mask |= CNST_L2L3_GROUP_MASK; 320 value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT); 321 } 322 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { 323 mask |= CNST_CACHE_GROUP_MASK; 324 value |= CNST_CACHE_GROUP_VAL(event & 0xff); 325 326 mask |= CNST_CACHE_PMC4_MASK; 327 if (pmc == 4) 328 value |= CNST_CACHE_PMC4_VAL; 329 } else if (cache & 0x7) { 330 /* 331 * L2/L3 events contain a cache selector field, which is 332 * supposed to be programmed into MMCRC. However MMCRC is only 333 * HV writable, and there is no API for guest kernels to modify 334 * it. The solution is for the hypervisor to initialise the 335 * field to zeroes, and for us to only ever allow events that 336 * have a cache selector of zero. The bank selector (bit 3) is 337 * irrelevant, as long as the rest of the value is 0. 338 */ 339 return -1; 340 } 341 342 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) { 343 mask |= CNST_L1_QUAL_MASK; 344 value |= CNST_L1_QUAL_VAL(cache); 345 } 346 347 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 348 mask |= CNST_RADIX_SCOPE_GROUP_MASK; 349 value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT); 350 } 351 352 if (is_event_marked(event)) { 353 mask |= CNST_SAMPLE_MASK; 354 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 355 } 356 357 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 358 if (event_is_threshold(event)) { 359 mask |= CNST_THRESH_CTL_SEL_MASK; 360 value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT); 361 } 362 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { 363 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { 364 mask |= CNST_THRESH_MASK; 365 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 366 } else if (event_is_threshold(event)) 367 return -1; 368 } else { 369 /* 370 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 371 * the threshold control bits are used for the match value. 372 */ 373 if (event_is_fab_match(event)) { 374 mask |= CNST_FAB_MATCH_MASK; 375 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); 376 } else { 377 if (!is_thresh_cmp_valid(event)) 378 return -1; 379 380 mask |= CNST_THRESH_MASK; 381 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 382 } 383 } 384 385ebb_bhrb: 386 if (!pmc && ebb) 387 /* EBB events must specify the PMC */ 388 return -1; 389 390 if (event & EVENT_WANTS_BHRB) { 391 if (!ebb) 392 /* Only EBB events can request BHRB */ 393 return -1; 394 395 mask |= CNST_IFM_MASK; 396 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); 397 } 398 399 /* 400 * All events must agree on EBB, either all request it or none. 401 * EBB events are pinned & exclusive, so this should never actually 402 * hit, but we leave it as a fallback in case. 403 */ 404 mask |= CNST_EBB_MASK; 405 value |= CNST_EBB_VAL(ebb); 406 407 *maskp = mask; 408 *valp = value; 409 410 return 0; 411} 412 413int isa207_compute_mmcr(u64 event[], int n_ev, 414 unsigned int hwc[], struct mmcr_regs *mmcr, 415 struct perf_event *pevents[]) 416{ 417 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; 418 unsigned long mmcr3; 419 unsigned int pmc, pmc_inuse; 420 int i; 421 422 pmc_inuse = 0; 423 424 /* First pass to count resource use */ 425 for (i = 0; i < n_ev; ++i) { 426 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 427 if (pmc) 428 pmc_inuse |= 1 << pmc; 429 } 430 431 mmcra = mmcr1 = mmcr2 = mmcr3 = 0; 432 433 /* 434 * Disable bhrb unless explicitly requested 435 * by setting MMCRA (BHRBRD) bit. 436 */ 437 if (cpu_has_feature(CPU_FTR_ARCH_31)) 438 mmcra |= MMCRA_BHRB_DISABLE; 439 440 /* Second pass: assign PMCs, set all MMCR1 fields */ 441 for (i = 0; i < n_ev; ++i) { 442 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 443 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 444 combine = combine_from_event(event[i]); 445 psel = event[i] & EVENT_PSEL_MASK; 446 447 if (!pmc) { 448 for (pmc = 1; pmc <= 4; ++pmc) { 449 if (!(pmc_inuse & (1 << pmc))) 450 break; 451 } 452 453 pmc_inuse |= 1 << pmc; 454 } 455 456 if (pmc <= 4) { 457 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); 458 mmcr1 |= combine << combine_shift(pmc); 459 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); 460 } 461 462 /* In continuous sampling mode, update SDAR on TLB miss */ 463 mmcra_sdar_mode(event[i], &mmcra); 464 465 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 466 cache = dc_ic_rld_quad_l1_sel(event[i]); 467 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 468 } else { 469 if (event[i] & EVENT_IS_L1) { 470 cache = dc_ic_rld_quad_l1_sel(event[i]); 471 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 472 } 473 } 474 475 /* Set RADIX_SCOPE_QUAL bit */ 476 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 477 val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) & 478 p10_EVENT_RADIX_SCOPE_QUAL_MASK; 479 mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT; 480 } 481 482 if (is_event_marked(event[i])) { 483 mmcra |= MMCRA_SAMPLE_ENABLE; 484 485 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 486 if (val) { 487 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; 488 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; 489 } 490 } 491 492 /* 493 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 494 * the threshold bits are used for the match value. 495 */ 496 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) { 497 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 498 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 499 } else { 500 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 501 mmcra |= val << MMCRA_THR_CTL_SHIFT; 502 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 503 mmcra |= val << MMCRA_THR_SEL_SHIFT; 504 if (!cpu_has_feature(CPU_FTR_ARCH_31)) { 505 val = (event[i] >> EVENT_THR_CMP_SHIFT) & 506 EVENT_THR_CMP_MASK; 507 mmcra |= thresh_cmp_val(val); 508 } 509 } 510 511 if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) { 512 val = (event[i] >> p10_L2L3_EVENT_SHIFT) & 513 p10_EVENT_L2L3_SEL_MASK; 514 mmcr2 |= val << p10_L2L3_SEL_SHIFT; 515 } 516 517 if (event[i] & EVENT_WANTS_BHRB) { 518 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; 519 mmcra |= val << MMCRA_IFM_SHIFT; 520 } 521 522 /* set MMCRA (BHRBRD) to 0 if there is user request for BHRB */ 523 if (cpu_has_feature(CPU_FTR_ARCH_31) && 524 (has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB))) 525 mmcra &= ~MMCRA_BHRB_DISABLE; 526 527 if (pevents[i]->attr.exclude_user) 528 mmcr2 |= MMCR2_FCP(pmc); 529 530 if (pevents[i]->attr.exclude_hv) 531 mmcr2 |= MMCR2_FCH(pmc); 532 533 if (pevents[i]->attr.exclude_kernel) { 534 if (cpu_has_feature(CPU_FTR_HVMODE)) 535 mmcr2 |= MMCR2_FCH(pmc); 536 else 537 mmcr2 |= MMCR2_FCS(pmc); 538 } 539 540 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 541 if (pmc <= 4) { 542 val = (event[i] >> p10_EVENT_MMCR3_SHIFT) & 543 p10_EVENT_MMCR3_MASK; 544 mmcr3 |= val << MMCR3_SHIFT(pmc); 545 } 546 } 547 548 hwc[i] = pmc - 1; 549 } 550 551 /* Return MMCRx values */ 552 mmcr->mmcr0 = 0; 553 554 /* pmc_inuse is 1-based */ 555 if (pmc_inuse & 2) 556 mmcr->mmcr0 = MMCR0_PMC1CE; 557 558 if (pmc_inuse & 0x7c) 559 mmcr->mmcr0 |= MMCR0_PMCjCE; 560 561 /* If we're not using PMC 5 or 6, freeze them */ 562 if (!(pmc_inuse & 0x60)) 563 mmcr->mmcr0 |= MMCR0_FC56; 564 565 /* 566 * Set mmcr0 (PMCCEXT) for p10 which 567 * will restrict access to group B registers 568 * when MMCR0 PMCC=0b00. 569 */ 570 if (cpu_has_feature(CPU_FTR_ARCH_31)) 571 mmcr->mmcr0 |= MMCR0_PMCCEXT; 572 573 mmcr->mmcr1 = mmcr1; 574 mmcr->mmcra = mmcra; 575 mmcr->mmcr2 = mmcr2; 576 mmcr->mmcr3 = mmcr3; 577 578 return 0; 579} 580 581void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr) 582{ 583 if (pmc <= 3) 584 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 585} 586 587static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size) 588{ 589 int i, j; 590 591 for (i = 0; i < size; ++i) { 592 if (event < ev_alt[i][0]) 593 break; 594 595 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j) 596 if (event == ev_alt[i][j]) 597 return i; 598 } 599 600 return -1; 601} 602 603int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags, 604 const unsigned int ev_alt[][MAX_ALT]) 605{ 606 int i, j, num_alt = 0; 607 u64 alt_event; 608 609 alt[num_alt++] = event; 610 i = find_alternative(event, ev_alt, size); 611 if (i >= 0) { 612 /* Filter out the original event, it's already in alt[0] */ 613 for (j = 0; j < MAX_ALT; ++j) { 614 alt_event = ev_alt[i][j]; 615 if (alt_event && alt_event != event) 616 alt[num_alt++] = alt_event; 617 } 618 } 619 620 if (flags & PPMU_ONLY_COUNT_RUN) { 621 /* 622 * We're only counting in RUN state, so PM_CYC is equivalent to 623 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL. 624 */ 625 j = num_alt; 626 for (i = 0; i < num_alt; ++i) { 627 switch (alt[i]) { 628 case 0x1e: /* PMC_CYC */ 629 alt[j++] = 0x600f4; /* PM_RUN_CYC */ 630 break; 631 case 0x600f4: 632 alt[j++] = 0x1e; 633 break; 634 case 0x2: /* PM_INST_CMPL */ 635 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ 636 break; 637 case 0x500fa: 638 alt[j++] = 0x2; 639 break; 640 } 641 } 642 num_alt = j; 643 } 644 645 return num_alt; 646} 647