1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
4 */
5
6#include <linux/sched.h>
7#include <linux/mm_types.h>
8#include <linux/memblock.h>
9#include <misc/cxl-base.h>
10
11#include <asm/debugfs.h>
12#include <asm/pgalloc.h>
13#include <asm/tlb.h>
14#include <asm/trace.h>
15#include <asm/powernv.h>
16#include <asm/firmware.h>
17#include <asm/ultravisor.h>
18#include <asm/kexec.h>
19
20#include <mm/mmu_decl.h>
21#include <trace/events/thp.h>
22
23unsigned long __pmd_frag_nr;
24EXPORT_SYMBOL(__pmd_frag_nr);
25unsigned long __pmd_frag_size_shift;
26EXPORT_SYMBOL(__pmd_frag_size_shift);
27
28#ifdef CONFIG_TRANSPARENT_HUGEPAGE
29/*
30 * This is called when relaxing access to a hugepage. It's also called in the page
31 * fault path when we don't hit any of the major fault cases, ie, a minor
32 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
33 * handled those two for us, we additionally deal with missing execute
34 * permission here on some processors
35 */
36int pmdp_set_access_flags(struct vm_area_struct *vma, unsigned long address,
37			  pmd_t *pmdp, pmd_t entry, int dirty)
38{
39	int changed;
40#ifdef CONFIG_DEBUG_VM
41	WARN_ON(!pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
42	assert_spin_locked(pmd_lockptr(vma->vm_mm, pmdp));
43#endif
44	changed = !pmd_same(*(pmdp), entry);
45	if (changed) {
46		/*
47		 * We can use MMU_PAGE_2M here, because only radix
48		 * path look at the psize.
49		 */
50		__ptep_set_access_flags(vma, pmdp_ptep(pmdp),
51					pmd_pte(entry), address, MMU_PAGE_2M);
52	}
53	return changed;
54}
55
56int pmdp_test_and_clear_young(struct vm_area_struct *vma,
57			      unsigned long address, pmd_t *pmdp)
58{
59	return __pmdp_test_and_clear_young(vma->vm_mm, address, pmdp);
60}
61/*
62 * set a new huge pmd. We should not be called for updating
63 * an existing pmd entry. That should go via pmd_hugepage_update.
64 */
65void set_pmd_at(struct mm_struct *mm, unsigned long addr,
66		pmd_t *pmdp, pmd_t pmd)
67{
68#ifdef CONFIG_DEBUG_VM
69	/*
70	 * Make sure hardware valid bit is not set. We don't do
71	 * tlb flush for this update.
72	 */
73
74	WARN_ON(pte_hw_valid(pmd_pte(*pmdp)) && !pte_protnone(pmd_pte(*pmdp)));
75	assert_spin_locked(pmd_lockptr(mm, pmdp));
76	WARN_ON(!(pmd_large(pmd)));
77#endif
78	trace_hugepage_set_pmd(addr, pmd_val(pmd));
79	return set_pte_at(mm, addr, pmdp_ptep(pmdp), pmd_pte(pmd));
80}
81
82static void do_nothing(void *unused)
83{
84
85}
86/*
87 * Serialize against find_current_mm_pte which does lock-less
88 * lookup in page tables with local interrupts disabled. For huge pages
89 * it casts pmd_t to pte_t. Since format of pte_t is different from
90 * pmd_t we want to prevent transit from pmd pointing to page table
91 * to pmd pointing to huge page (and back) while interrupts are disabled.
92 * We clear pmd to possibly replace it with page table pointer in
93 * different code paths. So make sure we wait for the parallel
94 * find_current_mm_pte to finish.
95 */
96void serialize_against_pte_lookup(struct mm_struct *mm)
97{
98	smp_mb();
99	smp_call_function_many(mm_cpumask(mm), do_nothing, NULL, 1);
100}
101
102/*
103 * We use this to invalidate a pmdp entry before switching from a
104 * hugepte to regular pmd entry.
105 */
106pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
107		     pmd_t *pmdp)
108{
109	unsigned long old_pmd;
110
111	old_pmd = pmd_hugepage_update(vma->vm_mm, address, pmdp, _PAGE_PRESENT, _PAGE_INVALID);
112	flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
113	return __pmd(old_pmd);
114}
115
116pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
117				   unsigned long addr, pmd_t *pmdp, int full)
118{
119	pmd_t pmd;
120	VM_BUG_ON(addr & ~HPAGE_PMD_MASK);
121	VM_BUG_ON((pmd_present(*pmdp) && !pmd_trans_huge(*pmdp) &&
122		   !pmd_devmap(*pmdp)) || !pmd_present(*pmdp));
123	pmd = pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp);
124	/*
125	 * if it not a fullmm flush, then we can possibly end up converting
126	 * this PMD pte entry to a regular level 0 PTE by a parallel page fault.
127	 * Make sure we flush the tlb in this case.
128	 */
129	if (!full)
130		flush_pmd_tlb_range(vma, addr, addr + HPAGE_PMD_SIZE);
131	return pmd;
132}
133
134static pmd_t pmd_set_protbits(pmd_t pmd, pgprot_t pgprot)
135{
136	return __pmd(pmd_val(pmd) | pgprot_val(pgprot));
137}
138
139pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot)
140{
141	unsigned long pmdv;
142
143	pmdv = (pfn << PAGE_SHIFT) & PTE_RPN_MASK;
144	return pmd_set_protbits(__pmd(pmdv), pgprot);
145}
146
147pmd_t mk_pmd(struct page *page, pgprot_t pgprot)
148{
149	return pfn_pmd(page_to_pfn(page), pgprot);
150}
151
152pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
153{
154	unsigned long pmdv;
155
156	pmdv = pmd_val(pmd);
157	pmdv &= _HPAGE_CHG_MASK;
158	return pmd_set_protbits(__pmd(pmdv), newprot);
159}
160#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
161
162/* For use by kexec */
163void mmu_cleanup_all(void)
164{
165	if (radix_enabled())
166		radix__mmu_cleanup_all();
167	else if (mmu_hash_ops.hpte_clear_all)
168		mmu_hash_ops.hpte_clear_all();
169
170	reset_sprs();
171}
172
173#ifdef CONFIG_MEMORY_HOTPLUG
174int __meminit create_section_mapping(unsigned long start, unsigned long end,
175				     int nid, pgprot_t prot)
176{
177	if (radix_enabled())
178		return radix__create_section_mapping(start, end, nid, prot);
179
180	return hash__create_section_mapping(start, end, nid, prot);
181}
182
183int __meminit remove_section_mapping(unsigned long start, unsigned long end)
184{
185	if (radix_enabled())
186		return radix__remove_section_mapping(start, end);
187
188	return hash__remove_section_mapping(start, end);
189}
190#endif /* CONFIG_MEMORY_HOTPLUG */
191
192void __init mmu_partition_table_init(void)
193{
194	unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
195	unsigned long ptcr;
196
197	BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 36), "Partition table size too large.");
198	/* Initialize the Partition Table with no entries */
199	partition_tb = memblock_alloc(patb_size, patb_size);
200	if (!partition_tb)
201		panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
202		      __func__, patb_size, patb_size);
203
204	/*
205	 * update partition table control register,
206	 * 64 K size.
207	 */
208	ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12);
209	set_ptcr_when_no_uv(ptcr);
210	powernv_set_nmmu_ptcr(ptcr);
211}
212
213static void flush_partition(unsigned int lpid, bool radix)
214{
215	if (radix) {
216		radix__flush_all_lpid(lpid);
217		radix__flush_all_lpid_guest(lpid);
218	} else {
219		asm volatile("ptesync" : : : "memory");
220		asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
221			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
222		/* do we need fixup here ?*/
223		asm volatile("eieio; tlbsync; ptesync" : : : "memory");
224		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
225	}
226}
227
228void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
229				  unsigned long dw1, bool flush)
230{
231	unsigned long old = be64_to_cpu(partition_tb[lpid].patb0);
232
233	/*
234	 * When ultravisor is enabled, the partition table is stored in secure
235	 * memory and can only be accessed doing an ultravisor call. However, we
236	 * maintain a copy of the partition table in normal memory to allow Nest
237	 * MMU translations to occur (for normal VMs).
238	 *
239	 * Therefore, here we always update partition_tb, regardless of whether
240	 * we are running under an ultravisor or not.
241	 */
242	partition_tb[lpid].patb0 = cpu_to_be64(dw0);
243	partition_tb[lpid].patb1 = cpu_to_be64(dw1);
244
245	/*
246	 * If ultravisor is enabled, we do an ultravisor call to register the
247	 * partition table entry (PATE), which also do a global flush of TLBs
248	 * and partition table caches for the lpid. Otherwise, just do the
249	 * flush. The type of flush (hash or radix) depends on what the previous
250	 * use of the partition ID was, not the new use.
251	 */
252	if (firmware_has_feature(FW_FEATURE_ULTRAVISOR)) {
253		uv_register_pate(lpid, dw0, dw1);
254		pr_info("PATE registered by ultravisor: dw0 = 0x%lx, dw1 = 0x%lx\n",
255			dw0, dw1);
256	} else if (flush) {
257		/*
258		 * Boot does not need to flush, because MMU is off and each
259		 * CPU does a tlbiel_all() before switching them on, which
260		 * flushes everything.
261		 */
262		flush_partition(lpid, (old & PATB_HR));
263	}
264}
265EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry);
266
267static pmd_t *get_pmd_from_cache(struct mm_struct *mm)
268{
269	void *pmd_frag, *ret;
270
271	if (PMD_FRAG_NR == 1)
272		return NULL;
273
274	spin_lock(&mm->page_table_lock);
275	ret = mm->context.pmd_frag;
276	if (ret) {
277		pmd_frag = ret + PMD_FRAG_SIZE;
278		/*
279		 * If we have taken up all the fragments mark PTE page NULL
280		 */
281		if (((unsigned long)pmd_frag & ~PAGE_MASK) == 0)
282			pmd_frag = NULL;
283		mm->context.pmd_frag = pmd_frag;
284	}
285	spin_unlock(&mm->page_table_lock);
286	return (pmd_t *)ret;
287}
288
289static pmd_t *__alloc_for_pmdcache(struct mm_struct *mm)
290{
291	void *ret = NULL;
292	struct page *page;
293	gfp_t gfp = GFP_KERNEL_ACCOUNT | __GFP_ZERO;
294
295	if (mm == &init_mm)
296		gfp &= ~__GFP_ACCOUNT;
297	page = alloc_page(gfp);
298	if (!page)
299		return NULL;
300	if (!pgtable_pmd_page_ctor(page)) {
301		__free_pages(page, 0);
302		return NULL;
303	}
304
305	atomic_set(&page->pt_frag_refcount, 1);
306
307	ret = page_address(page);
308	/*
309	 * if we support only one fragment just return the
310	 * allocated page.
311	 */
312	if (PMD_FRAG_NR == 1)
313		return ret;
314
315	spin_lock(&mm->page_table_lock);
316	/*
317	 * If we find pgtable_page set, we return
318	 * the allocated page with single fragement
319	 * count.
320	 */
321	if (likely(!mm->context.pmd_frag)) {
322		atomic_set(&page->pt_frag_refcount, PMD_FRAG_NR);
323		mm->context.pmd_frag = ret + PMD_FRAG_SIZE;
324	}
325	spin_unlock(&mm->page_table_lock);
326
327	return (pmd_t *)ret;
328}
329
330pmd_t *pmd_fragment_alloc(struct mm_struct *mm, unsigned long vmaddr)
331{
332	pmd_t *pmd;
333
334	pmd = get_pmd_from_cache(mm);
335	if (pmd)
336		return pmd;
337
338	return __alloc_for_pmdcache(mm);
339}
340
341void pmd_fragment_free(unsigned long *pmd)
342{
343	struct page *page = virt_to_page(pmd);
344
345	if (PageReserved(page))
346		return free_reserved_page(page);
347
348	BUG_ON(atomic_read(&page->pt_frag_refcount) <= 0);
349	if (atomic_dec_and_test(&page->pt_frag_refcount)) {
350		pgtable_pmd_page_dtor(page);
351		__free_page(page);
352	}
353}
354
355static inline void pgtable_free(void *table, int index)
356{
357	switch (index) {
358	case PTE_INDEX:
359		pte_fragment_free(table, 0);
360		break;
361	case PMD_INDEX:
362		pmd_fragment_free(table);
363		break;
364	case PUD_INDEX:
365		__pud_free(table);
366		break;
367#if defined(CONFIG_PPC_4K_PAGES) && defined(CONFIG_HUGETLB_PAGE)
368		/* 16M hugepd directory at pud level */
369	case HTLB_16M_INDEX:
370		BUILD_BUG_ON(H_16M_CACHE_INDEX <= 0);
371		kmem_cache_free(PGT_CACHE(H_16M_CACHE_INDEX), table);
372		break;
373		/* 16G hugepd directory at the pgd level */
374	case HTLB_16G_INDEX:
375		BUILD_BUG_ON(H_16G_CACHE_INDEX <= 0);
376		kmem_cache_free(PGT_CACHE(H_16G_CACHE_INDEX), table);
377		break;
378#endif
379		/* We don't free pgd table via RCU callback */
380	default:
381		BUG();
382	}
383}
384
385void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int index)
386{
387	unsigned long pgf = (unsigned long)table;
388
389	BUG_ON(index > MAX_PGTABLE_INDEX_SIZE);
390	pgf |= index;
391	tlb_remove_table(tlb, (void *)pgf);
392}
393
394void __tlb_remove_table(void *_table)
395{
396	void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
397	unsigned int index = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
398
399	return pgtable_free(table, index);
400}
401
402#ifdef CONFIG_PROC_FS
403atomic_long_t direct_pages_count[MMU_PAGE_COUNT];
404
405void arch_report_meminfo(struct seq_file *m)
406{
407	/*
408	 * Hash maps the memory with one size mmu_linear_psize.
409	 * So don't bother to print these on hash
410	 */
411	if (!radix_enabled())
412		return;
413	seq_printf(m, "DirectMap4k:    %8lu kB\n",
414		   atomic_long_read(&direct_pages_count[MMU_PAGE_4K]) << 2);
415	seq_printf(m, "DirectMap64k:    %8lu kB\n",
416		   atomic_long_read(&direct_pages_count[MMU_PAGE_64K]) << 6);
417	seq_printf(m, "DirectMap2M:    %8lu kB\n",
418		   atomic_long_read(&direct_pages_count[MMU_PAGE_2M]) << 11);
419	seq_printf(m, "DirectMap1G:    %8lu kB\n",
420		   atomic_long_read(&direct_pages_count[MMU_PAGE_1G]) << 20);
421}
422#endif /* CONFIG_PROC_FS */
423
424pte_t ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr,
425			     pte_t *ptep)
426{
427	unsigned long pte_val;
428
429	/*
430	 * Clear the _PAGE_PRESENT so that no hardware parallel update is
431	 * possible. Also keep the pte_present true so that we don't take
432	 * wrong fault.
433	 */
434	pte_val = pte_update(vma->vm_mm, addr, ptep, _PAGE_PRESENT, _PAGE_INVALID, 0);
435
436	return __pte(pte_val);
437
438}
439
440void ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr,
441			     pte_t *ptep, pte_t old_pte, pte_t pte)
442{
443	if (radix_enabled())
444		return radix__ptep_modify_prot_commit(vma, addr,
445						      ptep, old_pte, pte);
446	set_pte_at(vma->vm_mm, addr, ptep, pte);
447}
448
449#ifdef CONFIG_TRANSPARENT_HUGEPAGE
450/*
451 * For hash translation mode, we use the deposited table to store hash slot
452 * information and they are stored at PTRS_PER_PMD offset from related pmd
453 * location. Hence a pmd move requires deposit and withdraw.
454 *
455 * For radix translation with split pmd ptl, we store the deposited table in the
456 * pmd page. Hence if we have different pmd page we need to withdraw during pmd
457 * move.
458 *
459 * With hash we use deposited table always irrespective of anon or not.
460 * With radix we use deposited table only for anonymous mapping.
461 */
462int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
463			   struct spinlock *old_pmd_ptl,
464			   struct vm_area_struct *vma)
465{
466	if (radix_enabled())
467		return (new_pmd_ptl != old_pmd_ptl) && vma_is_anonymous(vma);
468
469	return true;
470}
471#endif
472
473/*
474 * Does the CPU support tlbie?
475 */
476bool tlbie_capable __read_mostly = true;
477EXPORT_SYMBOL(tlbie_capable);
478
479/*
480 * Should tlbie be used for management of CPU TLBs, for kernel and process
481 * address spaces? tlbie may still be used for nMMU accelerators, and for KVM
482 * guest address spaces.
483 */
484bool tlbie_enabled __read_mostly = true;
485
486static int __init setup_disable_tlbie(char *str)
487{
488	if (!radix_enabled()) {
489		pr_err("disable_tlbie: Unable to disable TLBIE with Hash MMU.\n");
490		return 1;
491	}
492
493	tlbie_capable = false;
494	tlbie_enabled = false;
495
496        return 1;
497}
498__setup("disable_tlbie", setup_disable_tlbie);
499
500static int __init pgtable_debugfs_setup(void)
501{
502	if (!tlbie_capable)
503		return 0;
504
505	/*
506	 * There is no locking vs tlb flushing when changing this value.
507	 * The tlb flushers will see one value or another, and use either
508	 * tlbie or tlbiel with IPIs. In both cases the TLBs will be
509	 * invalidated as expected.
510	 */
511	debugfs_create_bool("tlbie_enabled", 0600,
512			powerpc_debugfs_root,
513			&tlbie_enabled);
514
515	return 0;
516}
517arch_initcall(pgtable_debugfs_setup);
518