18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 48c2ecf20Sopenharmony_ci * Rewrite, cleanup: 58c2ecf20Sopenharmony_ci * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef _ASM_POWERPC_TCE_H 98c2ecf20Sopenharmony_ci#define _ASM_POWERPC_TCE_H 108c2ecf20Sopenharmony_ci#ifdef __KERNEL__ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <asm/iommu.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci/* 158c2ecf20Sopenharmony_ci * Tces come in two formats, one for the virtual bus and a different 168c2ecf20Sopenharmony_ci * format for PCI. PCI TCEs can have hardware or software maintianed 178c2ecf20Sopenharmony_ci * coherency. 188c2ecf20Sopenharmony_ci */ 198c2ecf20Sopenharmony_ci#define TCE_VB 0 208c2ecf20Sopenharmony_ci#define TCE_PCI 1 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci/* TCE page size is 4096 bytes (1 << 12) */ 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci#define TCE_SHIFT 12 258c2ecf20Sopenharmony_ci#define TCE_PAGE_SIZE (1 << TCE_SHIFT) 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci#define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */ 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci#define TCE_RPN_MASK 0xfffffffffful /* 40-bit RPN (4K pages) */ 308c2ecf20Sopenharmony_ci#define TCE_RPN_SHIFT 12 318c2ecf20Sopenharmony_ci#define TCE_VALID 0x800 /* TCE valid */ 328c2ecf20Sopenharmony_ci#define TCE_ALLIO 0x400 /* TCE valid for all lpars */ 338c2ecf20Sopenharmony_ci#define TCE_PCI_WRITE 0x2 /* write from PCI allowed */ 348c2ecf20Sopenharmony_ci#define TCE_PCI_READ 0x1 /* read from PCI allowed */ 358c2ecf20Sopenharmony_ci#define TCE_VB_WRITE 0x1 /* write from VB allowed */ 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci#endif /* __KERNEL__ */ 388c2ecf20Sopenharmony_ci#endif /* _ASM_POWERPC_TCE_H */ 39