1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * smp.h: PowerPC-specific SMP code.
4 *
5 * Original was a copy of sparc smp.h.  Now heavily modified
6 * for PPC.
7 *
8 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
9 * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
10 */
11
12#ifndef _ASM_POWERPC_SMP_H
13#define _ASM_POWERPC_SMP_H
14#ifdef __KERNEL__
15
16#include <linux/threads.h>
17#include <linux/cpumask.h>
18#include <linux/kernel.h>
19#include <linux/irqreturn.h>
20
21#ifndef __ASSEMBLY__
22
23#ifdef CONFIG_PPC64
24#include <asm/paca.h>
25#endif
26#include <asm/percpu.h>
27
28extern int boot_cpuid;
29extern int spinning_secondaries;
30extern u32 *cpu_to_phys_id;
31extern bool coregroup_enabled;
32
33extern int cpu_to_chip_id(int cpu);
34
35#ifdef CONFIG_SMP
36
37struct smp_ops_t {
38	void  (*message_pass)(int cpu, int msg);
39#ifdef CONFIG_PPC_SMP_MUXED_IPI
40	void  (*cause_ipi)(int cpu);
41#endif
42	int   (*cause_nmi_ipi)(int cpu);
43	void  (*probe)(void);
44	int   (*kick_cpu)(int nr);
45	int   (*prepare_cpu)(int nr);
46	void  (*setup_cpu)(int nr);
47	void  (*bringup_done)(void);
48	void  (*take_timebase)(void);
49	void  (*give_timebase)(void);
50	int   (*cpu_disable)(void);
51	void  (*cpu_die)(unsigned int nr);
52	int   (*cpu_bootable)(unsigned int nr);
53#ifdef CONFIG_HOTPLUG_CPU
54	void  (*cpu_offline_self)(void);
55#endif
56};
57
58extern int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us);
59extern int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us);
60extern void smp_send_debugger_break(void);
61extern void start_secondary_resume(void);
62extern void smp_generic_give_timebase(void);
63extern void smp_generic_take_timebase(void);
64
65DECLARE_PER_CPU(unsigned int, cpu_pvr);
66
67#ifdef CONFIG_HOTPLUG_CPU
68int generic_cpu_disable(void);
69void generic_cpu_die(unsigned int cpu);
70void generic_set_cpu_dead(unsigned int cpu);
71void generic_set_cpu_up(unsigned int cpu);
72int generic_check_cpu_restart(unsigned int cpu);
73int is_cpu_dead(unsigned int cpu);
74#else
75#define generic_set_cpu_up(i)	do { } while (0)
76#endif
77
78#ifdef CONFIG_PPC64
79#define raw_smp_processor_id()	(local_paca->paca_index)
80#define hard_smp_processor_id() (get_paca()->hw_cpu_id)
81#else
82/* 32-bit */
83extern int smp_hw_index[];
84
85/*
86 * This is particularly ugly: it appears we can't actually get the definition
87 * of task_struct here, but we need access to the CPU this task is running on.
88 * Instead of using task_struct we're using _TASK_CPU which is extracted from
89 * asm-offsets.h by kbuild to get the current processor ID.
90 *
91 * This also needs to be safeguarded when building asm-offsets.s because at
92 * that time _TASK_CPU is not defined yet. It could have been guarded by
93 * _TASK_CPU itself, but we want the build to fail if _TASK_CPU is missing
94 * when building something else than asm-offsets.s
95 */
96#ifdef GENERATING_ASM_OFFSETS
97#define raw_smp_processor_id()		(0)
98#else
99#define raw_smp_processor_id()		(*(unsigned int *)((void *)current + _TASK_CPU))
100#endif
101#define hard_smp_processor_id() 	(smp_hw_index[smp_processor_id()])
102
103static inline int get_hard_smp_processor_id(int cpu)
104{
105	return smp_hw_index[cpu];
106}
107
108static inline void set_hard_smp_processor_id(int cpu, int phys)
109{
110	smp_hw_index[cpu] = phys;
111}
112#endif
113
114DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map);
115DECLARE_PER_CPU(cpumask_var_t, cpu_l2_cache_map);
116DECLARE_PER_CPU(cpumask_var_t, cpu_core_map);
117DECLARE_PER_CPU(cpumask_var_t, cpu_smallcore_map);
118
119static inline struct cpumask *cpu_sibling_mask(int cpu)
120{
121	return per_cpu(cpu_sibling_map, cpu);
122}
123
124static inline struct cpumask *cpu_core_mask(int cpu)
125{
126	return per_cpu(cpu_core_map, cpu);
127}
128
129static inline struct cpumask *cpu_l2_cache_mask(int cpu)
130{
131	return per_cpu(cpu_l2_cache_map, cpu);
132}
133
134static inline struct cpumask *cpu_smallcore_mask(int cpu)
135{
136	return per_cpu(cpu_smallcore_map, cpu);
137}
138
139extern int cpu_to_core_id(int cpu);
140
141extern bool has_big_cores;
142
143#define cpu_smt_mask cpu_smt_mask
144#ifdef CONFIG_SCHED_SMT
145static inline const struct cpumask *cpu_smt_mask(int cpu)
146{
147	if (has_big_cores)
148		return per_cpu(cpu_smallcore_map, cpu);
149
150	return per_cpu(cpu_sibling_map, cpu);
151}
152#endif /* CONFIG_SCHED_SMT */
153
154/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
155 *
156 * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up
157 * in /proc/interrupts will be wrong!!! --Troy */
158#define PPC_MSG_CALL_FUNCTION	0
159#define PPC_MSG_RESCHEDULE	1
160#define PPC_MSG_TICK_BROADCAST	2
161#define PPC_MSG_NMI_IPI		3
162
163/* This is only used by the powernv kernel */
164#define PPC_MSG_RM_HOST_ACTION	4
165
166#define NMI_IPI_ALL_OTHERS		-2
167
168#ifdef CONFIG_NMI_IPI
169extern int smp_handle_nmi_ipi(struct pt_regs *regs);
170#else
171static inline int smp_handle_nmi_ipi(struct pt_regs *regs) { return 0; }
172#endif
173
174/* for irq controllers that have dedicated ipis per message (4) */
175extern int smp_request_message_ipi(int virq, int message);
176extern const char *smp_ipi_name[];
177
178/* for irq controllers with only a single ipi */
179extern void smp_muxed_ipi_message_pass(int cpu, int msg);
180extern void smp_muxed_ipi_set_message(int cpu, int msg);
181extern irqreturn_t smp_ipi_demux(void);
182extern irqreturn_t smp_ipi_demux_relaxed(void);
183
184void smp_init_pSeries(void);
185void smp_init_cell(void);
186void smp_setup_cpu_maps(void);
187
188extern int __cpu_disable(void);
189extern void __cpu_die(unsigned int cpu);
190
191#else
192/* for UP */
193#define hard_smp_processor_id()		get_hard_smp_processor_id(0)
194#define smp_setup_cpu_maps()
195static inline void inhibit_secondary_onlining(void) {}
196static inline void uninhibit_secondary_onlining(void) {}
197static inline const struct cpumask *cpu_sibling_mask(int cpu)
198{
199	return cpumask_of(cpu);
200}
201
202static inline const struct cpumask *cpu_smallcore_mask(int cpu)
203{
204	return cpumask_of(cpu);
205}
206
207#endif /* CONFIG_SMP */
208
209#ifdef CONFIG_PPC64
210static inline int get_hard_smp_processor_id(int cpu)
211{
212	return paca_ptrs[cpu]->hw_cpu_id;
213}
214
215static inline void set_hard_smp_processor_id(int cpu, int phys)
216{
217	paca_ptrs[cpu]->hw_cpu_id = phys;
218}
219#else
220/* 32-bit */
221#ifndef CONFIG_SMP
222extern int boot_cpuid_phys;
223static inline int get_hard_smp_processor_id(int cpu)
224{
225	return boot_cpuid_phys;
226}
227
228static inline void set_hard_smp_processor_id(int cpu, int phys)
229{
230	boot_cpuid_phys = phys;
231}
232#endif /* !CONFIG_SMP */
233#endif /* !CONFIG_PPC64 */
234
235#if defined(CONFIG_PPC64) && (defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE))
236extern void smp_release_cpus(void);
237#else
238static inline void smp_release_cpus(void) { };
239#endif
240
241extern int smt_enabled_at_boot;
242
243extern void smp_mpic_probe(void);
244extern void smp_mpic_setup_cpu(int cpu);
245extern int smp_generic_kick_cpu(int nr);
246extern int smp_generic_cpu_bootable(unsigned int nr);
247
248
249extern void smp_generic_give_timebase(void);
250extern void smp_generic_take_timebase(void);
251
252extern struct smp_ops_t *smp_ops;
253
254extern void arch_send_call_function_single_ipi(int cpu);
255extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
256
257/* Definitions relative to the secondary CPU spin loop
258 * and entry point. Not all of them exist on both 32 and
259 * 64-bit but defining them all here doesn't harm
260 */
261extern void generic_secondary_smp_init(void);
262extern unsigned long __secondary_hold_spinloop;
263extern unsigned long __secondary_hold_acknowledge;
264extern char __secondary_hold;
265extern unsigned int booting_thread_hwid;
266
267extern void __early_start(void);
268#endif /* __ASSEMBLY__ */
269
270#endif /* __KERNEL__ */
271#endif /* _ASM_POWERPC_SMP_H) */
272