1/* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4#ifndef _ASM_POWERPC_PPC_ASM_H 5#define _ASM_POWERPC_PPC_ASM_H 6 7#include <linux/stringify.h> 8#include <asm/asm-compat.h> 9#include <asm/processor.h> 10#include <asm/ppc-opcode.h> 11#include <asm/firmware.h> 12#include <asm/feature-fixups.h> 13 14#ifdef __ASSEMBLY__ 15 16#define SZL (BITS_PER_LONG/8) 17 18/* 19 * Stuff for accurate CPU time accounting. 20 * These macros handle transitions between user and system state 21 * in exception entry and exit and accumulate time to the 22 * user_time and system_time fields in the paca. 23 */ 24 25#ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 26#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) 27#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) 28#define ACCOUNT_STOLEN_TIME 29#else 30#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) \ 31 MFTB(ra); /* get timebase */ \ 32 PPC_LL rb, ACCOUNT_STARTTIME_USER(ptr); \ 33 PPC_STL ra, ACCOUNT_STARTTIME(ptr); \ 34 subf rb,rb,ra; /* subtract start value */ \ 35 PPC_LL ra, ACCOUNT_USER_TIME(ptr); \ 36 add ra,ra,rb; /* add on to user time */ \ 37 PPC_STL ra, ACCOUNT_USER_TIME(ptr); \ 38 39#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) \ 40 MFTB(ra); /* get timebase */ \ 41 PPC_LL rb, ACCOUNT_STARTTIME(ptr); \ 42 PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr); \ 43 subf rb,rb,ra; /* subtract start value */ \ 44 PPC_LL ra, ACCOUNT_SYSTEM_TIME(ptr); \ 45 add ra,ra,rb; /* add on to system time */ \ 46 PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr) 47 48#ifdef CONFIG_PPC_SPLPAR 49#define ACCOUNT_STOLEN_TIME \ 50BEGIN_FW_FTR_SECTION; \ 51 beq 33f; \ 52 /* from user - see if there are any DTL entries to process */ \ 53 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 54 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 55 addi r10,r10,LPPACA_DTLIDX; \ 56 LDX_BE r10,0,r10; /* get log write index */ \ 57 cmpd cr1,r11,r10; \ 58 beq+ cr1,33f; \ 59 bl accumulate_stolen_time; \ 60 ld r12,_MSR(r1); \ 61 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 6233: \ 63END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 64 65#else /* CONFIG_PPC_SPLPAR */ 66#define ACCOUNT_STOLEN_TIME 67 68#endif /* CONFIG_PPC_SPLPAR */ 69 70#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 71 72/* 73 * Macros for storing registers into and loading registers from 74 * exception frames. 75 */ 76#ifdef __powerpc64__ 77#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 78#define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 79#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 80#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 81#else 82#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 83#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 84#define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base) 85#define REST_NVGPRS(base) lmw 13, GPR0+4*13(base) 86#endif 87 88#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 89#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 90#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 91#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 92#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 93#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 94#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 95#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 96 97#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 98#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 99#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 100#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 101#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 102#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 103#define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 104#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 105#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 106#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 107#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 108#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 109 110#define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 111#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 112#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 113#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 114#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 115#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 116#define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 117#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 118#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 119#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 120#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 121#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 122 123#ifdef __BIG_ENDIAN__ 124#define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 125#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 126#else 127#define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 128 STXVD2X(n,b,base); \ 129 XXSWAPD(n,n) 130 131#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 132 XXSWAPD(n,n) 133#endif 134/* Save the lower 32 VSRs in the thread VSR region */ 135#define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 136#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 137#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 138#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 139#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 140#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 141#define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 142#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 143#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 144#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 145#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 146#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 147 148/* 149 * b = base register for addressing, o = base offset from register of 1st EVR 150 * n = first EVR, s = scratch 151 */ 152#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 153#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 154#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 155#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 156#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 157#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 158#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 159#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 160#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 161#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 162#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 163#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 164 165/* Macros to adjust thread priority for hardware multithreading */ 166#define HMT_VERY_LOW or 31,31,31 # very low priority 167#define HMT_LOW or 1,1,1 168#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 169#define HMT_MEDIUM or 2,2,2 170#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 171#define HMT_HIGH or 3,3,3 172#define HMT_EXTRA_HIGH or 7,7,7 # power7 only 173 174#ifdef CONFIG_PPC64 175#define ULONG_SIZE 8 176#else 177#define ULONG_SIZE 4 178#endif 179#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 180#define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 181 182#ifdef __KERNEL__ 183#ifdef CONFIG_PPC64 184 185#define STACKFRAMESIZE 256 186#define __STK_REG(i) (112 + ((i)-14)*8) 187#define STK_REG(i) __STK_REG(__REG_##i) 188 189#ifdef PPC64_ELF_ABI_v2 190#define STK_GOT 24 191#define __STK_PARAM(i) (32 + ((i)-3)*8) 192#else 193#define STK_GOT 40 194#define __STK_PARAM(i) (48 + ((i)-3)*8) 195#endif 196#define STK_PARAM(i) __STK_PARAM(__REG_##i) 197 198#ifdef PPC64_ELF_ABI_v2 199 200#define _GLOBAL(name) \ 201 .align 2 ; \ 202 .type name,@function; \ 203 .globl name; \ 204name: 205 206#define _GLOBAL_TOC(name) \ 207 .align 2 ; \ 208 .type name,@function; \ 209 .globl name; \ 210name: \ 2110: addis r2,r12,(.TOC.-0b)@ha; \ 212 addi r2,r2,(.TOC.-0b)@l; \ 213 .localentry name,.-name 214 215#define DOTSYM(a) a 216 217#else 218 219#define XGLUE(a,b) a##b 220#define GLUE(a,b) XGLUE(a,b) 221 222#define _GLOBAL(name) \ 223 .align 2 ; \ 224 .globl name; \ 225 .globl GLUE(.,name); \ 226 .pushsection ".opd","aw"; \ 227name: \ 228 .quad GLUE(.,name); \ 229 .quad .TOC.@tocbase; \ 230 .quad 0; \ 231 .popsection; \ 232 .type GLUE(.,name),@function; \ 233GLUE(.,name): 234 235#define _GLOBAL_TOC(name) _GLOBAL(name) 236 237#define DOTSYM(a) GLUE(.,a) 238 239#endif 240 241#else /* 32-bit */ 242 243#define _ENTRY(n) \ 244 .globl n; \ 245n: 246 247#define _GLOBAL(n) \ 248 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 249 .globl n; \ 250n: 251 252#define _GLOBAL_TOC(name) _GLOBAL(name) 253 254#endif 255 256/* 257 * __kprobes (the C annotation) puts the symbol into the .kprobes.text 258 * section, which gets emitted at the end of regular text. 259 * 260 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to 261 * a blacklist. The former is for core kprobe functions/data, the 262 * latter is for those that incdentially must be excluded from probing 263 * and allows them to be linked at more optimal location within text. 264 */ 265#ifdef CONFIG_KPROBES 266#define _ASM_NOKPROBE_SYMBOL(entry) \ 267 .pushsection "_kprobe_blacklist","aw"; \ 268 PPC_LONG (entry) ; \ 269 .popsection 270#else 271#define _ASM_NOKPROBE_SYMBOL(entry) 272#endif 273 274#define FUNC_START(name) _GLOBAL(name) 275#define FUNC_END(name) 276 277/* 278 * LOAD_REG_IMMEDIATE(rn, expr) 279 * Loads the value of the constant expression 'expr' into register 'rn' 280 * using immediate instructions only. Use this when it's important not 281 * to reference other data (i.e. on ppc64 when the TOC pointer is not 282 * valid) and when 'expr' is a constant or absolute address. 283 * 284 * LOAD_REG_ADDR(rn, name) 285 * Loads the address of label 'name' into register 'rn'. Use this when 286 * you don't particularly need immediate instructions only, but you need 287 * the whole address in one register (e.g. it's a structure address and 288 * you want to access various offsets within it). On ppc32 this is 289 * identical to LOAD_REG_IMMEDIATE. 290 * 291 * LOAD_REG_ADDR_PIC(rn, name) 292 * Loads the address of label 'name' into register 'run'. Use this when 293 * the kernel doesn't run at the linked or relocated address. Please 294 * note that this macro will clobber the lr register. 295 * 296 * LOAD_REG_ADDRBASE(rn, name) 297 * ADDROFF(name) 298 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 299 * register 'rn'. ADDROFF(name) returns the remainder of the address as 300 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 301 * in size, so is suitable for use directly as an offset in load and store 302 * instructions. Use this when loading/storing a single word or less as: 303 * LOAD_REG_ADDRBASE(rX, name) 304 * ld rY,ADDROFF(name)(rX) 305 */ 306 307/* Be careful, this will clobber the lr register. */ 308#define LOAD_REG_ADDR_PIC(reg, name) \ 309 bl 0f; \ 3100: mflr reg; \ 311 addis reg,reg,(name - 0b)@ha; \ 312 addi reg,reg,(name - 0b)@l; 313 314#if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH) 315#define __AS_ATHIGH high 316#else 317#define __AS_ATHIGH h 318#endif 319 320.macro __LOAD_REG_IMMEDIATE_32 r, x 321 .if (\x) >= 0x8000 || (\x) < -0x8000 322 lis \r, (\x)@__AS_ATHIGH 323 .if (\x) & 0xffff != 0 324 ori \r, \r, (\x)@l 325 .endif 326 .else 327 li \r, (\x)@l 328 .endif 329.endm 330 331.macro __LOAD_REG_IMMEDIATE r, x 332 .if (\x) >= 0x80000000 || (\x) < -0x80000000 333 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32 334 sldi \r, \r, 32 335 .if (\x) & 0xffff0000 != 0 336 oris \r, \r, (\x)@__AS_ATHIGH 337 .endif 338 .if (\x) & 0xffff != 0 339 ori \r, \r, (\x)@l 340 .endif 341 .else 342 __LOAD_REG_IMMEDIATE_32 \r, \x 343 .endif 344.endm 345 346#ifdef __powerpc64__ 347 348#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr 349 350#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ 351 lis tmp, (expr)@highest; \ 352 lis reg, (expr)@__AS_ATHIGH; \ 353 ori tmp, tmp, (expr)@higher; \ 354 ori reg, reg, (expr)@l; \ 355 rldimi reg, tmp, 32, 0 356 357#define LOAD_REG_ADDR(reg,name) \ 358 ld reg,name@got(r2) 359 360#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 361#define ADDROFF(name) 0 362 363/* offsets for stack frame layout */ 364#define LRSAVE 16 365 366#else /* 32-bit */ 367 368#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr 369 370#define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ 371 lis reg,(expr)@ha; \ 372 addi reg,reg,(expr)@l; 373 374#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) 375 376#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 377#define ADDROFF(name) name@l 378 379/* offsets for stack frame layout */ 380#define LRSAVE 4 381 382#endif 383 384/* various errata or part fixups */ 385#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 386#define MFTB(dest) \ 38790: mfspr dest, SPRN_TBRL; \ 388BEGIN_FTR_SECTION_NESTED(96); \ 389 cmpwi dest,0; \ 390 beq- 90b; \ 391END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 392#else 393#define MFTB(dest) MFTBL(dest) 394#endif 395 396#ifdef CONFIG_PPC_8xx 397#define MFTBL(dest) mftb dest 398#define MFTBU(dest) mftbu dest 399#else 400#define MFTBL(dest) mfspr dest, SPRN_TBRL 401#define MFTBU(dest) mfspr dest, SPRN_TBRU 402#endif 403 404#ifndef CONFIG_SMP 405#define TLBSYNC 406#else 407#define TLBSYNC tlbsync; sync 408#endif 409 410#ifdef CONFIG_PPC64 411#define MTOCRF(FXM, RS) \ 412 BEGIN_FTR_SECTION_NESTED(848); \ 413 mtcrf (FXM), RS; \ 414 FTR_SECTION_ELSE_NESTED(848); \ 415 mtocrf (FXM), RS; \ 416 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 417#endif 418 419/* 420 * This instruction is not implemented on the PPC 603 or 601; however, on 421 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 422 * All of these instructions exist in the 8xx, they have magical powers, 423 * and they must be used. 424 */ 425 426#if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx) 427#define tlbia \ 428 li r4,1024; \ 429 mtctr r4; \ 430 lis r4,KERNELBASE@h; \ 431 .machine push; \ 432 .machine "power4"; \ 4330: tlbie r4; \ 434 .machine pop; \ 435 addi r4,r4,0x1000; \ 436 bdnz 0b 437#endif 438 439 440#ifdef CONFIG_IBM440EP_ERR42 441#define PPC440EP_ERR42 isync 442#else 443#define PPC440EP_ERR42 444#endif 445 446/* The following stops all load and store data streams associated with stream 447 * ID (ie. streams created explicitly). The embedded and server mnemonics for 448 * dcbt are different so this must only be used for server. 449 */ 450#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \ 451 lis scratch,0x60000000@h; \ 452 dcbt 0,scratch,0b01010 453 454/* 455 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 456 * keep the address intact to be compatible with code shared with 457 * 32-bit classic. 458 * 459 * On the other hand, I find it useful to have them behave as expected 460 * by their name (ie always do the addition) on 64-bit BookE 461 */ 462#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 463#define toreal(rd) 464#define fromreal(rd) 465 466/* 467 * We use addis to ensure compatibility with the "classic" ppc versions of 468 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 469 * converting the address in r0, and so this version has to do that too 470 * (i.e. set register rd to 0 when rs == 0). 471 */ 472#define tophys(rd,rs) \ 473 addis rd,rs,0 474 475#define tovirt(rd,rs) \ 476 addis rd,rs,0 477 478#elif defined(CONFIG_PPC64) 479#define toreal(rd) /* we can access c000... in real mode */ 480#define fromreal(rd) 481 482#define tophys(rd,rs) \ 483 clrldi rd,rs,2 484 485#define tovirt(rd,rs) \ 486 rotldi rd,rs,16; \ 487 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 488 rotldi rd,rd,48 489#else 490#define toreal(rd) tophys(rd,rd) 491#define fromreal(rd) tovirt(rd,rd) 492 493#define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h 494#define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h 495#endif 496 497#ifdef CONFIG_PPC_BOOK3S_64 498#define RFI rfid 499#define MTMSRD(r) mtmsrd r 500#define MTMSR_EERI(reg) mtmsrd reg,1 501#else 502#ifndef CONFIG_40x 503#define RFI rfi 504#else 505#define RFI rfi; b . /* Prevent prefetch past rfi */ 506#endif 507#define MTMSRD(r) mtmsr r 508#define MTMSR_EERI(reg) mtmsr reg 509#endif 510 511#endif /* __KERNEL__ */ 512 513/* The boring bits... */ 514 515/* Condition Register Bit Fields */ 516 517#define cr0 0 518#define cr1 1 519#define cr2 2 520#define cr3 3 521#define cr4 4 522#define cr5 5 523#define cr6 6 524#define cr7 7 525 526 527/* 528 * General Purpose Registers (GPRs) 529 * 530 * The lower case r0-r31 should be used in preference to the upper 531 * case R0-R31 as they provide more error checking in the assembler. 532 * Use R0-31 only when really nessesary. 533 */ 534 535#define r0 %r0 536#define r1 %r1 537#define r2 %r2 538#define r3 %r3 539#define r4 %r4 540#define r5 %r5 541#define r6 %r6 542#define r7 %r7 543#define r8 %r8 544#define r9 %r9 545#define r10 %r10 546#define r11 %r11 547#define r12 %r12 548#define r13 %r13 549#define r14 %r14 550#define r15 %r15 551#define r16 %r16 552#define r17 %r17 553#define r18 %r18 554#define r19 %r19 555#define r20 %r20 556#define r21 %r21 557#define r22 %r22 558#define r23 %r23 559#define r24 %r24 560#define r25 %r25 561#define r26 %r26 562#define r27 %r27 563#define r28 %r28 564#define r29 %r29 565#define r30 %r30 566#define r31 %r31 567 568 569/* Floating Point Registers (FPRs) */ 570 571#define fr0 0 572#define fr1 1 573#define fr2 2 574#define fr3 3 575#define fr4 4 576#define fr5 5 577#define fr6 6 578#define fr7 7 579#define fr8 8 580#define fr9 9 581#define fr10 10 582#define fr11 11 583#define fr12 12 584#define fr13 13 585#define fr14 14 586#define fr15 15 587#define fr16 16 588#define fr17 17 589#define fr18 18 590#define fr19 19 591#define fr20 20 592#define fr21 21 593#define fr22 22 594#define fr23 23 595#define fr24 24 596#define fr25 25 597#define fr26 26 598#define fr27 27 599#define fr28 28 600#define fr29 29 601#define fr30 30 602#define fr31 31 603 604/* AltiVec Registers (VPRs) */ 605 606#define v0 0 607#define v1 1 608#define v2 2 609#define v3 3 610#define v4 4 611#define v5 5 612#define v6 6 613#define v7 7 614#define v8 8 615#define v9 9 616#define v10 10 617#define v11 11 618#define v12 12 619#define v13 13 620#define v14 14 621#define v15 15 622#define v16 16 623#define v17 17 624#define v18 18 625#define v19 19 626#define v20 20 627#define v21 21 628#define v22 22 629#define v23 23 630#define v24 24 631#define v25 25 632#define v26 26 633#define v27 27 634#define v28 28 635#define v29 29 636#define v30 30 637#define v31 31 638 639/* VSX Registers (VSRs) */ 640 641#define vs0 0 642#define vs1 1 643#define vs2 2 644#define vs3 3 645#define vs4 4 646#define vs5 5 647#define vs6 6 648#define vs7 7 649#define vs8 8 650#define vs9 9 651#define vs10 10 652#define vs11 11 653#define vs12 12 654#define vs13 13 655#define vs14 14 656#define vs15 15 657#define vs16 16 658#define vs17 17 659#define vs18 18 660#define vs19 19 661#define vs20 20 662#define vs21 21 663#define vs22 22 664#define vs23 23 665#define vs24 24 666#define vs25 25 667#define vs26 26 668#define vs27 27 669#define vs28 28 670#define vs29 29 671#define vs30 30 672#define vs31 31 673#define vs32 32 674#define vs33 33 675#define vs34 34 676#define vs35 35 677#define vs36 36 678#define vs37 37 679#define vs38 38 680#define vs39 39 681#define vs40 40 682#define vs41 41 683#define vs42 42 684#define vs43 43 685#define vs44 44 686#define vs45 45 687#define vs46 46 688#define vs47 47 689#define vs48 48 690#define vs49 49 691#define vs50 50 692#define vs51 51 693#define vs52 52 694#define vs53 53 695#define vs54 54 696#define vs55 55 697#define vs56 56 698#define vs57 57 699#define vs58 58 700#define vs59 59 701#define vs60 60 702#define vs61 61 703#define vs62 62 704#define vs63 63 705 706/* SPE Registers (EVPRs) */ 707 708#define evr0 0 709#define evr1 1 710#define evr2 2 711#define evr3 3 712#define evr4 4 713#define evr5 5 714#define evr6 6 715#define evr7 7 716#define evr8 8 717#define evr9 9 718#define evr10 10 719#define evr11 11 720#define evr12 12 721#define evr13 13 722#define evr14 14 723#define evr15 15 724#define evr16 16 725#define evr17 17 726#define evr18 18 727#define evr19 19 728#define evr20 20 729#define evr21 21 730#define evr22 22 731#define evr23 23 732#define evr24 24 733#define evr25 25 734#define evr26 26 735#define evr27 27 736#define evr28 28 737#define evr29 29 738#define evr30 30 739#define evr31 31 740 741/* some stab codes */ 742#define N_FUN 36 743#define N_RSYM 64 744#define N_SLINE 68 745#define N_SO 100 746 747#define RFSCV .long 0x4c0000a4 748 749/* 750 * Create an endian fixup trampoline 751 * 752 * This starts with a "tdi 0,0,0x48" instruction which is 753 * essentially a "trap never", and thus akin to a nop. 754 * 755 * The opcode for this instruction read with the wrong endian 756 * however results in a b . + 8 757 * 758 * So essentially we use that trick to execute the following 759 * trampoline in "reverse endian" if we are running with the 760 * MSR_LE bit set the "wrong" way for whatever endianness the 761 * kernel is built for. 762 */ 763 764#ifdef CONFIG_PPC_BOOK3E 765#define FIXUP_ENDIAN 766#else 767/* 768 * This version may be used in HV or non-HV context. 769 * MSR[EE] must be disabled. 770 */ 771#define FIXUP_ENDIAN \ 772 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 773 b 191f; /* Skip trampoline if endian is good */ \ 774 .long 0xa600607d; /* mfmsr r11 */ \ 775 .long 0x01006b69; /* xori r11,r11,1 */ \ 776 .long 0x00004039; /* li r10,0 */ \ 777 .long 0x6401417d; /* mtmsrd r10,1 */ \ 778 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 779 .long 0xa602487d; /* mflr r10 */ \ 780 .long 0x14004a39; /* addi r10,r10,20 */ \ 781 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 782 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 783 .long 0x2400004c; /* rfid */ \ 784191: 785 786/* 787 * This version that may only be used with MSR[HV]=1 788 * - Does not clear MSR[RI], so more robust. 789 * - Slightly smaller and faster. 790 */ 791#define FIXUP_ENDIAN_HV \ 792 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 793 b 191f; /* Skip trampoline if endian is good */ \ 794 .long 0xa600607d; /* mfmsr r11 */ \ 795 .long 0x01006b69; /* xori r11,r11,1 */ \ 796 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 797 .long 0xa602487d; /* mflr r10 */ \ 798 .long 0x14004a39; /* addi r10,r10,20 */ \ 799 .long 0xa64b5a7d; /* mthsrr0 r10 */ \ 800 .long 0xa64b7b7d; /* mthsrr1 r11 */ \ 801 .long 0x2402004c; /* hrfid */ \ 802191: 803 804#endif /* !CONFIG_PPC_BOOK3E */ 805 806#endif /* __ASSEMBLY__ */ 807 808/* 809 * Helper macro for exception table entries 810 */ 811#define EX_TABLE(_fault, _target) \ 812 stringify_in_c(.section __ex_table,"a";)\ 813 stringify_in_c(.balign 4;) \ 814 stringify_in_c(.long (_fault) - . ;) \ 815 stringify_in_c(.long (_target) - . ;) \ 816 stringify_in_c(.previous) 817 818#ifdef CONFIG_PPC_FSL_BOOK3E 819#define BTB_FLUSH(reg) \ 820 lis reg,BUCSR_INIT@h; \ 821 ori reg,reg,BUCSR_INIT@l; \ 822 mtspr SPRN_BUCSR,reg; \ 823 isync; 824#else 825#define BTB_FLUSH(reg) 826#endif /* CONFIG_PPC_FSL_BOOK3E */ 827 828#endif /* _ASM_POWERPC_PPC_ASM_H */ 829