18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Performance event support - hardware-specific disambiguation
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * For now this is a compile-time decision, but eventually it should be
68c2ecf20Sopenharmony_ci * runtime.  This would allow multiplatform perf event support for e300 (fsl
78c2ecf20Sopenharmony_ci * embedded perf counters) plus server/classic, and would accommodate
88c2ecf20Sopenharmony_ci * devices other than the core which provide their own performance counters.
98c2ecf20Sopenharmony_ci *
108c2ecf20Sopenharmony_ci * Copyright 2010 Freescale Semiconductor, Inc.
118c2ecf20Sopenharmony_ci */
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ci#ifdef CONFIG_PPC_PERF_CTRS
148c2ecf20Sopenharmony_ci#include <asm/perf_event_server.h>
158c2ecf20Sopenharmony_ci#else
168c2ecf20Sopenharmony_cistatic inline bool is_sier_available(void) { return false; }
178c2ecf20Sopenharmony_ci#endif
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci#ifdef CONFIG_FSL_EMB_PERF_EVENT
208c2ecf20Sopenharmony_ci#include <asm/perf_event_fsl_emb.h>
218c2ecf20Sopenharmony_ci#endif
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci#ifdef CONFIG_PERF_EVENTS
248c2ecf20Sopenharmony_ci#include <asm/ptrace.h>
258c2ecf20Sopenharmony_ci#include <asm/reg.h>
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci#define perf_arch_bpf_user_pt_regs(regs) &regs->user_regs
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci/*
308c2ecf20Sopenharmony_ci * Overload regs->result to specify whether we should use the MSR (result
318c2ecf20Sopenharmony_ci * is zero) or the SIAR (result is non zero).
328c2ecf20Sopenharmony_ci */
338c2ecf20Sopenharmony_ci#define perf_arch_fetch_caller_regs(regs, __ip)			\
348c2ecf20Sopenharmony_ci	do {							\
358c2ecf20Sopenharmony_ci		(regs)->result = 0;				\
368c2ecf20Sopenharmony_ci		(regs)->nip = __ip;				\
378c2ecf20Sopenharmony_ci		(regs)->gpr[1] = current_stack_frame();		\
388c2ecf20Sopenharmony_ci		asm volatile("mfmsr %0" : "=r" ((regs)->msr));	\
398c2ecf20Sopenharmony_ci	} while (0)
408c2ecf20Sopenharmony_ci
418c2ecf20Sopenharmony_ci/* To support perf_regs sier update */
428c2ecf20Sopenharmony_ciextern bool is_sier_available(void);
438c2ecf20Sopenharmony_ci/* To define perf extended regs mask value */
448c2ecf20Sopenharmony_ciextern u64 PERF_REG_EXTENDED_MASK;
458c2ecf20Sopenharmony_ci#define PERF_REG_EXTENDED_MASK	PERF_REG_EXTENDED_MASK
468c2ecf20Sopenharmony_ci#endif
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