1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_POWERPC_NOHASH_32_PTE_44x_H
3#define _ASM_POWERPC_NOHASH_32_PTE_44x_H
4#ifdef __KERNEL__
5
6/*
7 * Definitions for PPC440
8 *
9 * Because of the 3 word TLB entries to support 36-bit addressing,
10 * the attribute are difficult to map in such a fashion that they
11 * are easily loaded during exception processing.  I decided to
12 * organize the entry so the ERPN is the only portion in the
13 * upper word of the PTE and the attribute bits below are packed
14 * in as sensibly as they can be in the area below a 4KB page size
15 * oriented RPN.  This at least makes it easy to load the RPN and
16 * ERPN fields in the TLB. -Matt
17 *
18 * This isn't entirely true anymore, at least some bits are now
19 * easier to move into the TLB from the PTE. -BenH.
20 *
21 * Note that these bits preclude future use of a page size
22 * less than 4KB.
23 *
24 *
25 * PPC 440 core has following TLB attribute fields;
26 *
27 *   TLB1:
28 *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
29 *   RPN.................................  -  -  -  -  -  - ERPN.......
30 *
31 *   TLB2:
32 *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
33 *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
34 *
35 * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
36 * TLB2 storage attribute fields. Those are:
37 *
38 *   TLB2:
39 *   0...10    11   12   13   14   15   16...31
40 *   no change WL1  IL1I IL1D IL2I IL2D no change
41 *
42 * There are some constrains and options, to decide mapping software bits
43 * into TLB entry.
44 *
45 *   - PRESENT *must* be in the bottom three bits because swap cache
46 *     entries use the top 29 bits for TLB2.
47 *
48 *   - CACHE COHERENT bit (M) has no effect on original PPC440 cores,
49 *     because it doesn't support SMP. However, some later 460 variants
50 *     have -some- form of SMP support and so I keep the bit there for
51 *     future use
52 *
53 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
54 * for memory protection related functions (see PTE structure in
55 * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
56 * above bits.  Note that the bit values are CPU specific, not architecture
57 * specific.
58 *
59 * The kernel PTE entry holds an arch-dependent swp_entry structure under
60 * certain situations. In other words, in such situations some portion of
61 * the PTE bits are used as a swp_entry. In the PPC implementation, the
62 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
63 * hold protection values. That means the three protection bits are
64 * reserved for both PTE and SWAP entry at the most significant three
65 * LSBs.
66 *
67 * There are three protection bits available for SWAP entry:
68 *	_PAGE_PRESENT
69 *	_PAGE_HASHPTE (if HW has)
70 *
71 * So those three bits have to be inside of 0-2nd LSB of PTE.
72 *
73 */
74
75#define _PAGE_PRESENT	0x00000001		/* S: PTE valid */
76#define _PAGE_RW	0x00000002		/* S: Write permission */
77#define _PAGE_EXEC	0x00000004		/* H: Execute permission */
78#define _PAGE_ACCESSED	0x00000008		/* S: Page referenced */
79#define _PAGE_DIRTY	0x00000010		/* S: Page dirty */
80#define _PAGE_SPECIAL	0x00000020		/* S: Special page */
81#define _PAGE_USER	0x00000040		/* S: User page */
82#define _PAGE_ENDIAN	0x00000080		/* H: E bit */
83#define _PAGE_GUARDED	0x00000100		/* H: G bit */
84#define _PAGE_COHERENT	0x00000200		/* H: M bit */
85#define _PAGE_NO_CACHE	0x00000400		/* H: I bit */
86#define _PAGE_WRITETHRU	0x00000800		/* H: W bit */
87
88/* No page size encoding in the linux PTE */
89#define _PAGE_PSIZE		0
90
91#define _PAGE_KERNEL_RO		0
92#define _PAGE_KERNEL_ROX	_PAGE_EXEC
93#define _PAGE_KERNEL_RW		(_PAGE_DIRTY | _PAGE_RW)
94#define _PAGE_KERNEL_RWX	(_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
95
96/* TODO: Add large page lowmem mapping support */
97#define _PMD_PRESENT	0
98#define _PMD_PRESENT_MASK (PAGE_MASK)
99#define _PMD_BAD	(~PAGE_MASK)
100#define _PMD_USER	0
101
102/* ERPN in a PTE never gets cleared, ignore it */
103#define _PTE_NONE_MASK	0xffffffff00000000ULL
104
105/*
106 * We define 2 sets of base prot bits, one for basic pages (ie,
107 * cacheable kernel and user pages) and one for non cacheable
108 * pages. We always set _PAGE_COHERENT when SMP is enabled or
109 * the processor might need it for DMA coherency.
110 */
111#define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED)
112#if defined(CONFIG_SMP)
113#define _PAGE_BASE	(_PAGE_BASE_NC | _PAGE_COHERENT)
114#else
115#define _PAGE_BASE	(_PAGE_BASE_NC)
116#endif
117
118/* Permission masks used to generate the __P and __S table */
119#define PAGE_NONE	__pgprot(_PAGE_BASE)
120#define PAGE_SHARED	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
121#define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
122#define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_USER)
123#define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
124#define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_USER)
125#define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
126
127#endif /* __KERNEL__ */
128#endif /*  _ASM_POWERPC_NOHASH_32_PTE_44x_H */
129