1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright SUSE Linux Products GmbH 2010
5 *
6 * Authors: Alexander Graf <agraf@suse.de>
7 */
8
9#ifndef __ASM_KVM_BOOK3S_64_H__
10#define __ASM_KVM_BOOK3S_64_H__
11
12#include <linux/string.h>
13#include <asm/bitops.h>
14#include <asm/book3s/64/mmu-hash.h>
15#include <asm/cpu_has_feature.h>
16#include <asm/ppc-opcode.h>
17#include <asm/pte-walk.h>
18
19#ifdef CONFIG_PPC_PSERIES
20static inline bool kvmhv_on_pseries(void)
21{
22	return !cpu_has_feature(CPU_FTR_HVMODE);
23}
24#else
25static inline bool kvmhv_on_pseries(void)
26{
27	return false;
28}
29#endif
30
31/*
32 * Structure for a nested guest, that is, for a guest that is managed by
33 * one of our guests.
34 */
35struct kvm_nested_guest {
36	struct kvm *l1_host;		/* L1 VM that owns this nested guest */
37	int l1_lpid;			/* lpid L1 guest thinks this guest is */
38	int shadow_lpid;		/* real lpid of this nested guest */
39	pgd_t *shadow_pgtable;		/* our page table for this guest */
40	u64 l1_gr_to_hr;		/* L1's addr of part'n-scoped table */
41	u64 process_table;		/* process table entry for this guest */
42	long refcnt;			/* number of pointers to this struct */
43	struct mutex tlb_lock;		/* serialize page faults and tlbies */
44	struct kvm_nested_guest *next;
45	cpumask_t need_tlb_flush;
46	cpumask_t cpu_in_guest;
47	short prev_cpu[NR_CPUS];
48	u8 radix;			/* is this nested guest radix */
49};
50
51/*
52 * We define a nested rmap entry as a single 64-bit quantity
53 * 0xFFF0000000000000	12-bit lpid field
54 * 0x000FFFFFFFFFF000	40-bit guest 4k page frame number
55 * 0x0000000000000001	1-bit  single entry flag
56 */
57#define RMAP_NESTED_LPID_MASK		0xFFF0000000000000UL
58#define RMAP_NESTED_LPID_SHIFT		(52)
59#define RMAP_NESTED_GPA_MASK		0x000FFFFFFFFFF000UL
60#define RMAP_NESTED_IS_SINGLE_ENTRY	0x0000000000000001UL
61
62/* Structure for a nested guest rmap entry */
63struct rmap_nested {
64	struct llist_node list;
65	u64 rmap;
66};
67
68/*
69 * for_each_nest_rmap_safe - iterate over the list of nested rmap entries
70 *			     safe against removal of the list entry or NULL list
71 * @pos:	a (struct rmap_nested *) to use as a loop cursor
72 * @node:	pointer to the first entry
73 *		NOTE: this can be NULL
74 * @rmapp:	an (unsigned long *) in which to return the rmap entries on each
75 *		iteration
76 *		NOTE: this must point to already allocated memory
77 *
78 * The nested_rmap is a llist of (struct rmap_nested) entries pointed to by the
79 * rmap entry in the memslot. The list is always terminated by a "single entry"
80 * stored in the list element of the final entry of the llist. If there is ONLY
81 * a single entry then this is itself in the rmap entry of the memslot, not a
82 * llist head pointer.
83 *
84 * Note that the iterator below assumes that a nested rmap entry is always
85 * non-zero.  This is true for our usage because the LPID field is always
86 * non-zero (zero is reserved for the host).
87 *
88 * This should be used to iterate over the list of rmap_nested entries with
89 * processing done on the u64 rmap value given by each iteration. This is safe
90 * against removal of list entries and it is always safe to call free on (pos).
91 *
92 * e.g.
93 * struct rmap_nested *cursor;
94 * struct llist_node *first;
95 * unsigned long rmap;
96 * for_each_nest_rmap_safe(cursor, first, &rmap) {
97 *	do_something(rmap);
98 *	free(cursor);
99 * }
100 */
101#define for_each_nest_rmap_safe(pos, node, rmapp)			       \
102	for ((pos) = llist_entry((node), typeof(*(pos)), list);		       \
103	     (node) &&							       \
104	     (*(rmapp) = ((RMAP_NESTED_IS_SINGLE_ENTRY & ((u64) (node))) ?     \
105			  ((u64) (node)) : ((pos)->rmap))) &&		       \
106	     (((node) = ((RMAP_NESTED_IS_SINGLE_ENTRY & ((u64) (node))) ?      \
107			 ((struct llist_node *) ((pos) = NULL)) :	       \
108			 (pos)->list.next)), true);			       \
109	     (pos) = llist_entry((node), typeof(*(pos)), list))
110
111struct kvm_nested_guest *kvmhv_get_nested(struct kvm *kvm, int l1_lpid,
112					  bool create);
113void kvmhv_put_nested(struct kvm_nested_guest *gp);
114int kvmhv_nested_next_lpid(struct kvm *kvm, int lpid);
115
116/* Encoding of first parameter for H_TLB_INVALIDATE */
117#define H_TLBIE_P1_ENC(ric, prs, r)	(___PPC_RIC(ric) | ___PPC_PRS(prs) | \
118					 ___PPC_R(r))
119
120/* Power architecture requires HPT is at least 256kiB, at most 64TiB */
121#define PPC_MIN_HPT_ORDER	18
122#define PPC_MAX_HPT_ORDER	46
123
124#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
125static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
126{
127	preempt_disable();
128	return &get_paca()->shadow_vcpu;
129}
130
131static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
132{
133	preempt_enable();
134}
135#endif
136
137#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
138
139static inline bool kvm_is_radix(struct kvm *kvm)
140{
141	return kvm->arch.radix;
142}
143
144static inline bool kvmhv_vcpu_is_radix(struct kvm_vcpu *vcpu)
145{
146	bool radix;
147
148	if (vcpu->arch.nested)
149		radix = vcpu->arch.nested->radix;
150	else
151		radix = kvm_is_radix(vcpu->kvm);
152
153	return radix;
154}
155
156#define KVM_DEFAULT_HPT_ORDER	24	/* 16MB HPT by default */
157#endif
158
159/*
160 * We use a lock bit in HPTE dword 0 to synchronize updates and
161 * accesses to each HPTE, and another bit to indicate non-present
162 * HPTEs.
163 */
164#define HPTE_V_HVLOCK	0x40UL
165#define HPTE_V_ABSENT	0x20UL
166
167/*
168 * We use this bit in the guest_rpte field of the revmap entry
169 * to indicate a modified HPTE.
170 */
171#define HPTE_GR_MODIFIED	(1ul << 62)
172
173/* These bits are reserved in the guest view of the HPTE */
174#define HPTE_GR_RESERVED	HPTE_GR_MODIFIED
175
176static inline long try_lock_hpte(__be64 *hpte, unsigned long bits)
177{
178	unsigned long tmp, old;
179	__be64 be_lockbit, be_bits;
180
181	/*
182	 * We load/store in native endian, but the HTAB is in big endian. If
183	 * we byte swap all data we apply on the PTE we're implicitly correct
184	 * again.
185	 */
186	be_lockbit = cpu_to_be64(HPTE_V_HVLOCK);
187	be_bits = cpu_to_be64(bits);
188
189	asm volatile("	ldarx	%0,0,%2\n"
190		     "	and.	%1,%0,%3\n"
191		     "	bne	2f\n"
192		     "	or	%0,%0,%4\n"
193		     "  stdcx.	%0,0,%2\n"
194		     "	beq+	2f\n"
195		     "	mr	%1,%3\n"
196		     "2:	isync"
197		     : "=&r" (tmp), "=&r" (old)
198		     : "r" (hpte), "r" (be_bits), "r" (be_lockbit)
199		     : "cc", "memory");
200	return old == 0;
201}
202
203static inline void unlock_hpte(__be64 *hpte, unsigned long hpte_v)
204{
205	hpte_v &= ~HPTE_V_HVLOCK;
206	asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
207	hpte[0] = cpu_to_be64(hpte_v);
208}
209
210/* Without barrier */
211static inline void __unlock_hpte(__be64 *hpte, unsigned long hpte_v)
212{
213	hpte_v &= ~HPTE_V_HVLOCK;
214	hpte[0] = cpu_to_be64(hpte_v);
215}
216
217/*
218 * These functions encode knowledge of the POWER7/8/9 hardware
219 * interpretations of the HPTE LP (large page size) field.
220 */
221static inline int kvmppc_hpte_page_shifts(unsigned long h, unsigned long l)
222{
223	unsigned int lphi;
224
225	if (!(h & HPTE_V_LARGE))
226		return 12;	/* 4kB */
227	lphi = (l >> 16) & 0xf;
228	switch ((l >> 12) & 0xf) {
229	case 0:
230		return !lphi ? 24 : 0;		/* 16MB */
231		break;
232	case 1:
233		return 16;			/* 64kB */
234		break;
235	case 3:
236		return !lphi ? 34 : 0;		/* 16GB */
237		break;
238	case 7:
239		return (16 << 8) + 12;		/* 64kB in 4kB */
240		break;
241	case 8:
242		if (!lphi)
243			return (24 << 8) + 16;	/* 16MB in 64kkB */
244		if (lphi == 3)
245			return (24 << 8) + 12;	/* 16MB in 4kB */
246		break;
247	}
248	return 0;
249}
250
251static inline int kvmppc_hpte_base_page_shift(unsigned long h, unsigned long l)
252{
253	return kvmppc_hpte_page_shifts(h, l) & 0xff;
254}
255
256static inline int kvmppc_hpte_actual_page_shift(unsigned long h, unsigned long l)
257{
258	int tmp = kvmppc_hpte_page_shifts(h, l);
259
260	if (tmp >= 0x100)
261		tmp >>= 8;
262	return tmp;
263}
264
265static inline unsigned long kvmppc_actual_pgsz(unsigned long v, unsigned long r)
266{
267	int shift = kvmppc_hpte_actual_page_shift(v, r);
268
269	if (shift)
270		return 1ul << shift;
271	return 0;
272}
273
274static inline int kvmppc_pgsize_lp_encoding(int base_shift, int actual_shift)
275{
276	switch (base_shift) {
277	case 12:
278		switch (actual_shift) {
279		case 12:
280			return 0;
281		case 16:
282			return 7;
283		case 24:
284			return 0x38;
285		}
286		break;
287	case 16:
288		switch (actual_shift) {
289		case 16:
290			return 1;
291		case 24:
292			return 8;
293		}
294		break;
295	case 24:
296		return 0;
297	}
298	return -1;
299}
300
301static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
302					     unsigned long pte_index)
303{
304	int a_pgshift, b_pgshift;
305	unsigned long rb = 0, va_low, sllp;
306
307	b_pgshift = a_pgshift = kvmppc_hpte_page_shifts(v, r);
308	if (a_pgshift >= 0x100) {
309		b_pgshift &= 0xff;
310		a_pgshift >>= 8;
311	}
312
313	/*
314	 * Ignore the top 14 bits of va
315	 * v have top two bits covering segment size, hence move
316	 * by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits.
317	 * AVA field in v also have the lower 23 bits ignored.
318	 * For base page size 4K we need 14 .. 65 bits (so need to
319	 * collect extra 11 bits)
320	 * For others we need 14..14+i
321	 */
322	/* This covers 14..54 bits of va*/
323	rb = (v & ~0x7fUL) << 16;		/* AVA field */
324
325	/*
326	 * AVA in v had cleared lower 23 bits. We need to derive
327	 * that from pteg index
328	 */
329	va_low = pte_index >> 3;
330	if (v & HPTE_V_SECONDARY)
331		va_low = ~va_low;
332	/*
333	 * get the vpn bits from va_low using reverse of hashing.
334	 * In v we have va with 23 bits dropped and then left shifted
335	 * HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need
336	 * right shift it with (SID_SHIFT - (23 - 7))
337	 */
338	if (!(v & HPTE_V_1TB_SEG))
339		va_low ^= v >> (SID_SHIFT - 16);
340	else
341		va_low ^= v >> (SID_SHIFT_1T - 16);
342	va_low &= 0x7ff;
343
344	if (b_pgshift <= 12) {
345		if (a_pgshift > 12) {
346			sllp = (a_pgshift == 16) ? 5 : 4;
347			rb |= sllp << 5;	/*  AP field */
348		}
349		rb |= (va_low & 0x7ff) << 12;	/* remaining 11 bits of AVA */
350	} else {
351		int aval_shift;
352		/*
353		 * remaining bits of AVA/LP fields
354		 * Also contain the rr bits of LP
355		 */
356		rb |= (va_low << b_pgshift) & 0x7ff000;
357		/*
358		 * Now clear not needed LP bits based on actual psize
359		 */
360		rb &= ~((1ul << a_pgshift) - 1);
361		/*
362		 * AVAL field 58..77 - base_page_shift bits of va
363		 * we have space for 58..64 bits, Missing bits should
364		 * be zero filled. +1 is to take care of L bit shift
365		 */
366		aval_shift = 64 - (77 - b_pgshift) + 1;
367		rb |= ((va_low << aval_shift) & 0xfe);
368
369		rb |= 1;		/* L field */
370		rb |= r & 0xff000 & ((1ul << a_pgshift) - 1); /* LP field */
371	}
372	rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8;	/* B field */
373	return rb;
374}
375
376static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
377{
378	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
379}
380
381static inline int hpte_is_writable(unsigned long ptel)
382{
383	unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
384
385	return pp != PP_RXRX && pp != PP_RXXX;
386}
387
388static inline unsigned long hpte_make_readonly(unsigned long ptel)
389{
390	if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
391		ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
392	else
393		ptel |= PP_RXRX;
394	return ptel;
395}
396
397static inline bool hpte_cache_flags_ok(unsigned long hptel, bool is_ci)
398{
399	unsigned int wimg = hptel & HPTE_R_WIMG;
400
401	/* Handle SAO */
402	if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
403	    cpu_has_feature(CPU_FTR_ARCH_206))
404		wimg = HPTE_R_M;
405
406	if (!is_ci)
407		return wimg == HPTE_R_M;
408	/*
409	 * if host is mapped cache inhibited, make sure hptel also have
410	 * cache inhibited.
411	 */
412	if (wimg & HPTE_R_W) /* FIXME!! is this ok for all guest. ? */
413		return false;
414	return !!(wimg & HPTE_R_I);
415}
416
417/*
418 * If it's present and writable, atomically set dirty and referenced bits and
419 * return the PTE, otherwise return 0.
420 */
421static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing)
422{
423	pte_t old_pte, new_pte = __pte(0);
424
425	while (1) {
426		/*
427		 * Make sure we don't reload from ptep
428		 */
429		old_pte = READ_ONCE(*ptep);
430		/*
431		 * wait until H_PAGE_BUSY is clear then set it atomically
432		 */
433		if (unlikely(pte_val(old_pte) & H_PAGE_BUSY)) {
434			cpu_relax();
435			continue;
436		}
437		/* If pte is not present return None */
438		if (unlikely(!pte_present(old_pte)))
439			return __pte(0);
440
441		new_pte = pte_mkyoung(old_pte);
442		if (writing && pte_write(old_pte))
443			new_pte = pte_mkdirty(new_pte);
444
445		if (pte_xchg(ptep, old_pte, new_pte))
446			break;
447	}
448	return new_pte;
449}
450
451static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
452{
453	if (key)
454		return PP_RWRX <= pp && pp <= PP_RXRX;
455	return true;
456}
457
458static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
459{
460	if (key)
461		return pp == PP_RWRW;
462	return pp <= PP_RWRW;
463}
464
465static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
466{
467	unsigned long skey;
468
469	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
470		((hpte_r & HPTE_R_KEY_LO) >> 9);
471	return (amr >> (62 - 2 * skey)) & 3;
472}
473
474static inline void lock_rmap(unsigned long *rmap)
475{
476	do {
477		while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
478			cpu_relax();
479	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
480}
481
482static inline void unlock_rmap(unsigned long *rmap)
483{
484	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
485}
486
487static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
488				   unsigned long pagesize)
489{
490	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
491
492	if (pagesize <= PAGE_SIZE)
493		return true;
494	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
495}
496
497/*
498 * This works for 4k, 64k and 16M pages on POWER7,
499 * and 4k and 16M pages on PPC970.
500 */
501static inline unsigned long slb_pgsize_encoding(unsigned long psize)
502{
503	unsigned long senc = 0;
504
505	if (psize > 0x1000) {
506		senc = SLB_VSID_L;
507		if (psize == 0x10000)
508			senc |= SLB_VSID_LP_01;
509	}
510	return senc;
511}
512
513static inline int is_vrma_hpte(unsigned long hpte_v)
514{
515	return (hpte_v & ~0xffffffUL) ==
516		(HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)));
517}
518
519#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
520/*
521 * Note modification of an HPTE; set the HPTE modified bit
522 * if anyone is interested.
523 */
524static inline void note_hpte_modification(struct kvm *kvm,
525					  struct revmap_entry *rev)
526{
527	if (atomic_read(&kvm->arch.hpte_mod_interest))
528		rev->guest_rpte |= HPTE_GR_MODIFIED;
529}
530
531/*
532 * Like kvm_memslots(), but for use in real mode when we can't do
533 * any RCU stuff (since the secondary threads are offline from the
534 * kernel's point of view), and we can't print anything.
535 * Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
536 */
537static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
538{
539	return rcu_dereference_raw_check(kvm->memslots[0]);
540}
541
542extern void kvmppc_mmu_debugfs_init(struct kvm *kvm);
543extern void kvmhv_radix_debugfs_init(struct kvm *kvm);
544
545extern void kvmhv_rm_send_ipi(int cpu);
546
547static inline unsigned long kvmppc_hpt_npte(struct kvm_hpt_info *hpt)
548{
549	/* HPTEs are 2**4 bytes long */
550	return 1UL << (hpt->order - 4);
551}
552
553static inline unsigned long kvmppc_hpt_mask(struct kvm_hpt_info *hpt)
554{
555	/* 128 (2**7) bytes in each HPTEG */
556	return (1UL << (hpt->order - 7)) - 1;
557}
558
559/* Set bits in a dirty bitmap, which is in LE format */
560static inline void set_dirty_bits(unsigned long *map, unsigned long i,
561				  unsigned long npages)
562{
563
564	if (npages >= 8)
565		memset((char *)map + i / 8, 0xff, npages / 8);
566	else
567		for (; npages; ++i, --npages)
568			__set_bit_le(i, map);
569}
570
571static inline void set_dirty_bits_atomic(unsigned long *map, unsigned long i,
572					 unsigned long npages)
573{
574	if (npages >= 8)
575		memset((char *)map + i / 8, 0xff, npages / 8);
576	else
577		for (; npages; ++i, --npages)
578			set_bit_le(i, map);
579}
580
581static inline u64 sanitize_msr(u64 msr)
582{
583	msr &= ~MSR_HV;
584	msr |= MSR_ME;
585	return msr;
586}
587
588#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
589static inline void copy_from_checkpoint(struct kvm_vcpu *vcpu)
590{
591	vcpu->arch.regs.ccr  = vcpu->arch.cr_tm;
592	vcpu->arch.regs.xer = vcpu->arch.xer_tm;
593	vcpu->arch.regs.link  = vcpu->arch.lr_tm;
594	vcpu->arch.regs.ctr = vcpu->arch.ctr_tm;
595	vcpu->arch.amr = vcpu->arch.amr_tm;
596	vcpu->arch.ppr = vcpu->arch.ppr_tm;
597	vcpu->arch.dscr = vcpu->arch.dscr_tm;
598	vcpu->arch.tar = vcpu->arch.tar_tm;
599	memcpy(vcpu->arch.regs.gpr, vcpu->arch.gpr_tm,
600	       sizeof(vcpu->arch.regs.gpr));
601	vcpu->arch.fp  = vcpu->arch.fp_tm;
602	vcpu->arch.vr  = vcpu->arch.vr_tm;
603	vcpu->arch.vrsave = vcpu->arch.vrsave_tm;
604}
605
606static inline void copy_to_checkpoint(struct kvm_vcpu *vcpu)
607{
608	vcpu->arch.cr_tm  = vcpu->arch.regs.ccr;
609	vcpu->arch.xer_tm = vcpu->arch.regs.xer;
610	vcpu->arch.lr_tm  = vcpu->arch.regs.link;
611	vcpu->arch.ctr_tm = vcpu->arch.regs.ctr;
612	vcpu->arch.amr_tm = vcpu->arch.amr;
613	vcpu->arch.ppr_tm = vcpu->arch.ppr;
614	vcpu->arch.dscr_tm = vcpu->arch.dscr;
615	vcpu->arch.tar_tm = vcpu->arch.tar;
616	memcpy(vcpu->arch.gpr_tm, vcpu->arch.regs.gpr,
617	       sizeof(vcpu->arch.regs.gpr));
618	vcpu->arch.fp_tm  = vcpu->arch.fp;
619	vcpu->arch.vr_tm  = vcpu->arch.vr;
620	vcpu->arch.vrsave_tm = vcpu->arch.vrsave;
621}
622#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
623
624extern int kvmppc_create_pte(struct kvm *kvm, pgd_t *pgtable, pte_t pte,
625			     unsigned long gpa, unsigned int level,
626			     unsigned long mmu_seq, unsigned int lpid,
627			     unsigned long *rmapp, struct rmap_nested **n_rmap);
628extern void kvmhv_insert_nest_rmap(struct kvm *kvm, unsigned long *rmapp,
629				   struct rmap_nested **n_rmap);
630extern void kvmhv_update_nest_rmap_rc_list(struct kvm *kvm, unsigned long *rmapp,
631					   unsigned long clr, unsigned long set,
632					   unsigned long hpa, unsigned long nbytes);
633extern void kvmhv_remove_nest_rmap_range(struct kvm *kvm,
634				const struct kvm_memory_slot *memslot,
635				unsigned long gpa, unsigned long hpa,
636				unsigned long nbytes);
637
638static inline pte_t *
639find_kvm_secondary_pte_unlocked(struct kvm *kvm, unsigned long ea,
640				unsigned *hshift)
641{
642	pte_t *pte;
643
644	pte = __find_linux_pte(kvm->arch.pgtable, ea, NULL, hshift);
645	return pte;
646}
647
648static inline pte_t *find_kvm_secondary_pte(struct kvm *kvm, unsigned long ea,
649					    unsigned *hshift)
650{
651	pte_t *pte;
652
653	VM_WARN(!spin_is_locked(&kvm->mmu_lock),
654		"%s called with kvm mmu_lock not held \n", __func__);
655	pte = __find_linux_pte(kvm->arch.pgtable, ea, NULL, hshift);
656
657	return pte;
658}
659
660static inline pte_t *find_kvm_host_pte(struct kvm *kvm, unsigned long mmu_seq,
661				       unsigned long ea, unsigned *hshift)
662{
663	pte_t *pte;
664
665	VM_WARN(!spin_is_locked(&kvm->mmu_lock),
666		"%s called with kvm mmu_lock not held \n", __func__);
667
668	if (mmu_notifier_retry(kvm, mmu_seq))
669		return NULL;
670
671	pte = __find_linux_pte(kvm->mm->pgd, ea, NULL, hshift);
672
673	return pte;
674}
675
676extern pte_t *find_kvm_nested_guest_pte(struct kvm *kvm, unsigned long lpid,
677					unsigned long ea, unsigned *hshift);
678
679#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
680
681#endif /* __ASM_KVM_BOOK3S_64_H__ */
682