1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2#ifndef _ASM_POWERPC_IO_H 3#define _ASM_POWERPC_IO_H 4#ifdef __KERNEL__ 5 6#define ARCH_HAS_IOREMAP_WC 7#ifdef CONFIG_PPC32 8#define ARCH_HAS_IOREMAP_WT 9#endif 10 11/* 12 */ 13 14/* Check of existence of legacy devices */ 15extern int check_legacy_ioport(unsigned long base_port); 16#define I8042_DATA_REG 0x60 17#define FDC_BASE 0x3f0 18 19#if defined(CONFIG_PPC64) && defined(CONFIG_PCI) 20extern struct pci_dev *isa_bridge_pcidev; 21/* 22 * has legacy ISA devices ? 23 */ 24#define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special) 25#endif 26 27#include <linux/device.h> 28#include <linux/compiler.h> 29#include <linux/mm.h> 30#include <asm/page.h> 31#include <asm/byteorder.h> 32#include <asm/synch.h> 33#include <asm/delay.h> 34#include <asm/mmiowb.h> 35#include <asm/mmu.h> 36#include <asm/ppc_asm.h> 37 38#define SIO_CONFIG_RA 0x398 39#define SIO_CONFIG_RD 0x399 40 41#define SLOW_DOWN_IO 42 43/* 32 bits uses slightly different variables for the various IO 44 * bases. Most of this file only uses _IO_BASE though which we 45 * define properly based on the platform 46 */ 47#ifndef CONFIG_PCI 48#define _IO_BASE 0 49#define _ISA_MEM_BASE 0 50#define PCI_DRAM_OFFSET 0 51#elif defined(CONFIG_PPC32) 52#define _IO_BASE isa_io_base 53#define _ISA_MEM_BASE isa_mem_base 54#define PCI_DRAM_OFFSET pci_dram_offset 55#else 56#define _IO_BASE pci_io_base 57#define _ISA_MEM_BASE isa_mem_base 58#define PCI_DRAM_OFFSET 0 59#endif 60 61extern unsigned long isa_io_base; 62extern unsigned long pci_io_base; 63extern unsigned long pci_dram_offset; 64 65extern resource_size_t isa_mem_base; 66 67/* Boolean set by platform if PIO accesses are suppored while _IO_BASE 68 * is not set or addresses cannot be translated to MMIO. This is typically 69 * set when the platform supports "special" PIO accesses via a non memory 70 * mapped mechanism, and allows things like the early udbg UART code to 71 * function. 72 */ 73extern bool isa_io_special; 74 75#ifdef CONFIG_PPC32 76#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 77#error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits 78#endif 79#endif 80 81/* 82 * 83 * Low level MMIO accessors 84 * 85 * This provides the non-bus specific accessors to MMIO. Those are PowerPC 86 * specific and thus shouldn't be used in generic code. The accessors 87 * provided here are: 88 * 89 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 90 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 91 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns 92 * 93 * Those operate directly on a kernel virtual address. Note that the prototype 94 * for the out_* accessors has the arguments in opposite order from the usual 95 * linux PCI accessors. Unlike those, they take the address first and the value 96 * next. 97 * 98 * Note: I might drop the _ns suffix on the stream operations soon as it is 99 * simply normal for stream operations to not swap in the first place. 100 * 101 */ 102 103#define DEF_MMIO_IN_X(name, size, insn) \ 104static inline u##size name(const volatile u##size __iomem *addr) \ 105{ \ 106 u##size ret; \ 107 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ 108 : "=r" (ret) : "Z" (*addr) : "memory"); \ 109 return ret; \ 110} 111 112#define DEF_MMIO_OUT_X(name, size, insn) \ 113static inline void name(volatile u##size __iomem *addr, u##size val) \ 114{ \ 115 __asm__ __volatile__("sync;"#insn" %1,%y0" \ 116 : "=Z" (*addr) : "r" (val) : "memory"); \ 117 mmiowb_set_pending(); \ 118} 119 120#define DEF_MMIO_IN_D(name, size, insn) \ 121static inline u##size name(const volatile u##size __iomem *addr) \ 122{ \ 123 u##size ret; \ 124 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ 125 : "=r" (ret) : "m" (*addr) : "memory"); \ 126 return ret; \ 127} 128 129#define DEF_MMIO_OUT_D(name, size, insn) \ 130static inline void name(volatile u##size __iomem *addr, u##size val) \ 131{ \ 132 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ 133 : "=m" (*addr) : "r" (val) : "memory"); \ 134 mmiowb_set_pending(); \ 135} 136 137DEF_MMIO_IN_D(in_8, 8, lbz); 138DEF_MMIO_OUT_D(out_8, 8, stb); 139 140#ifdef __BIG_ENDIAN__ 141DEF_MMIO_IN_D(in_be16, 16, lhz); 142DEF_MMIO_IN_D(in_be32, 32, lwz); 143DEF_MMIO_IN_X(in_le16, 16, lhbrx); 144DEF_MMIO_IN_X(in_le32, 32, lwbrx); 145 146DEF_MMIO_OUT_D(out_be16, 16, sth); 147DEF_MMIO_OUT_D(out_be32, 32, stw); 148DEF_MMIO_OUT_X(out_le16, 16, sthbrx); 149DEF_MMIO_OUT_X(out_le32, 32, stwbrx); 150#else 151DEF_MMIO_IN_X(in_be16, 16, lhbrx); 152DEF_MMIO_IN_X(in_be32, 32, lwbrx); 153DEF_MMIO_IN_D(in_le16, 16, lhz); 154DEF_MMIO_IN_D(in_le32, 32, lwz); 155 156DEF_MMIO_OUT_X(out_be16, 16, sthbrx); 157DEF_MMIO_OUT_X(out_be32, 32, stwbrx); 158DEF_MMIO_OUT_D(out_le16, 16, sth); 159DEF_MMIO_OUT_D(out_le32, 32, stw); 160 161#endif /* __BIG_ENDIAN */ 162 163#ifdef __powerpc64__ 164 165#ifdef __BIG_ENDIAN__ 166DEF_MMIO_OUT_D(out_be64, 64, std); 167DEF_MMIO_IN_D(in_be64, 64, ld); 168 169/* There is no asm instructions for 64 bits reverse loads and stores */ 170static inline u64 in_le64(const volatile u64 __iomem *addr) 171{ 172 return swab64(in_be64(addr)); 173} 174 175static inline void out_le64(volatile u64 __iomem *addr, u64 val) 176{ 177 out_be64(addr, swab64(val)); 178} 179#else 180DEF_MMIO_OUT_D(out_le64, 64, std); 181DEF_MMIO_IN_D(in_le64, 64, ld); 182 183/* There is no asm instructions for 64 bits reverse loads and stores */ 184static inline u64 in_be64(const volatile u64 __iomem *addr) 185{ 186 return swab64(in_le64(addr)); 187} 188 189static inline void out_be64(volatile u64 __iomem *addr, u64 val) 190{ 191 out_le64(addr, swab64(val)); 192} 193 194#endif 195#endif /* __powerpc64__ */ 196 197/* 198 * Low level IO stream instructions are defined out of line for now 199 */ 200extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); 201extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); 202extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); 203extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); 204extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); 205extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); 206 207/* The _ns naming is historical and will be removed. For now, just #define 208 * the non _ns equivalent names 209 */ 210#define _insw _insw_ns 211#define _insl _insl_ns 212#define _outsw _outsw_ns 213#define _outsl _outsl_ns 214 215 216/* 217 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line 218 */ 219 220extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); 221extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, 222 unsigned long n); 223extern void _memcpy_toio(volatile void __iomem *dest, const void *src, 224 unsigned long n); 225 226/* 227 * 228 * PCI and standard ISA accessors 229 * 230 * Those are globally defined linux accessors for devices on PCI or ISA 231 * busses. They follow the Linux defined semantics. The current implementation 232 * for PowerPC is as close as possible to the x86 version of these, and thus 233 * provides fairly heavy weight barriers for the non-raw versions 234 * 235 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO 236 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its 237 * own implementation of some or all of the accessors. 238 */ 239 240/* 241 * Include the EEH definitions when EEH is enabled only so they don't get 242 * in the way when building for 32 bits 243 */ 244#ifdef CONFIG_EEH 245#include <asm/eeh.h> 246#endif 247 248/* Shortcut to the MMIO argument pointer */ 249#define PCI_IO_ADDR volatile void __iomem * 250 251/* Indirect IO address tokens: 252 * 253 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks 254 * on all MMIOs. (Note that this is all 64 bits only for now) 255 * 256 * To help platforms who may need to differentiate MMIO addresses in 257 * their hooks, a bitfield is reserved for use by the platform near the 258 * top of MMIO addresses (not PIO, those have to cope the hard way). 259 * 260 * The highest address in the kernel virtual space are: 261 * 262 * d0003fffffffffff # with Hash MMU 263 * c00fffffffffffff # with Radix MMU 264 * 265 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits 266 * that can be used for the field. 267 * 268 * The direct IO mapping operations will then mask off those bits 269 * before doing the actual access, though that only happen when 270 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that 271 * mechanism 272 * 273 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes 274 * all PIO functions call through a hook. 275 */ 276 277#ifdef CONFIG_PPC_INDIRECT_MMIO 278#define PCI_IO_IND_TOKEN_SHIFT 52 279#define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT) 280#define PCI_FIX_ADDR(addr) \ 281 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) 282#define PCI_GET_ADDR_TOKEN(addr) \ 283 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ 284 PCI_IO_IND_TOKEN_SHIFT) 285#define PCI_SET_ADDR_TOKEN(addr, token) \ 286do { \ 287 unsigned long __a = (unsigned long)(addr); \ 288 __a &= ~PCI_IO_IND_TOKEN_MASK; \ 289 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ 290 (addr) = (void __iomem *)__a; \ 291} while(0) 292#else 293#define PCI_FIX_ADDR(addr) (addr) 294#endif 295 296 297/* 298 * Non ordered and non-swapping "raw" accessors 299 */ 300 301static inline unsigned char __raw_readb(const volatile void __iomem *addr) 302{ 303 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); 304} 305static inline unsigned short __raw_readw(const volatile void __iomem *addr) 306{ 307 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); 308} 309static inline unsigned int __raw_readl(const volatile void __iomem *addr) 310{ 311 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); 312} 313static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 314{ 315 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; 316} 317static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 318{ 319 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; 320} 321static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 322{ 323 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; 324} 325 326#ifdef __powerpc64__ 327static inline unsigned long __raw_readq(const volatile void __iomem *addr) 328{ 329 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); 330} 331static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 332{ 333 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; 334} 335 336static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr) 337{ 338 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr); 339} 340 341/* 342 * Real mode versions of the above. Those instructions are only supposed 343 * to be used in hypervisor real mode as per the architecture spec. 344 */ 345static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr) 346{ 347 __asm__ __volatile__(".machine push; \ 348 .machine power6; \ 349 stbcix %0,0,%1; \ 350 .machine pop;" 351 : : "r" (val), "r" (paddr) : "memory"); 352} 353 354static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr) 355{ 356 __asm__ __volatile__(".machine push; \ 357 .machine power6; \ 358 sthcix %0,0,%1; \ 359 .machine pop;" 360 : : "r" (val), "r" (paddr) : "memory"); 361} 362 363static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr) 364{ 365 __asm__ __volatile__(".machine push; \ 366 .machine power6; \ 367 stwcix %0,0,%1; \ 368 .machine pop;" 369 : : "r" (val), "r" (paddr) : "memory"); 370} 371 372static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 373{ 374 __asm__ __volatile__(".machine push; \ 375 .machine power6; \ 376 stdcix %0,0,%1; \ 377 .machine pop;" 378 : : "r" (val), "r" (paddr) : "memory"); 379} 380 381static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr) 382{ 383 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr); 384} 385 386static inline u8 __raw_rm_readb(volatile void __iomem *paddr) 387{ 388 u8 ret; 389 __asm__ __volatile__(".machine push; \ 390 .machine power6; \ 391 lbzcix %0,0, %1; \ 392 .machine pop;" 393 : "=r" (ret) : "r" (paddr) : "memory"); 394 return ret; 395} 396 397static inline u16 __raw_rm_readw(volatile void __iomem *paddr) 398{ 399 u16 ret; 400 __asm__ __volatile__(".machine push; \ 401 .machine power6; \ 402 lhzcix %0,0, %1; \ 403 .machine pop;" 404 : "=r" (ret) : "r" (paddr) : "memory"); 405 return ret; 406} 407 408static inline u32 __raw_rm_readl(volatile void __iomem *paddr) 409{ 410 u32 ret; 411 __asm__ __volatile__(".machine push; \ 412 .machine power6; \ 413 lwzcix %0,0, %1; \ 414 .machine pop;" 415 : "=r" (ret) : "r" (paddr) : "memory"); 416 return ret; 417} 418 419static inline u64 __raw_rm_readq(volatile void __iomem *paddr) 420{ 421 u64 ret; 422 __asm__ __volatile__(".machine push; \ 423 .machine power6; \ 424 ldcix %0,0, %1; \ 425 .machine pop;" 426 : "=r" (ret) : "r" (paddr) : "memory"); 427 return ret; 428} 429#endif /* __powerpc64__ */ 430 431/* 432 * 433 * PCI PIO and MMIO accessors. 434 * 435 * 436 * On 32 bits, PIO operations have a recovery mechanism in case they trigger 437 * machine checks (which they occasionally do when probing non existing 438 * IO ports on some platforms, like PowerMac and 8xx). 439 * I always found it to be of dubious reliability and I am tempted to get 440 * rid of it one of these days. So if you think it's important to keep it, 441 * please voice up asap. We never had it for 64 bits and I do not intend 442 * to port it over 443 */ 444 445#ifdef CONFIG_PPC32 446 447#define __do_in_asm(name, op) \ 448static inline unsigned int name(unsigned int port) \ 449{ \ 450 unsigned int x; \ 451 __asm__ __volatile__( \ 452 "sync\n" \ 453 "0:" op " %0,0,%1\n" \ 454 "1: twi 0,%0,0\n" \ 455 "2: isync\n" \ 456 "3: nop\n" \ 457 "4:\n" \ 458 ".section .fixup,\"ax\"\n" \ 459 "5: li %0,-1\n" \ 460 " b 4b\n" \ 461 ".previous\n" \ 462 EX_TABLE(0b, 5b) \ 463 EX_TABLE(1b, 5b) \ 464 EX_TABLE(2b, 5b) \ 465 EX_TABLE(3b, 5b) \ 466 : "=&r" (x) \ 467 : "r" (port + _IO_BASE) \ 468 : "memory"); \ 469 return x; \ 470} 471 472#define __do_out_asm(name, op) \ 473static inline void name(unsigned int val, unsigned int port) \ 474{ \ 475 __asm__ __volatile__( \ 476 "sync\n" \ 477 "0:" op " %0,0,%1\n" \ 478 "1: sync\n" \ 479 "2:\n" \ 480 EX_TABLE(0b, 2b) \ 481 EX_TABLE(1b, 2b) \ 482 : : "r" (val), "r" (port + _IO_BASE) \ 483 : "memory"); \ 484} 485 486__do_in_asm(_rec_inb, "lbzx") 487__do_in_asm(_rec_inw, "lhbrx") 488__do_in_asm(_rec_inl, "lwbrx") 489__do_out_asm(_rec_outb, "stbx") 490__do_out_asm(_rec_outw, "sthbrx") 491__do_out_asm(_rec_outl, "stwbrx") 492 493#endif /* CONFIG_PPC32 */ 494 495/* The "__do_*" operations below provide the actual "base" implementation 496 * for each of the defined accessors. Some of them use the out_* functions 497 * directly, some of them still use EEH, though we might change that in the 498 * future. Those macros below provide the necessary argument swapping and 499 * handling of the IO base for PIO. 500 * 501 * They are themselves used by the macros that define the actual accessors 502 * and can be used by the hooks if any. 503 * 504 * Note that PIO operations are always defined in terms of their corresonding 505 * MMIO operations. That allows platforms like iSeries who want to modify the 506 * behaviour of both to only hook on the MMIO version and get both. It's also 507 * possible to hook directly at the toplevel PIO operation if they have to 508 * be handled differently 509 */ 510#define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) 511#define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) 512#define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) 513#define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) 514#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) 515#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) 516#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) 517 518#ifdef CONFIG_EEH 519#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) 520#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) 521#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) 522#define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) 523#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) 524#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) 525#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) 526#else /* CONFIG_EEH */ 527#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) 528#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) 529#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) 530#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) 531#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) 532#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) 533#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) 534#endif /* !defined(CONFIG_EEH) */ 535 536#ifdef CONFIG_PPC32 537#define __do_outb(val, port) _rec_outb(val, port) 538#define __do_outw(val, port) _rec_outw(val, port) 539#define __do_outl(val, port) _rec_outl(val, port) 540#define __do_inb(port) _rec_inb(port) 541#define __do_inw(port) _rec_inw(port) 542#define __do_inl(port) _rec_inl(port) 543#else /* CONFIG_PPC32 */ 544#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); 545#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); 546#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); 547#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); 548#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); 549#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); 550#endif /* !CONFIG_PPC32 */ 551 552#ifdef CONFIG_EEH 553#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) 554#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) 555#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) 556#else /* CONFIG_EEH */ 557#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) 558#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) 559#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) 560#endif /* !CONFIG_EEH */ 561#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) 562#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) 563#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) 564 565#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 566#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 567#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 568#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 569#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 570#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 571 572#define __do_memset_io(addr, c, n) \ 573 _memset_io(PCI_FIX_ADDR(addr), c, n) 574#define __do_memcpy_toio(dst, src, n) \ 575 _memcpy_toio(PCI_FIX_ADDR(dst), src, n) 576 577#ifdef CONFIG_EEH 578#define __do_memcpy_fromio(dst, src, n) \ 579 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) 580#else /* CONFIG_EEH */ 581#define __do_memcpy_fromio(dst, src, n) \ 582 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 583#endif /* !CONFIG_EEH */ 584 585#ifdef CONFIG_PPC_INDIRECT_PIO 586#define DEF_PCI_HOOK_pio(x) x 587#else 588#define DEF_PCI_HOOK_pio(x) NULL 589#endif 590 591#ifdef CONFIG_PPC_INDIRECT_MMIO 592#define DEF_PCI_HOOK_mem(x) x 593#else 594#define DEF_PCI_HOOK_mem(x) NULL 595#endif 596 597/* Structure containing all the hooks */ 598extern struct ppc_pci_io { 599 600#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; 601#define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; 602 603#include <asm/io-defs.h> 604 605#undef DEF_PCI_AC_RET 606#undef DEF_PCI_AC_NORET 607 608} ppc_pci_io; 609 610/* The inline wrappers */ 611#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ 612static inline ret name at \ 613{ \ 614 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 615 return ppc_pci_io.name al; \ 616 return __do_##name al; \ 617} 618 619#define DEF_PCI_AC_NORET(name, at, al, space, aa) \ 620static inline void name at \ 621{ \ 622 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 623 ppc_pci_io.name al; \ 624 else \ 625 __do_##name al; \ 626} 627 628#include <asm/io-defs.h> 629 630#undef DEF_PCI_AC_RET 631#undef DEF_PCI_AC_NORET 632 633/* Some drivers check for the presence of readq & writeq with 634 * a #ifdef, so we make them happy here. 635 */ 636#ifdef __powerpc64__ 637#define readq readq 638#define writeq writeq 639#endif 640 641/* 642 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 643 * access 644 */ 645#define xlate_dev_mem_ptr(p) __va(p) 646 647/* 648 * Convert a virtual cached pointer to an uncached pointer 649 */ 650#define xlate_dev_kmem_ptr(p) p 651 652/* 653 * We don't do relaxed operations yet, at least not with this semantic 654 */ 655#define readb_relaxed(addr) readb(addr) 656#define readw_relaxed(addr) readw(addr) 657#define readl_relaxed(addr) readl(addr) 658#define readq_relaxed(addr) readq(addr) 659#define writeb_relaxed(v, addr) writeb(v, addr) 660#define writew_relaxed(v, addr) writew(v, addr) 661#define writel_relaxed(v, addr) writel(v, addr) 662#define writeq_relaxed(v, addr) writeq(v, addr) 663 664#include <asm-generic/iomap.h> 665 666static inline void iosync(void) 667{ 668 __asm__ __volatile__ ("sync" : : : "memory"); 669} 670 671/* Enforce in-order execution of data I/O. 672 * No distinction between read/write on PPC; use eieio for all three. 673 * Those are fairly week though. They don't provide a barrier between 674 * MMIO and cacheable storage nor do they provide a barrier vs. locks, 675 * they only provide barriers between 2 __raw MMIO operations and 676 * possibly break write combining. 677 */ 678#define iobarrier_rw() eieio() 679#define iobarrier_r() eieio() 680#define iobarrier_w() eieio() 681 682 683/* 684 * output pause versions need a delay at least for the 685 * w83c105 ide controller in a p610. 686 */ 687#define inb_p(port) inb(port) 688#define outb_p(val, port) (udelay(1), outb((val), (port))) 689#define inw_p(port) inw(port) 690#define outw_p(val, port) (udelay(1), outw((val), (port))) 691#define inl_p(port) inl(port) 692#define outl_p(val, port) (udelay(1), outl((val), (port))) 693 694 695#define IO_SPACE_LIMIT ~(0UL) 696 697 698/** 699 * ioremap - map bus memory into CPU space 700 * @address: bus address of the memory 701 * @size: size of the resource to map 702 * 703 * ioremap performs a platform specific sequence of operations to 704 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 705 * writew/writel functions and the other mmio helpers. The returned 706 * address is not guaranteed to be usable directly as a virtual 707 * address. 708 * 709 * We provide a few variations of it: 710 * 711 * * ioremap is the standard one and provides non-cacheable guarded mappings 712 * and can be hooked by the platform via ppc_md 713 * 714 * * ioremap_prot allows to specify the page flags as an argument and can 715 * also be hooked by the platform via ppc_md. 716 * 717 * * ioremap_wc enables write combining 718 * 719 * * ioremap_wt enables write through 720 * 721 * * ioremap_coherent maps coherent cached memory 722 * 723 * * iounmap undoes such a mapping and can be hooked 724 * 725 * * __ioremap_caller is the same as above but takes an explicit caller 726 * reference rather than using __builtin_return_address(0) 727 * 728 */ 729extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 730extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, 731 unsigned long flags); 732extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); 733void __iomem *ioremap_wt(phys_addr_t address, unsigned long size); 734void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size); 735#define ioremap_uc(addr, size) ioremap((addr), (size)) 736#define ioremap_cache(addr, size) \ 737 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL)) 738 739extern void iounmap(volatile void __iomem *addr); 740 741void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size); 742 743int early_ioremap_range(unsigned long ea, phys_addr_t pa, 744 unsigned long size, pgprot_t prot); 745void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size, 746 pgprot_t prot, void *caller); 747 748extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, 749 pgprot_t prot, void *caller); 750 751/* 752 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation 753 * which needs some additional definitions here. They basically allow PIO 754 * space overall to be 1GB. This will work as long as we never try to use 755 * iomap to map MMIO below 1GB which should be fine on ppc64 756 */ 757#define HAVE_ARCH_PIO_SIZE 1 758#define PIO_OFFSET 0x00000000UL 759#define PIO_MASK (FULL_IO_SIZE - 1) 760#define PIO_RESERVED (FULL_IO_SIZE) 761 762#define mmio_read16be(addr) readw_be(addr) 763#define mmio_read32be(addr) readl_be(addr) 764#define mmio_read64be(addr) readq_be(addr) 765#define mmio_write16be(val, addr) writew_be(val, addr) 766#define mmio_write32be(val, addr) writel_be(val, addr) 767#define mmio_write64be(val, addr) writeq_be(val, addr) 768#define mmio_insb(addr, dst, count) readsb(addr, dst, count) 769#define mmio_insw(addr, dst, count) readsw(addr, dst, count) 770#define mmio_insl(addr, dst, count) readsl(addr, dst, count) 771#define mmio_outsb(addr, src, count) writesb(addr, src, count) 772#define mmio_outsw(addr, src, count) writesw(addr, src, count) 773#define mmio_outsl(addr, src, count) writesl(addr, src, count) 774 775/** 776 * virt_to_phys - map virtual addresses to physical 777 * @address: address to remap 778 * 779 * The returned physical address is the physical (CPU) mapping for 780 * the memory address given. It is only valid to use this function on 781 * addresses directly mapped or allocated via kmalloc. 782 * 783 * This function does not give bus mappings for DMA transfers. In 784 * almost all conceivable cases a device driver should not be using 785 * this function 786 */ 787static inline unsigned long virt_to_phys(volatile void * address) 788{ 789 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address)); 790 791 return __pa((unsigned long)address); 792} 793 794/** 795 * phys_to_virt - map physical address to virtual 796 * @address: address to remap 797 * 798 * The returned virtual address is a current CPU mapping for 799 * the memory address given. It is only valid to use this function on 800 * addresses that have a kernel mapping 801 * 802 * This function does not handle bus mappings for DMA transfers. In 803 * almost all conceivable cases a device driver should not be using 804 * this function 805 */ 806static inline void * phys_to_virt(unsigned long address) 807{ 808 return (void *)__va(address); 809} 810 811/* 812 * Change "struct page" to physical address. 813 */ 814static inline phys_addr_t page_to_phys(struct page *page) 815{ 816 unsigned long pfn = page_to_pfn(page); 817 818 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn)); 819 820 return PFN_PHYS(pfn); 821} 822 823/* 824 * 32 bits still uses virt_to_bus() for it's implementation of DMA 825 * mappings se we have to keep it defined here. We also have some old 826 * drivers (shame shame shame) that use bus_to_virt() and haven't been 827 * fixed yet so I need to define it here. 828 */ 829#ifdef CONFIG_PPC32 830 831static inline unsigned long virt_to_bus(volatile void * address) 832{ 833 if (address == NULL) 834 return 0; 835 return __pa(address) + PCI_DRAM_OFFSET; 836} 837 838static inline void * bus_to_virt(unsigned long address) 839{ 840 if (address == 0) 841 return NULL; 842 return __va(address - PCI_DRAM_OFFSET); 843} 844 845#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 846 847#endif /* CONFIG_PPC32 */ 848 849/* access ports */ 850#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) 851#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) 852 853#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) 854#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) 855 856#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) 857#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) 858 859/* Clear and set bits in one shot. These macros can be used to clear and 860 * set multiple bits in a register using a single read-modify-write. These 861 * macros can also be used to set a multiple-bit bit pattern using a mask, 862 * by specifying the mask in the 'clear' parameter and the new bit pattern 863 * in the 'set' parameter. 864 */ 865 866#define clrsetbits(type, addr, clear, set) \ 867 out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) 868 869#ifdef __powerpc64__ 870#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) 871#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) 872#endif 873 874#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) 875#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) 876 877#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) 878#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) 879 880#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) 881 882#endif /* __KERNEL__ */ 883 884#endif /* _ASM_POWERPC_IO_H */ 885