1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5#include <asm-generic/pgtable-nop4d.h> 6 7#ifndef __ASSEMBLY__ 8#include <linux/mmdebug.h> 9#include <linux/bug.h> 10#include <linux/sizes.h> 11#endif 12 13/* 14 * Common bits between hash and Radix page table 15 */ 16#define _PAGE_BIT_SWAP_TYPE 0 17 18#define _PAGE_EXEC 0x00001 /* execute permission */ 19#define _PAGE_WRITE 0x00002 /* write access allowed */ 20#define _PAGE_READ 0x00004 /* read access allowed */ 21#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 22#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 23#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 24#define _PAGE_SAO 0x00010 /* Strong access order */ 25#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 26#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 27#define _PAGE_DIRTY 0x00080 /* C: page changed */ 28#define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 29/* 30 * Software bits 31 */ 32#define _RPAGE_SW0 0x2000000000000000UL 33#define _RPAGE_SW1 0x00800 34#define _RPAGE_SW2 0x00400 35#define _RPAGE_SW3 0x00200 36#define _RPAGE_RSV1 0x00040UL 37 38#define _RPAGE_PKEY_BIT4 0x1000000000000000UL 39#define _RPAGE_PKEY_BIT3 0x0800000000000000UL 40#define _RPAGE_PKEY_BIT2 0x0400000000000000UL 41#define _RPAGE_PKEY_BIT1 0x0200000000000000UL 42#define _RPAGE_PKEY_BIT0 0x0100000000000000UL 43 44#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 45#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 46/* 47 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 48 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 49 * differentiate between two use a SW field when invalidating. 50 * 51 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 52 * 53 * This is used only when _PAGE_PRESENT is cleared. 54 */ 55#define _PAGE_INVALID _RPAGE_SW0 56 57/* 58 * Top and bottom bits of RPN which can be used by hash 59 * translation mode, because we expect them to be zero 60 * otherwise. 61 */ 62#define _RPAGE_RPN0 0x01000 63#define _RPAGE_RPN1 0x02000 64#define _RPAGE_RPN43 0x0080000000000000UL 65#define _RPAGE_RPN42 0x0040000000000000UL 66#define _RPAGE_RPN41 0x0020000000000000UL 67 68/* Max physical address bit as per radix table */ 69#define _RPAGE_PA_MAX 56 70 71/* 72 * Max physical address bit we will use for now. 73 * 74 * This is mostly a hardware limitation and for now Power9 has 75 * a 51 bit limit. 76 * 77 * This is different from the number of physical bit required to address 78 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 79 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 80 * number of sections we can support (SECTIONS_SHIFT). 81 * 82 * This is different from Radix page table limitation above and 83 * should always be less than that. The limit is done such that 84 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 85 * for hash linux page table specific bits. 86 * 87 * In order to be compatible with future hardware generations we keep 88 * some offsets and limit this for now to 53 89 */ 90#define _PAGE_PA_MAX 53 91 92#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 93#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 94#define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 95 96/* 97 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 98 * Instead of fixing all of them, add an alternate define which 99 * maps CI pte mapping. 100 */ 101#define _PAGE_NO_CACHE _PAGE_TOLERANT 102/* 103 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 104 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 105 * and every thing below PAGE_SHIFT; 106 */ 107#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 108/* 109 * set of bits not changed in pmd_modify. Even though we have hash specific bits 110 * in here, on radix we expect them to be zero. 111 */ 112#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 113 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 114 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 115/* 116 * user access blocked by key 117 */ 118#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 119#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 120#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 121 _PAGE_RW | _PAGE_EXEC) 122/* 123 * _PAGE_CHG_MASK masks of bits that are to be preserved across 124 * pgprot changes 125 */ 126#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 127 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 128 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 129 130/* 131 * We define 2 sets of base prot bits, one for basic pages (ie, 132 * cacheable kernel and user pages) and one for non cacheable 133 * pages. We always set _PAGE_COHERENT when SMP is enabled or 134 * the processor might need it for DMA coherency. 135 */ 136#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 137#define _PAGE_BASE (_PAGE_BASE_NC) 138 139/* Permission masks used to generate the __P and __S table, 140 * 141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 142 * 143 * Write permissions imply read permissions for now (we could make write-only 144 * pages on BookE but we don't bother for now). Execute permission control is 145 * possible on platforms that define _PAGE_EXEC 146 */ 147#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 148#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 149#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 150#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 151#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 152#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 153#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 155/* Permission masks used for kernel mappings */ 156#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 157#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 158 _PAGE_TOLERANT) 159#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 160 _PAGE_NON_IDEMPOTENT) 161#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 162#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 163#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 164 165/* 166 * Protection used for kernel text. We want the debuggers to be able to 167 * set breakpoints anywhere, so don't write protect the kernel text 168 * on platforms where such control is possible. 169 */ 170#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 171 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 172#define PAGE_KERNEL_TEXT PAGE_KERNEL_X 173#else 174#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 175#endif 176 177/* Make modules code happy. We don't set RO yet */ 178#define PAGE_KERNEL_EXEC PAGE_KERNEL_X 179#define PAGE_AGP (PAGE_KERNEL_NC) 180 181#ifndef __ASSEMBLY__ 182/* 183 * page table defines 184 */ 185extern unsigned long __pte_index_size; 186extern unsigned long __pmd_index_size; 187extern unsigned long __pud_index_size; 188extern unsigned long __pgd_index_size; 189extern unsigned long __pud_cache_index; 190#define PTE_INDEX_SIZE __pte_index_size 191#define PMD_INDEX_SIZE __pmd_index_size 192#define PUD_INDEX_SIZE __pud_index_size 193#define PGD_INDEX_SIZE __pgd_index_size 194/* pmd table use page table fragments */ 195#define PMD_CACHE_INDEX 0 196#define PUD_CACHE_INDEX __pud_cache_index 197/* 198 * Because of use of pte fragments and THP, size of page table 199 * are not always derived out of index size above. 200 */ 201extern unsigned long __pte_table_size; 202extern unsigned long __pmd_table_size; 203extern unsigned long __pud_table_size; 204extern unsigned long __pgd_table_size; 205#define PTE_TABLE_SIZE __pte_table_size 206#define PMD_TABLE_SIZE __pmd_table_size 207#define PUD_TABLE_SIZE __pud_table_size 208#define PGD_TABLE_SIZE __pgd_table_size 209 210extern unsigned long __pmd_val_bits; 211extern unsigned long __pud_val_bits; 212extern unsigned long __pgd_val_bits; 213#define PMD_VAL_BITS __pmd_val_bits 214#define PUD_VAL_BITS __pud_val_bits 215#define PGD_VAL_BITS __pgd_val_bits 216 217extern unsigned long __pte_frag_nr; 218#define PTE_FRAG_NR __pte_frag_nr 219extern unsigned long __pte_frag_size_shift; 220#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 221#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 222 223extern unsigned long __pmd_frag_nr; 224#define PMD_FRAG_NR __pmd_frag_nr 225extern unsigned long __pmd_frag_size_shift; 226#define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 227#define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 228 229#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 230#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 231#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 232#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 233 234/* PMD_SHIFT determines what a second-level page table entry can map */ 235#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 236#define PMD_SIZE (1UL << PMD_SHIFT) 237#define PMD_MASK (~(PMD_SIZE-1)) 238 239/* PUD_SHIFT determines what a third-level page table entry can map */ 240#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 241#define PUD_SIZE (1UL << PUD_SHIFT) 242#define PUD_MASK (~(PUD_SIZE-1)) 243 244/* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 245#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 246#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 247#define PGDIR_MASK (~(PGDIR_SIZE-1)) 248 249/* Bits to mask out from a PMD to get to the PTE page */ 250#define PMD_MASKED_BITS 0xc0000000000000ffUL 251/* Bits to mask out from a PUD to get to the PMD page */ 252#define PUD_MASKED_BITS 0xc0000000000000ffUL 253/* Bits to mask out from a PGD to get to the PUD page */ 254#define P4D_MASKED_BITS 0xc0000000000000ffUL 255 256/* 257 * Used as an indicator for rcu callback functions 258 */ 259enum pgtable_index { 260 PTE_INDEX = 0, 261 PMD_INDEX, 262 PUD_INDEX, 263 PGD_INDEX, 264 /* 265 * Below are used with 4k page size and hugetlb 266 */ 267 HTLB_16M_INDEX, 268 HTLB_16G_INDEX, 269}; 270 271extern unsigned long __vmalloc_start; 272extern unsigned long __vmalloc_end; 273#define VMALLOC_START __vmalloc_start 274#define VMALLOC_END __vmalloc_end 275 276static inline unsigned int ioremap_max_order(void) 277{ 278 if (radix_enabled()) 279 return PUD_SHIFT; 280 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 281} 282#define IOREMAP_MAX_ORDER ioremap_max_order() 283 284extern unsigned long __kernel_virt_start; 285extern unsigned long __kernel_io_start; 286extern unsigned long __kernel_io_end; 287#define KERN_VIRT_START __kernel_virt_start 288#define KERN_IO_START __kernel_io_start 289#define KERN_IO_END __kernel_io_end 290 291extern struct page *vmemmap; 292extern unsigned long pci_io_base; 293#endif /* __ASSEMBLY__ */ 294 295#include <asm/book3s/64/hash.h> 296#include <asm/book3s/64/radix.h> 297 298#if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 299#define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 300#else 301#define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 302#endif 303 304 305#ifdef CONFIG_PPC_64K_PAGES 306#include <asm/book3s/64/pgtable-64k.h> 307#else 308#include <asm/book3s/64/pgtable-4k.h> 309#endif 310 311#include <asm/barrier.h> 312/* 313 * IO space itself carved into the PIO region (ISA and PHB IO space) and 314 * the ioremap space 315 * 316 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 317 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 318 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 319 */ 320#define FULL_IO_SIZE 0x80000000ul 321#define ISA_IO_BASE (KERN_IO_START) 322#define ISA_IO_END (KERN_IO_START + 0x10000ul) 323#define PHB_IO_BASE (ISA_IO_END) 324#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 325#define IOREMAP_BASE (PHB_IO_END) 326#define IOREMAP_START (ioremap_bot) 327#define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 328#define FIXADDR_SIZE SZ_32M 329 330/* Advertise special mapping type for AGP */ 331#define HAVE_PAGE_AGP 332 333#ifndef __ASSEMBLY__ 334 335/* 336 * This is the default implementation of various PTE accessors, it's 337 * used in all cases except Book3S with 64K pages where we have a 338 * concept of sub-pages 339 */ 340#ifndef __real_pte 341 342#define __real_pte(e, p, o) ((real_pte_t){(e)}) 343#define __rpte_to_pte(r) ((r).pte) 344#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 345 346#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 347 do { \ 348 index = 0; \ 349 shift = mmu_psize_defs[psize].shift; \ 350 351#define pte_iterate_hashed_end() } while(0) 352 353/* 354 * We expect this to be called only for user addresses or kernel virtual 355 * addresses other than the linear mapping. 356 */ 357#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 358 359#endif /* __real_pte */ 360 361static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 362 pte_t *ptep, unsigned long clr, 363 unsigned long set, int huge) 364{ 365 if (radix_enabled()) 366 return radix__pte_update(mm, addr, ptep, clr, set, huge); 367 return hash__pte_update(mm, addr, ptep, clr, set, huge); 368} 369/* 370 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 371 * We currently remove entries from the hashtable regardless of whether 372 * the entry was young or dirty. 373 * 374 * We should be more intelligent about this but for the moment we override 375 * these functions and force a tlb flush unconditionally 376 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 377 * function for both hash and radix. 378 */ 379static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 380 unsigned long addr, pte_t *ptep) 381{ 382 unsigned long old; 383 384 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 385 return 0; 386 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 387 return (old & _PAGE_ACCESSED) != 0; 388} 389 390#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 391#define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 392({ \ 393 int __r; \ 394 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 395 __r; \ 396}) 397 398static inline int __pte_write(pte_t pte) 399{ 400 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 401} 402 403#ifdef CONFIG_NUMA_BALANCING 404#define pte_savedwrite pte_savedwrite 405static inline bool pte_savedwrite(pte_t pte) 406{ 407 /* 408 * Saved write ptes are prot none ptes that doesn't have 409 * privileged bit sit. We mark prot none as one which has 410 * present and pviliged bit set and RWX cleared. To mark 411 * protnone which used to have _PAGE_WRITE set we clear 412 * the privileged bit. 413 */ 414 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 415} 416#else 417#define pte_savedwrite pte_savedwrite 418static inline bool pte_savedwrite(pte_t pte) 419{ 420 return false; 421} 422#endif 423 424static inline int pte_write(pte_t pte) 425{ 426 return __pte_write(pte) || pte_savedwrite(pte); 427} 428 429static inline int pte_read(pte_t pte) 430{ 431 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 432} 433 434#define __HAVE_ARCH_PTEP_SET_WRPROTECT 435static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 436 pte_t *ptep) 437{ 438 if (__pte_write(*ptep)) 439 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 440 else if (unlikely(pte_savedwrite(*ptep))) 441 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 442} 443 444#define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 445static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 446 unsigned long addr, pte_t *ptep) 447{ 448 /* 449 * We should not find protnone for hugetlb, but this complete the 450 * interface. 451 */ 452 if (__pte_write(*ptep)) 453 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 454 else if (unlikely(pte_savedwrite(*ptep))) 455 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 456} 457 458#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 459static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 460 unsigned long addr, pte_t *ptep) 461{ 462 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 463 return __pte(old); 464} 465 466#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 467static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 468 unsigned long addr, 469 pte_t *ptep, int full) 470{ 471 if (full && radix_enabled()) { 472 /* 473 * We know that this is a full mm pte clear and 474 * hence can be sure there is no parallel set_pte. 475 */ 476 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 477 } 478 return ptep_get_and_clear(mm, addr, ptep); 479} 480 481 482static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 483 pte_t * ptep) 484{ 485 pte_update(mm, addr, ptep, ~0UL, 0, 0); 486} 487 488static inline int pte_dirty(pte_t pte) 489{ 490 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 491} 492 493static inline int pte_young(pte_t pte) 494{ 495 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 496} 497 498static inline int pte_special(pte_t pte) 499{ 500 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 501} 502 503static inline bool pte_exec(pte_t pte) 504{ 505 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 506} 507 508 509#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 510static inline bool pte_soft_dirty(pte_t pte) 511{ 512 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 513} 514 515static inline pte_t pte_mksoft_dirty(pte_t pte) 516{ 517 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 518} 519 520static inline pte_t pte_clear_soft_dirty(pte_t pte) 521{ 522 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 523} 524#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 525 526#ifdef CONFIG_NUMA_BALANCING 527static inline int pte_protnone(pte_t pte) 528{ 529 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 530 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 531} 532 533#define pte_mk_savedwrite pte_mk_savedwrite 534static inline pte_t pte_mk_savedwrite(pte_t pte) 535{ 536 /* 537 * Used by Autonuma subsystem to preserve the write bit 538 * while marking the pte PROT_NONE. Only allow this 539 * on PROT_NONE pte 540 */ 541 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 542 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 543 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 544} 545 546#define pte_clear_savedwrite pte_clear_savedwrite 547static inline pte_t pte_clear_savedwrite(pte_t pte) 548{ 549 /* 550 * Used by KSM subsystem to make a protnone pte readonly. 551 */ 552 VM_BUG_ON(!pte_protnone(pte)); 553 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 554} 555#else 556#define pte_clear_savedwrite pte_clear_savedwrite 557static inline pte_t pte_clear_savedwrite(pte_t pte) 558{ 559 VM_WARN_ON(1); 560 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 561} 562#endif /* CONFIG_NUMA_BALANCING */ 563 564static inline bool pte_hw_valid(pte_t pte) 565{ 566 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 567 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 568} 569 570static inline int pte_present(pte_t pte) 571{ 572 /* 573 * A pte is considerent present if _PAGE_PRESENT is set. 574 * We also need to consider the pte present which is marked 575 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 576 * if we find _PAGE_PRESENT cleared. 577 */ 578 579 if (pte_hw_valid(pte)) 580 return true; 581 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 582 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 583} 584 585#ifdef CONFIG_PPC_MEM_KEYS 586extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 587#else 588static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 589{ 590 return true; 591} 592#endif /* CONFIG_PPC_MEM_KEYS */ 593 594static inline bool pte_user(pte_t pte) 595{ 596 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 597} 598 599#define pte_access_permitted pte_access_permitted 600static inline bool pte_access_permitted(pte_t pte, bool write) 601{ 602 /* 603 * _PAGE_READ is needed for any access and will be 604 * cleared for PROT_NONE 605 */ 606 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 607 return false; 608 609 if (write && !pte_write(pte)) 610 return false; 611 612 return arch_pte_access_permitted(pte_val(pte), write, 0); 613} 614 615/* 616 * Conversion functions: convert a page and protection to a page entry, 617 * and a page entry and page directory to the page they refer to. 618 * 619 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 620 * long for now. 621 */ 622static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 623{ 624 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 625 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 626 627 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 628} 629 630static inline unsigned long pte_pfn(pte_t pte) 631{ 632 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 633} 634 635/* Generic modifiers for PTE bits */ 636static inline pte_t pte_wrprotect(pte_t pte) 637{ 638 if (unlikely(pte_savedwrite(pte))) 639 return pte_clear_savedwrite(pte); 640 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 641} 642 643static inline pte_t pte_exprotect(pte_t pte) 644{ 645 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 646} 647 648static inline pte_t pte_mkclean(pte_t pte) 649{ 650 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 651} 652 653static inline pte_t pte_mkold(pte_t pte) 654{ 655 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 656} 657 658static inline pte_t pte_mkexec(pte_t pte) 659{ 660 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 661} 662 663static inline pte_t pte_mkwrite(pte_t pte) 664{ 665 /* 666 * write implies read, hence set both 667 */ 668 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 669} 670 671static inline pte_t pte_mkdirty(pte_t pte) 672{ 673 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 674} 675 676static inline pte_t pte_mkyoung(pte_t pte) 677{ 678 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 679} 680 681static inline pte_t pte_mkspecial(pte_t pte) 682{ 683 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 684} 685 686static inline pte_t pte_mkhuge(pte_t pte) 687{ 688 return pte; 689} 690 691static inline pte_t pte_mkdevmap(pte_t pte) 692{ 693 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 694} 695 696static inline pte_t pte_mkprivileged(pte_t pte) 697{ 698 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 699} 700 701static inline pte_t pte_mkuser(pte_t pte) 702{ 703 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 704} 705 706/* 707 * This is potentially called with a pmd as the argument, in which case it's not 708 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 709 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 710 * use in page directory entries (ie. non-ptes). 711 */ 712static inline int pte_devmap(pte_t pte) 713{ 714 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 715 716 return (pte_raw(pte) & mask) == mask; 717} 718 719static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 720{ 721 /* FIXME!! check whether this need to be a conditional */ 722 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 723 cpu_to_be64(pgprot_val(newprot))); 724} 725 726/* Encode and de-code a swap entry */ 727#define MAX_SWAPFILES_CHECK() do { \ 728 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 729 /* \ 730 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 731 * We filter HPTEFLAGS on set_pte. \ 732 */ \ 733 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 734 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 735 } while (0) 736 737#define SWP_TYPE_BITS 5 738#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 739 & ((1UL << SWP_TYPE_BITS) - 1)) 740#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 741#define __swp_entry(type, offset) ((swp_entry_t) { \ 742 ((type) << _PAGE_BIT_SWAP_TYPE) \ 743 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 744/* 745 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 746 * swap type and offset we get from swap and convert that to pte to find a 747 * matching pte in linux page table. 748 * Clear bits not found in swap entries here. 749 */ 750#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 751#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 752#define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 753#define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 754 755#ifdef CONFIG_MEM_SOFT_DIRTY 756#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 757#else 758#define _PAGE_SWP_SOFT_DIRTY 0UL 759#endif /* CONFIG_MEM_SOFT_DIRTY */ 760 761#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 762static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 763{ 764 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 765} 766 767static inline bool pte_swp_soft_dirty(pte_t pte) 768{ 769 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 770} 771 772static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 773{ 774 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 775} 776#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 777 778static inline bool check_pte_access(unsigned long access, unsigned long ptev) 779{ 780 /* 781 * This check for _PAGE_RWX and _PAGE_PRESENT bits 782 */ 783 if (access & ~ptev) 784 return false; 785 /* 786 * This check for access to privilege space 787 */ 788 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 789 return false; 790 791 return true; 792} 793/* 794 * Generic functions with hash/radix callbacks 795 */ 796 797static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 798 pte_t *ptep, pte_t entry, 799 unsigned long address, 800 int psize) 801{ 802 if (radix_enabled()) 803 return radix__ptep_set_access_flags(vma, ptep, entry, 804 address, psize); 805 return hash__ptep_set_access_flags(ptep, entry); 806} 807 808#define __HAVE_ARCH_PTE_SAME 809static inline int pte_same(pte_t pte_a, pte_t pte_b) 810{ 811 if (radix_enabled()) 812 return radix__pte_same(pte_a, pte_b); 813 return hash__pte_same(pte_a, pte_b); 814} 815 816static inline int pte_none(pte_t pte) 817{ 818 if (radix_enabled()) 819 return radix__pte_none(pte); 820 return hash__pte_none(pte); 821} 822 823static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 824 pte_t *ptep, pte_t pte, int percpu) 825{ 826 827 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 828 /* 829 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 830 * in all the callers. 831 */ 832 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 833 834 if (radix_enabled()) 835 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 836 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 837} 838 839#define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 840 841#define pgprot_noncached pgprot_noncached 842static inline pgprot_t pgprot_noncached(pgprot_t prot) 843{ 844 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 845 _PAGE_NON_IDEMPOTENT); 846} 847 848#define pgprot_noncached_wc pgprot_noncached_wc 849static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 850{ 851 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 852 _PAGE_TOLERANT); 853} 854 855#define pgprot_cached pgprot_cached 856static inline pgprot_t pgprot_cached(pgprot_t prot) 857{ 858 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 859} 860 861#define pgprot_writecombine pgprot_writecombine 862static inline pgprot_t pgprot_writecombine(pgprot_t prot) 863{ 864 return pgprot_noncached_wc(prot); 865} 866/* 867 * check a pte mapping have cache inhibited property 868 */ 869static inline bool pte_ci(pte_t pte) 870{ 871 __be64 pte_v = pte_raw(pte); 872 873 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 874 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 875 return true; 876 return false; 877} 878 879static inline void pmd_clear(pmd_t *pmdp) 880{ 881 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 882 /* 883 * Don't use this if we can possibly have a hash page table 884 * entry mapping this. 885 */ 886 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 887 } 888 *pmdp = __pmd(0); 889} 890 891static inline int pmd_none(pmd_t pmd) 892{ 893 return !pmd_raw(pmd); 894} 895 896static inline int pmd_present(pmd_t pmd) 897{ 898 /* 899 * A pmd is considerent present if _PAGE_PRESENT is set. 900 * We also need to consider the pmd present which is marked 901 * invalid during a split. Hence we look for _PAGE_INVALID 902 * if we find _PAGE_PRESENT cleared. 903 */ 904 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 905 return true; 906 907 return false; 908} 909 910static inline int pmd_is_serializing(pmd_t pmd) 911{ 912 /* 913 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 914 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 915 * 916 * This condition may also occur when flushing a pmd while flushing 917 * it (see ptep_modify_prot_start), so callers must ensure this 918 * case is fine as well. 919 */ 920 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 921 cpu_to_be64(_PAGE_INVALID)) 922 return true; 923 924 return false; 925} 926 927static inline int pmd_bad(pmd_t pmd) 928{ 929 if (radix_enabled()) 930 return radix__pmd_bad(pmd); 931 return hash__pmd_bad(pmd); 932} 933 934static inline void pud_clear(pud_t *pudp) 935{ 936 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 937 /* 938 * Don't use this if we can possibly have a hash page table 939 * entry mapping this. 940 */ 941 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 942 } 943 *pudp = __pud(0); 944} 945 946static inline int pud_none(pud_t pud) 947{ 948 return !pud_raw(pud); 949} 950 951static inline int pud_present(pud_t pud) 952{ 953 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 954} 955 956extern struct page *pud_page(pud_t pud); 957extern struct page *pmd_page(pmd_t pmd); 958static inline pte_t pud_pte(pud_t pud) 959{ 960 return __pte_raw(pud_raw(pud)); 961} 962 963static inline pud_t pte_pud(pte_t pte) 964{ 965 return __pud_raw(pte_raw(pte)); 966} 967#define pud_write(pud) pte_write(pud_pte(pud)) 968 969static inline int pud_bad(pud_t pud) 970{ 971 if (radix_enabled()) 972 return radix__pud_bad(pud); 973 return hash__pud_bad(pud); 974} 975 976#define pud_access_permitted pud_access_permitted 977static inline bool pud_access_permitted(pud_t pud, bool write) 978{ 979 return pte_access_permitted(pud_pte(pud), write); 980} 981 982#define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 983static inline __be64 p4d_raw(p4d_t x) 984{ 985 return pgd_raw(x.pgd); 986} 987 988#define p4d_write(p4d) pte_write(p4d_pte(p4d)) 989 990static inline void p4d_clear(p4d_t *p4dp) 991{ 992 *p4dp = __p4d(0); 993} 994 995static inline int p4d_none(p4d_t p4d) 996{ 997 return !p4d_raw(p4d); 998} 999 1000static inline int p4d_present(p4d_t p4d) 1001{ 1002 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 1003} 1004 1005static inline pte_t p4d_pte(p4d_t p4d) 1006{ 1007 return __pte_raw(p4d_raw(p4d)); 1008} 1009 1010static inline p4d_t pte_p4d(pte_t pte) 1011{ 1012 return __p4d_raw(pte_raw(pte)); 1013} 1014 1015static inline int p4d_bad(p4d_t p4d) 1016{ 1017 if (radix_enabled()) 1018 return radix__p4d_bad(p4d); 1019 return hash__p4d_bad(p4d); 1020} 1021 1022#define p4d_access_permitted p4d_access_permitted 1023static inline bool p4d_access_permitted(p4d_t p4d, bool write) 1024{ 1025 return pte_access_permitted(p4d_pte(p4d), write); 1026} 1027 1028extern struct page *p4d_page(p4d_t p4d); 1029 1030/* Pointers in the page table tree are physical addresses */ 1031#define __pgtable_ptr_val(ptr) __pa(ptr) 1032 1033static inline pud_t *p4d_pgtable(p4d_t p4d) 1034{ 1035 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); 1036} 1037 1038static inline pmd_t *pud_pgtable(pud_t pud) 1039{ 1040 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); 1041} 1042 1043#define pte_ERROR(e) \ 1044 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1045#define pmd_ERROR(e) \ 1046 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1047#define pud_ERROR(e) \ 1048 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1049#define pgd_ERROR(e) \ 1050 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1051 1052static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1053{ 1054 if (radix_enabled()) { 1055#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1056 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1057 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1058#endif 1059 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1060 } 1061 return hash__map_kernel_page(ea, pa, prot); 1062} 1063 1064void unmap_kernel_page(unsigned long va); 1065 1066static inline int __meminit vmemmap_create_mapping(unsigned long start, 1067 unsigned long page_size, 1068 unsigned long phys) 1069{ 1070 if (radix_enabled()) 1071 return radix__vmemmap_create_mapping(start, page_size, phys); 1072 return hash__vmemmap_create_mapping(start, page_size, phys); 1073} 1074 1075#ifdef CONFIG_MEMORY_HOTPLUG 1076static inline void vmemmap_remove_mapping(unsigned long start, 1077 unsigned long page_size) 1078{ 1079 if (radix_enabled()) 1080 return radix__vmemmap_remove_mapping(start, page_size); 1081 return hash__vmemmap_remove_mapping(start, page_size); 1082} 1083#endif 1084 1085static inline pte_t pmd_pte(pmd_t pmd) 1086{ 1087 return __pte_raw(pmd_raw(pmd)); 1088} 1089 1090static inline pmd_t pte_pmd(pte_t pte) 1091{ 1092 return __pmd_raw(pte_raw(pte)); 1093} 1094 1095static inline pte_t *pmdp_ptep(pmd_t *pmd) 1096{ 1097 return (pte_t *)pmd; 1098} 1099#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1100#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1101#define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1102#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1103#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1104#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1105#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1106#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1107#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1108#define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1109#define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1110 1111#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1112#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1113#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1114#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1115 1116#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1117#define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1118#define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1119#define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1120#endif 1121#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1122 1123#ifdef CONFIG_NUMA_BALANCING 1124static inline int pmd_protnone(pmd_t pmd) 1125{ 1126 return pte_protnone(pmd_pte(pmd)); 1127} 1128#endif /* CONFIG_NUMA_BALANCING */ 1129 1130#define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1131#define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1132#define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1133 1134#define pmd_access_permitted pmd_access_permitted 1135static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1136{ 1137 /* 1138 * pmdp_invalidate sets this combination (which is not caught by 1139 * !pte_present() check in pte_access_permitted), to prevent 1140 * lock-free lookups, as part of the serialize_against_pte_lookup() 1141 * synchronisation. 1142 * 1143 * This also catches the case where the PTE's hardware PRESENT bit is 1144 * cleared while TLB is flushed, which is suboptimal but should not 1145 * be frequent. 1146 */ 1147 if (pmd_is_serializing(pmd)) 1148 return false; 1149 1150 return pte_access_permitted(pmd_pte(pmd), write); 1151} 1152 1153#ifdef CONFIG_TRANSPARENT_HUGEPAGE 1154extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1155extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1156extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1157extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1158 pmd_t *pmdp, pmd_t pmd); 1159static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1160 unsigned long addr, pmd_t *pmd) 1161{ 1162} 1163 1164extern int hash__has_transparent_hugepage(void); 1165static inline int has_transparent_hugepage(void) 1166{ 1167 if (radix_enabled()) 1168 return radix__has_transparent_hugepage(); 1169 return hash__has_transparent_hugepage(); 1170} 1171#define has_transparent_hugepage has_transparent_hugepage 1172 1173static inline unsigned long 1174pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1175 unsigned long clr, unsigned long set) 1176{ 1177 if (radix_enabled()) 1178 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1179 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1180} 1181 1182/* 1183 * returns true for pmd migration entries, THP, devmap, hugetlb 1184 * But compile time dependent on THP config 1185 */ 1186static inline int pmd_large(pmd_t pmd) 1187{ 1188 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1189} 1190 1191/* 1192 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1193 * the below will work for radix too 1194 */ 1195static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1196 unsigned long addr, pmd_t *pmdp) 1197{ 1198 unsigned long old; 1199 1200 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1201 return 0; 1202 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1203 return ((old & _PAGE_ACCESSED) != 0); 1204} 1205 1206#define __HAVE_ARCH_PMDP_SET_WRPROTECT 1207static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1208 pmd_t *pmdp) 1209{ 1210 if (__pmd_write((*pmdp))) 1211 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1212 else if (unlikely(pmd_savedwrite(*pmdp))) 1213 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1214} 1215 1216/* 1217 * Only returns true for a THP. False for pmd migration entry. 1218 * We also need to return true when we come across a pte that 1219 * in between a thp split. While splitting THP, we mark the pmd 1220 * invalid (pmdp_invalidate()) before we set it with pte page 1221 * address. A pmd_trans_huge() check against a pmd entry during that time 1222 * should return true. 1223 * We should not call this on a hugetlb entry. We should check for HugeTLB 1224 * entry using vma->vm_flags 1225 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1226 */ 1227static inline int pmd_trans_huge(pmd_t pmd) 1228{ 1229 if (!pmd_present(pmd)) 1230 return false; 1231 1232 if (radix_enabled()) 1233 return radix__pmd_trans_huge(pmd); 1234 return hash__pmd_trans_huge(pmd); 1235} 1236 1237#define __HAVE_ARCH_PMD_SAME 1238static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1239{ 1240 if (radix_enabled()) 1241 return radix__pmd_same(pmd_a, pmd_b); 1242 return hash__pmd_same(pmd_a, pmd_b); 1243} 1244 1245static inline pmd_t pmd_mkhuge(pmd_t pmd) 1246{ 1247 if (radix_enabled()) 1248 return radix__pmd_mkhuge(pmd); 1249 return hash__pmd_mkhuge(pmd); 1250} 1251 1252#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1253extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1254 unsigned long address, pmd_t *pmdp, 1255 pmd_t entry, int dirty); 1256 1257#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1258extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1259 unsigned long address, pmd_t *pmdp); 1260 1261#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1262static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1263 unsigned long addr, pmd_t *pmdp) 1264{ 1265 if (radix_enabled()) 1266 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1267 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1268} 1269 1270static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1271 unsigned long address, pmd_t *pmdp) 1272{ 1273 if (radix_enabled()) 1274 return radix__pmdp_collapse_flush(vma, address, pmdp); 1275 return hash__pmdp_collapse_flush(vma, address, pmdp); 1276} 1277#define pmdp_collapse_flush pmdp_collapse_flush 1278 1279#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1280pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1281 unsigned long addr, 1282 pmd_t *pmdp, int full); 1283 1284#define __HAVE_ARCH_PGTABLE_DEPOSIT 1285static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1286 pmd_t *pmdp, pgtable_t pgtable) 1287{ 1288 if (radix_enabled()) 1289 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1290 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1291} 1292 1293#define __HAVE_ARCH_PGTABLE_WITHDRAW 1294static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1295 pmd_t *pmdp) 1296{ 1297 if (radix_enabled()) 1298 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1299 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1300} 1301 1302#define __HAVE_ARCH_PMDP_INVALIDATE 1303extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1304 pmd_t *pmdp); 1305 1306#define pmd_move_must_withdraw pmd_move_must_withdraw 1307struct spinlock; 1308extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1309 struct spinlock *old_pmd_ptl, 1310 struct vm_area_struct *vma); 1311/* 1312 * Hash translation mode use the deposited table to store hash pte 1313 * slot information. 1314 */ 1315#define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1316static inline bool arch_needs_pgtable_deposit(void) 1317{ 1318 if (radix_enabled()) 1319 return false; 1320 return true; 1321} 1322extern void serialize_against_pte_lookup(struct mm_struct *mm); 1323 1324 1325static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1326{ 1327 if (radix_enabled()) 1328 return radix__pmd_mkdevmap(pmd); 1329 return hash__pmd_mkdevmap(pmd); 1330} 1331 1332static inline int pmd_devmap(pmd_t pmd) 1333{ 1334 return pte_devmap(pmd_pte(pmd)); 1335} 1336 1337static inline int pud_devmap(pud_t pud) 1338{ 1339 return 0; 1340} 1341 1342static inline int pgd_devmap(pgd_t pgd) 1343{ 1344 return 0; 1345} 1346#endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1347 1348static inline int pud_pfn(pud_t pud) 1349{ 1350 /* 1351 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1352 * check so this should never be used. If it grows another user we 1353 * want to know about it. 1354 */ 1355 BUILD_BUG(); 1356 return 0; 1357} 1358#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1359pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1360void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1361 pte_t *, pte_t, pte_t); 1362 1363/* 1364 * Returns true for a R -> RW upgrade of pte 1365 */ 1366static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1367{ 1368 if (!(old_val & _PAGE_READ)) 1369 return false; 1370 1371 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1372 return true; 1373 1374 return false; 1375} 1376 1377/* 1378 * Like pmd_huge() and pmd_large(), but works regardless of config options 1379 */ 1380#define pmd_is_leaf pmd_is_leaf 1381#define pmd_leaf pmd_is_leaf 1382static inline bool pmd_is_leaf(pmd_t pmd) 1383{ 1384 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1385} 1386 1387#define pud_is_leaf pud_is_leaf 1388#define pud_leaf pud_is_leaf 1389static inline bool pud_is_leaf(pud_t pud) 1390{ 1391 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1392} 1393 1394#define p4d_is_leaf p4d_is_leaf 1395#define p4d_leaf p4d_is_leaf 1396static inline bool p4d_is_leaf(p4d_t p4d) 1397{ 1398 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1399} 1400 1401#endif /* __ASSEMBLY__ */ 1402#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1403