1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_POWERPC_BOOK3S_32_PGTABLE_H 3#define _ASM_POWERPC_BOOK3S_32_PGTABLE_H 4 5#include <asm-generic/pgtable-nopmd.h> 6 7#include <asm/book3s/32/hash.h> 8 9/* And here we include common definitions */ 10 11#define _PAGE_KERNEL_RO 0 12#define _PAGE_KERNEL_ROX (_PAGE_EXEC) 13#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW) 14#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 15 16#define _PAGE_HPTEFLAGS _PAGE_HASHPTE 17 18#ifndef __ASSEMBLY__ 19 20static inline bool pte_user(pte_t pte) 21{ 22 return pte_val(pte) & _PAGE_USER; 23} 24#endif /* __ASSEMBLY__ */ 25 26/* 27 * Location of the PFN in the PTE. Most 32-bit platforms use the same 28 * as _PAGE_SHIFT here (ie, naturally aligned). 29 * Platform who don't just pre-define the value so we don't override it here. 30 */ 31#define PTE_RPN_SHIFT (PAGE_SHIFT) 32 33/* 34 * The mask covered by the RPN must be a ULL on 32-bit platforms with 35 * 64-bit PTEs. 36 */ 37#ifdef CONFIG_PTE_64BIT 38#define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1)) 39#define MAX_POSSIBLE_PHYSMEM_BITS 36 40#else 41#define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1)) 42#define MAX_POSSIBLE_PHYSMEM_BITS 32 43#endif 44 45/* 46 * _PAGE_CHG_MASK masks of bits that are to be preserved across 47 * pgprot changes. 48 */ 49#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HASHPTE | _PAGE_DIRTY | \ 50 _PAGE_ACCESSED | _PAGE_SPECIAL) 51 52/* 53 * We define 2 sets of base prot bits, one for basic pages (ie, 54 * cacheable kernel and user pages) and one for non cacheable 55 * pages. We always set _PAGE_COHERENT when SMP is enabled or 56 * the processor might need it for DMA coherency. 57 */ 58#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 59#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 60 61/* 62 * Permission masks used to generate the __P and __S table. 63 * 64 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 65 * 66 * Write permissions imply read permissions for now. 67 */ 68#define PAGE_NONE __pgprot(_PAGE_BASE) 69#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 70#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 71#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 72#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 73#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 74#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 75 76/* Permission masks used for kernel mappings */ 77#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 78#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE) 79#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 80 _PAGE_NO_CACHE | _PAGE_GUARDED) 81#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 82#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 83#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 84 85/* 86 * Protection used for kernel text. We want the debuggers to be able to 87 * set breakpoints anywhere, so don't write protect the kernel text 88 * on platforms where such control is possible. 89 */ 90#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\ 91 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 92#define PAGE_KERNEL_TEXT PAGE_KERNEL_X 93#else 94#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 95#endif 96 97/* Make modules code happy. We don't set RO yet */ 98#define PAGE_KERNEL_EXEC PAGE_KERNEL_X 99 100/* Advertise special mapping type for AGP */ 101#define PAGE_AGP (PAGE_KERNEL_NC) 102#define HAVE_PAGE_AGP 103 104#define PTE_INDEX_SIZE PTE_SHIFT 105#define PMD_INDEX_SIZE 0 106#define PUD_INDEX_SIZE 0 107#define PGD_INDEX_SIZE (32 - PGDIR_SHIFT) 108 109#define PMD_CACHE_INDEX PMD_INDEX_SIZE 110#define PUD_CACHE_INDEX PUD_INDEX_SIZE 111 112#ifndef __ASSEMBLY__ 113#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) 114#define PMD_TABLE_SIZE 0 115#define PUD_TABLE_SIZE 0 116#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 117 118/* Bits to mask out from a PMD to get to the PTE page */ 119#define PMD_MASKED_BITS (PTE_TABLE_SIZE - 1) 120#endif /* __ASSEMBLY__ */ 121 122#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 123#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 124 125/* 126 * The normal case is that PTEs are 32-bits and we have a 1-page 127 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 128 * 129 * For any >32-bit physical address platform, we can use the following 130 * two level page table layout where the pgdir is 8KB and the MS 13 bits 131 * are an index to the second level table. The combined pgdir/pmd first 132 * level has 2048 entries and the second level has 512 64-bit PTE entries. 133 * -Matt 134 */ 135/* PGDIR_SHIFT determines what a top-level page table entry can map */ 136#define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 137#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 138#define PGDIR_MASK (~(PGDIR_SIZE-1)) 139 140#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 141 142#ifndef __ASSEMBLY__ 143 144int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot); 145void unmap_kernel_page(unsigned long va); 146 147#endif /* !__ASSEMBLY__ */ 148 149/* 150 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary 151 * value (for now) on others, from where we can start layout kernel 152 * virtual space that goes below PKMAP and FIXMAP 153 */ 154#include <asm/fixmap.h> 155 156/* 157 * ioremap_bot starts at that address. Early ioremaps move down from there, 158 * until mem_init() at which point this becomes the top of the vmalloc 159 * and ioremap space 160 */ 161#ifdef CONFIG_HIGHMEM 162#define IOREMAP_TOP PKMAP_BASE 163#else 164#define IOREMAP_TOP FIXADDR_START 165#endif 166 167/* PPC32 shares vmalloc area with ioremap */ 168#define IOREMAP_START VMALLOC_START 169#define IOREMAP_END VMALLOC_END 170 171/* 172 * Just any arbitrary offset to the start of the vmalloc VM area: the 173 * current 16MB value just means that there will be a 64MB "hole" after the 174 * physical memory until the kernel virtual memory starts. That means that 175 * any out-of-bounds memory accesses will hopefully be caught. 176 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 177 * area for the same reason. ;) 178 * 179 * We no longer map larger than phys RAM with the BATs so we don't have 180 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry 181 * about clashes between our early calls to ioremap() that start growing down 182 * from ioremap_base being run into the VM area allocations (growing upwards 183 * from VMALLOC_START). For this reason we have ioremap_bot to check when 184 * we actually run into our mappings setup in the early boot with the VM 185 * system. This really does become a problem for machines with good amounts 186 * of RAM. -- Cort 187 */ 188#define VMALLOC_OFFSET (0x1000000) /* 16M */ 189 190#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 191 192#ifdef CONFIG_KASAN_VMALLOC 193#define VMALLOC_END ALIGN_DOWN(ioremap_bot, PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT) 194#else 195#define VMALLOC_END ioremap_bot 196#endif 197 198#ifdef CONFIG_STRICT_KERNEL_RWX 199#define MODULES_END ALIGN_DOWN(PAGE_OFFSET, SZ_256M) 200#define MODULES_VADDR (MODULES_END - SZ_256M) 201#endif 202 203#ifndef __ASSEMBLY__ 204#include <linux/sched.h> 205#include <linux/threads.h> 206 207/* Bits to mask out from a PGD to get to the PUD page */ 208#define PGD_MASKED_BITS 0 209 210#define pte_ERROR(e) \ 211 pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \ 212 (unsigned long long)pte_val(e)) 213#define pgd_ERROR(e) \ 214 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 215/* 216 * Bits in a linux-style PTE. These match the bits in the 217 * (hardware-defined) PowerPC PTE as closely as possible. 218 */ 219 220#define pte_clear(mm, addr, ptep) \ 221 do { pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0); } while (0) 222 223#define pmd_none(pmd) (!pmd_val(pmd)) 224#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) 225#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) 226static inline void pmd_clear(pmd_t *pmdp) 227{ 228 *pmdp = __pmd(0); 229} 230 231 232/* 233 * When flushing the tlb entry for a page, we also need to flush the hash 234 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. 235 */ 236extern int flush_hash_pages(unsigned context, unsigned long va, 237 unsigned long pmdval, int count); 238 239/* Add an HPTE to the hash table */ 240extern void add_hash_page(unsigned context, unsigned long va, 241 unsigned long pmdval); 242 243/* Flush an entry from the TLB/hash table */ 244extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep, 245 unsigned long address); 246 247/* 248 * PTE updates. This function is called whenever an existing 249 * valid PTE is updated. This does -not- include set_pte_at() 250 * which nowadays only sets a new PTE. 251 * 252 * Depending on the type of MMU, we may need to use atomic updates 253 * and the PTE may be either 32 or 64 bit wide. In the later case, 254 * when using atomic updates, only the low part of the PTE is 255 * accessed atomically. 256 */ 257static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p, 258 unsigned long clr, unsigned long set, int huge) 259{ 260 pte_basic_t old; 261 unsigned long tmp; 262 263 __asm__ __volatile__( 264#ifndef CONFIG_PTE_64BIT 265"1: lwarx %0, 0, %3\n" 266" andc %1, %0, %4\n" 267#else 268"1: lwarx %L0, 0, %3\n" 269" lwz %0, -4(%3)\n" 270" andc %1, %L0, %4\n" 271#endif 272" or %1, %1, %5\n" 273" stwcx. %1, 0, %3\n" 274" bne- 1b" 275 : "=&r" (old), "=&r" (tmp), "=m" (*p) 276#ifndef CONFIG_PTE_64BIT 277 : "r" (p), 278#else 279 : "b" ((unsigned long)(p) + 4), 280#endif 281 "r" (clr), "r" (set), "m" (*p) 282 : "cc" ); 283 284 return old; 285} 286 287/* 288 * 2.6 calls this without flushing the TLB entry; this is wrong 289 * for our hash-based implementation, we fix that up here. 290 */ 291#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 292static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 293 unsigned long addr, pte_t *ptep) 294{ 295 unsigned long old; 296 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 297 if (old & _PAGE_HASHPTE) { 298 unsigned long ptephys = __pa(ptep) & PAGE_MASK; 299 flush_hash_pages(mm->context.id, addr, ptephys, 1); 300 } 301 return (old & _PAGE_ACCESSED) != 0; 302} 303#define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 304 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep) 305 306#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 307static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 308 pte_t *ptep) 309{ 310 return __pte(pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0)); 311} 312 313#define __HAVE_ARCH_PTEP_SET_WRPROTECT 314static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 315 pte_t *ptep) 316{ 317 pte_update(mm, addr, ptep, _PAGE_RW, 0, 0); 318} 319 320static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 321 pte_t *ptep, pte_t entry, 322 unsigned long address, 323 int psize) 324{ 325 unsigned long set = pte_val(entry) & 326 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 327 328 pte_update(vma->vm_mm, address, ptep, 0, set, 0); 329 330 flush_tlb_page(vma, address); 331} 332 333#define __HAVE_ARCH_PTE_SAME 334#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) 335 336#define pmd_page(pmd) \ 337 pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 338 339/* 340 * Encode and decode a swap entry. 341 * Note that the bits we use in a PTE for representing a swap entry 342 * must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used). 343 * -- paulus 344 */ 345#define __swp_type(entry) ((entry).val & 0x1f) 346#define __swp_offset(entry) ((entry).val >> 5) 347#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) 348#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) 349#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) 350 351/* Generic accessors to PTE bits */ 352static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);} 353static inline int pte_read(pte_t pte) { return 1; } 354static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); } 355static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); } 356static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); } 357static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 358static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 359 360static inline int pte_present(pte_t pte) 361{ 362 return pte_val(pte) & _PAGE_PRESENT; 363} 364 365static inline bool pte_hw_valid(pte_t pte) 366{ 367 return pte_val(pte) & _PAGE_PRESENT; 368} 369 370static inline bool pte_hashpte(pte_t pte) 371{ 372 return !!(pte_val(pte) & _PAGE_HASHPTE); 373} 374 375static inline bool pte_ci(pte_t pte) 376{ 377 return !!(pte_val(pte) & _PAGE_NO_CACHE); 378} 379 380/* 381 * We only find page table entry in the last level 382 * Hence no need for other accessors 383 */ 384#define pte_access_permitted pte_access_permitted 385static inline bool pte_access_permitted(pte_t pte, bool write) 386{ 387 /* 388 * A read-only access is controlled by _PAGE_USER bit. 389 * We have _PAGE_READ set for WRITE and EXECUTE 390 */ 391 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 392 return false; 393 394 if (write && !pte_write(pte)) 395 return false; 396 397 return true; 398} 399 400/* Conversion functions: convert a page and protection to a page entry, 401 * and a page entry and page directory to the page they refer to. 402 * 403 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 404 * long for now. 405 */ 406static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 407{ 408 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) | 409 pgprot_val(pgprot)); 410} 411 412static inline unsigned long pte_pfn(pte_t pte) 413{ 414 return pte_val(pte) >> PTE_RPN_SHIFT; 415} 416 417/* Generic modifiers for PTE bits */ 418static inline pte_t pte_wrprotect(pte_t pte) 419{ 420 return __pte(pte_val(pte) & ~_PAGE_RW); 421} 422 423static inline pte_t pte_exprotect(pte_t pte) 424{ 425 return __pte(pte_val(pte) & ~_PAGE_EXEC); 426} 427 428static inline pte_t pte_mkclean(pte_t pte) 429{ 430 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 431} 432 433static inline pte_t pte_mkold(pte_t pte) 434{ 435 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 436} 437 438static inline pte_t pte_mkexec(pte_t pte) 439{ 440 return __pte(pte_val(pte) | _PAGE_EXEC); 441} 442 443static inline pte_t pte_mkpte(pte_t pte) 444{ 445 return pte; 446} 447 448static inline pte_t pte_mkwrite(pte_t pte) 449{ 450 return __pte(pte_val(pte) | _PAGE_RW); 451} 452 453static inline pte_t pte_mkdirty(pte_t pte) 454{ 455 return __pte(pte_val(pte) | _PAGE_DIRTY); 456} 457 458static inline pte_t pte_mkyoung(pte_t pte) 459{ 460 return __pte(pte_val(pte) | _PAGE_ACCESSED); 461} 462 463static inline pte_t pte_mkspecial(pte_t pte) 464{ 465 return __pte(pte_val(pte) | _PAGE_SPECIAL); 466} 467 468static inline pte_t pte_mkhuge(pte_t pte) 469{ 470 return pte; 471} 472 473static inline pte_t pte_mkprivileged(pte_t pte) 474{ 475 return __pte(pte_val(pte) & ~_PAGE_USER); 476} 477 478static inline pte_t pte_mkuser(pte_t pte) 479{ 480 return __pte(pte_val(pte) | _PAGE_USER); 481} 482 483static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 484{ 485 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 486} 487 488 489 490/* This low level function performs the actual PTE insertion 491 * Setting the PTE depends on the MMU type and other factors. It's 492 * an horrible mess that I'm not going to try to clean up now but 493 * I'm keeping it in one place rather than spread around 494 */ 495static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 496 pte_t *ptep, pte_t pte, int percpu) 497{ 498#if defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT) 499 /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the 500 * helper pte_update() which does an atomic update. We need to do that 501 * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a 502 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving 503 * the hash bits instead (ie, same as the non-SMP case) 504 */ 505 if (percpu) 506 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 507 | (pte_val(pte) & ~_PAGE_HASHPTE)); 508 else 509 pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, pte_val(pte), 0); 510 511#elif defined(CONFIG_PTE_64BIT) 512 /* Second case is 32-bit with 64-bit PTE. In this case, we 513 * can just store as long as we do the two halves in the right order 514 * with a barrier in between. This is possible because we take care, 515 * in the hash code, to pre-invalidate if the PTE was already hashed, 516 * which synchronizes us with any concurrent invalidation. 517 * In the percpu case, we also fallback to the simple update preserving 518 * the hash bits 519 */ 520 if (percpu) { 521 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 522 | (pte_val(pte) & ~_PAGE_HASHPTE)); 523 return; 524 } 525 if (pte_val(*ptep) & _PAGE_HASHPTE) 526 flush_hash_entry(mm, ptep, addr); 527 __asm__ __volatile__("\ 528 stw%X0 %2,%0\n\ 529 eieio\n\ 530 stw%X1 %L2,%1" 531 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4)) 532 : "r" (pte) : "memory"); 533 534#else 535 /* Third case is 32-bit hash table in UP mode, we need to preserve 536 * the _PAGE_HASHPTE bit since we may not have invalidated the previous 537 * translation in the hash yet (done in a subsequent flush_tlb_xxx()) 538 * and see we need to keep track that this PTE needs invalidating 539 */ 540 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 541 | (pte_val(pte) & ~_PAGE_HASHPTE)); 542#endif 543} 544 545/* 546 * Macro to mark a page protection value as "uncacheable". 547 */ 548 549#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \ 550 _PAGE_WRITETHRU) 551 552#define pgprot_noncached pgprot_noncached 553static inline pgprot_t pgprot_noncached(pgprot_t prot) 554{ 555 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 556 _PAGE_NO_CACHE | _PAGE_GUARDED); 557} 558 559#define pgprot_noncached_wc pgprot_noncached_wc 560static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 561{ 562 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 563 _PAGE_NO_CACHE); 564} 565 566#define pgprot_cached pgprot_cached 567static inline pgprot_t pgprot_cached(pgprot_t prot) 568{ 569 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 570 _PAGE_COHERENT); 571} 572 573#define pgprot_cached_wthru pgprot_cached_wthru 574static inline pgprot_t pgprot_cached_wthru(pgprot_t prot) 575{ 576 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 577 _PAGE_COHERENT | _PAGE_WRITETHRU); 578} 579 580#define pgprot_cached_noncoherent pgprot_cached_noncoherent 581static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot) 582{ 583 return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL); 584} 585 586#define pgprot_writecombine pgprot_writecombine 587static inline pgprot_t pgprot_writecombine(pgprot_t prot) 588{ 589 return pgprot_noncached_wc(prot); 590} 591 592#endif /* !__ASSEMBLY__ */ 593 594#endif /* _ASM_POWERPC_BOOK3S_32_PGTABLE_H */ 595