1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * OpenRISC Linux
4 *
5 * Linux architectural port borrowing liberally from similar works of
6 * others.  All original copyrights apply as per the original source
7 * declaration.
8 *
9 * OpenRISC implementation:
10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
12 * et al.
13 */
14
15/* or32 pgtable.h - macros and functions to manipulate page tables
16 *
17 * Based on:
18 * include/asm-cris/pgtable.h
19 */
20
21#ifndef __ASM_OPENRISC_PGTABLE_H
22#define __ASM_OPENRISC_PGTABLE_H
23
24#include <asm-generic/pgtable-nopmd.h>
25
26#ifndef __ASSEMBLY__
27#include <asm/mmu.h>
28#include <asm/fixmap.h>
29
30/*
31 * The Linux memory management assumes a three-level page table setup. On
32 * or32, we use that, but "fold" the mid level into the top-level page
33 * table. Since the MMU TLB is software loaded through an interrupt, it
34 * supports any page table structure, so we could have used a three-level
35 * setup, but for the amounts of memory we normally use, a two-level is
36 * probably more efficient.
37 *
38 * This file contains the functions and defines necessary to modify and use
39 * the or32 page table tree.
40 */
41
42extern void paging_init(void);
43
44/* Certain architectures need to do special things when pte's
45 * within a page table are directly modified.  Thus, the following
46 * hook is made available.
47 */
48#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
49#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
50/*
51 * (pmds are folded into pgds so this doesn't get actually called,
52 * but the define is needed for a generic inline function.)
53 */
54#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
55
56#define PGDIR_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-2))
57#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
58#define PGDIR_MASK	(~(PGDIR_SIZE-1))
59
60/*
61 * entries per page directory level: we use a two-level, so
62 * we don't really have any PMD directory physically.
63 * pointers are 4 bytes so we can use the page size and
64 * divide it by 4 (shift by 2).
65 */
66#define PTRS_PER_PTE	(1UL << (PAGE_SHIFT-2))
67
68#define PTRS_PER_PGD	(1UL << (32-PGDIR_SHIFT))
69
70/* calculate how many PGD entries a user-level program can use
71 * the first mappable virtual address is 0
72 * (TASK_SIZE is the maximum virtual address space)
73 */
74
75#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
76#define FIRST_USER_ADDRESS      0UL
77
78/*
79 * Kernels own virtual memory area.
80 */
81
82/*
83 * The size and location of the vmalloc area are chosen so that modules
84 * placed in this area aren't more than a 28-bit signed offset from any
85 * kernel functions that they may need.  This greatly simplifies handling
86 * of the relocations for l.j and l.jal instructions as we don't need to
87 * introduce any trampolines for reaching "distant" code.
88 *
89 * 64 MB of vmalloc area is comparable to what's available on other arches.
90 */
91
92#define VMALLOC_START	(PAGE_OFFSET-0x04000000UL)
93#define VMALLOC_END	(PAGE_OFFSET)
94#define VMALLOC_VMADDR(x) ((unsigned long)(x))
95
96/* Define some higher level generic page attributes.
97 *
98 * If you change _PAGE_CI definition be sure to change it in
99 * io.h for ioremap() too.
100 */
101
102/*
103 * An OR32 PTE looks like this:
104 *
105 * |  31 ... 10 |  9  |  8 ... 6  |  5  |  4  |  3  |  2  |  1  |  0  |
106 *  Phys pg.num    L     PP Index    D     A    WOM   WBC   CI    CC
107 *
108 *  L  : link
109 *  PPI: Page protection index
110 *  D  : Dirty
111 *  A  : Accessed
112 *  WOM: Weakly ordered memory
113 *  WBC: Write-back cache
114 *  CI : Cache inhibit
115 *  CC : Cache coherent
116 *
117 * The protection bits below should correspond to the layout of the actual
118 * PTE as per above
119 */
120
121#define _PAGE_CC       0x001 /* software: pte contains a translation */
122#define _PAGE_CI       0x002 /* cache inhibit          */
123#define _PAGE_WBC      0x004 /* write back cache       */
124#define _PAGE_WOM      0x008 /* weakly ordered memory  */
125
126#define _PAGE_A        0x010 /* accessed               */
127#define _PAGE_D        0x020 /* dirty                  */
128#define _PAGE_URE      0x040 /* user read enable       */
129#define _PAGE_UWE      0x080 /* user write enable      */
130
131#define _PAGE_SRE      0x100 /* superuser read enable  */
132#define _PAGE_SWE      0x200 /* superuser write enable */
133#define _PAGE_EXEC     0x400 /* software: page is executable */
134#define _PAGE_U_SHARED 0x800 /* software: page is shared in user space */
135
136/* 0x001 is cache coherency bit, which should always be set to
137 *       1 - for SMP (when we support it)
138 *       0 - otherwise
139 *
140 * we just reuse this bit in software for _PAGE_PRESENT and
141 * force it to 0 when loading it into TLB.
142 */
143#define _PAGE_PRESENT  _PAGE_CC
144#define _PAGE_USER     _PAGE_URE
145#define _PAGE_WRITE    (_PAGE_UWE | _PAGE_SWE)
146#define _PAGE_DIRTY    _PAGE_D
147#define _PAGE_ACCESSED _PAGE_A
148#define _PAGE_NO_CACHE _PAGE_CI
149#define _PAGE_SHARED   _PAGE_U_SHARED
150#define _PAGE_READ     (_PAGE_URE | _PAGE_SRE)
151
152#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
153#define _PAGE_BASE     (_PAGE_PRESENT | _PAGE_ACCESSED)
154#define _PAGE_ALL      (_PAGE_PRESENT | _PAGE_ACCESSED)
155#define _KERNPG_TABLE \
156	(_PAGE_BASE | _PAGE_SRE | _PAGE_SWE | _PAGE_ACCESSED | _PAGE_DIRTY)
157
158#define PAGE_NONE       __pgprot(_PAGE_ALL)
159#define PAGE_READONLY   __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
160#define PAGE_READONLY_X __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
161#define PAGE_SHARED \
162	__pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
163		 | _PAGE_SHARED)
164#define PAGE_SHARED_X \
165	__pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
166		 | _PAGE_SHARED | _PAGE_EXEC)
167#define PAGE_COPY       __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
168#define PAGE_COPY_X     __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
169
170#define PAGE_KERNEL \
171	__pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
172		 | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
173#define PAGE_KERNEL_RO \
174	__pgprot(_PAGE_ALL | _PAGE_SRE \
175		 | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
176#define PAGE_KERNEL_NOCACHE \
177	__pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
178		 | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC | _PAGE_CI)
179
180#define __P000	PAGE_NONE
181#define __P001	PAGE_READONLY_X
182#define __P010	PAGE_COPY
183#define __P011	PAGE_COPY_X
184#define __P100	PAGE_READONLY
185#define __P101	PAGE_READONLY_X
186#define __P110	PAGE_COPY
187#define __P111	PAGE_COPY_X
188
189#define __S000	PAGE_NONE
190#define __S001	PAGE_READONLY_X
191#define __S010	PAGE_SHARED
192#define __S011	PAGE_SHARED_X
193#define __S100	PAGE_READONLY
194#define __S101	PAGE_READONLY_X
195#define __S110	PAGE_SHARED
196#define __S111	PAGE_SHARED_X
197
198/* zero page used for uninitialized stuff */
199extern unsigned long empty_zero_page[2048];
200#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
201
202/* number of bits that fit into a memory pointer */
203#define BITS_PER_PTR			(8*sizeof(unsigned long))
204
205/* to align the pointer to a pointer address */
206#define PTR_MASK			(~(sizeof(void *)-1))
207
208/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
209/* 64-bit machines, beware!  SRB. */
210#define SIZEOF_PTR_LOG2			2
211
212/* to find an entry in a page-table */
213#define PAGE_PTR(address) \
214((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
215
216/* to set the page-dir */
217#define SET_PAGE_DIR(tsk, pgdir)
218
219#define pte_none(x)	(!pte_val(x))
220#define pte_present(x)	(pte_val(x) & _PAGE_PRESENT)
221#define pte_clear(mm, addr, xp)	do { pte_val(*(xp)) = 0; } while (0)
222
223#define pmd_none(x)	(!pmd_val(x))
224#define	pmd_bad(x)	((pmd_val(x) & (~PAGE_MASK)) != _KERNPG_TABLE)
225#define pmd_present(x)	(pmd_val(x) & _PAGE_PRESENT)
226#define pmd_clear(xp)	do { pmd_val(*(xp)) = 0; } while (0)
227
228/*
229 * The following only work if pte_present() is true.
230 * Undefined behaviour if not..
231 */
232
233static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_READ; }
234static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
235static inline int pte_exec(pte_t pte)  { return pte_val(pte) & _PAGE_EXEC; }
236static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
237static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
238
239static inline pte_t pte_wrprotect(pte_t pte)
240{
241	pte_val(pte) &= ~(_PAGE_WRITE);
242	return pte;
243}
244
245static inline pte_t pte_rdprotect(pte_t pte)
246{
247	pte_val(pte) &= ~(_PAGE_READ);
248	return pte;
249}
250
251static inline pte_t pte_exprotect(pte_t pte)
252{
253	pte_val(pte) &= ~(_PAGE_EXEC);
254	return pte;
255}
256
257static inline pte_t pte_mkclean(pte_t pte)
258{
259	pte_val(pte) &= ~(_PAGE_DIRTY);
260	return pte;
261}
262
263static inline pte_t pte_mkold(pte_t pte)
264{
265	pte_val(pte) &= ~(_PAGE_ACCESSED);
266	return pte;
267}
268
269static inline pte_t pte_mkwrite(pte_t pte)
270{
271	pte_val(pte) |= _PAGE_WRITE;
272	return pte;
273}
274
275static inline pte_t pte_mkread(pte_t pte)
276{
277	pte_val(pte) |= _PAGE_READ;
278	return pte;
279}
280
281static inline pte_t pte_mkexec(pte_t pte)
282{
283	pte_val(pte) |= _PAGE_EXEC;
284	return pte;
285}
286
287static inline pte_t pte_mkdirty(pte_t pte)
288{
289	pte_val(pte) |= _PAGE_DIRTY;
290	return pte;
291}
292
293static inline pte_t pte_mkyoung(pte_t pte)
294{
295	pte_val(pte) |= _PAGE_ACCESSED;
296	return pte;
297}
298
299/*
300 * Conversion functions: convert a page and protection to a page entry,
301 * and a page entry and page directory to the page they refer to.
302 */
303
304/* What actually goes as arguments to the various functions is less than
305 * obvious, but a rule of thumb is that struct page's goes as struct page *,
306 * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
307 * addresses (the 0xc0xxxxxx's) goes as void *'s.
308 */
309
310static inline pte_t __mk_pte(void *page, pgprot_t pgprot)
311{
312	pte_t pte;
313	/* the PTE needs a physical address */
314	pte_val(pte) = __pa(page) | pgprot_val(pgprot);
315	return pte;
316}
317
318#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
319
320#define mk_pte_phys(physpage, pgprot) \
321({                                                                      \
322	pte_t __pte;                                                    \
323									\
324	pte_val(__pte) = (physpage) + pgprot_val(pgprot);               \
325	__pte;                                                          \
326})
327
328static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
329{
330	pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
331	return pte;
332}
333
334
335/*
336 * pte_val refers to a page in the 0x0xxxxxxx physical DRAM interval
337 * __pte_page(pte_val) refers to the "virtual" DRAM interval
338 * pte_pagenr refers to the page-number counted starting from the virtual
339 * DRAM start
340 */
341
342static inline unsigned long __pte_page(pte_t pte)
343{
344	/* the PTE contains a physical address */
345	return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
346}
347
348#define pte_pagenr(pte)         ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
349
350/* permanent address of a page */
351
352#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
353#define pte_page(pte)		(mem_map+pte_pagenr(pte))
354
355/*
356 * only the pte's themselves need to point to physical DRAM (see above)
357 * the pagetable links are purely handled within the kernel SW and thus
358 * don't need the __pa and __va transformations.
359 */
360static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
361{
362	pmd_val(*pmdp) = _KERNPG_TABLE | (unsigned long) ptep;
363}
364
365#define pmd_page(pmd)		(pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
366
367static inline unsigned long pmd_page_vaddr(pmd_t pmd)
368{
369	return ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK));
370}
371
372#define __pmd_offset(address) \
373	(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
374
375#define pte_pfn(x)		((unsigned long)(((x).pte)) >> PAGE_SHIFT)
376#define pfn_pte(pfn, prot)  __pte((((pfn) << PAGE_SHIFT)) | pgprot_val(prot))
377
378#define pte_ERROR(e) \
379	printk(KERN_ERR "%s:%d: bad pte %p(%08lx).\n", \
380	       __FILE__, __LINE__, &(e), pte_val(e))
381#define pgd_ERROR(e) \
382	printk(KERN_ERR "%s:%d: bad pgd %p(%08lx).\n", \
383	       __FILE__, __LINE__, &(e), pgd_val(e))
384
385extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
386
387struct vm_area_struct;
388
389static inline void update_tlb(struct vm_area_struct *vma,
390	unsigned long address, pte_t *pte)
391{
392}
393
394extern void update_cache(struct vm_area_struct *vma,
395	unsigned long address, pte_t *pte);
396
397static inline void update_mmu_cache(struct vm_area_struct *vma,
398	unsigned long address, pte_t *pte)
399{
400	update_tlb(vma, address, pte);
401	update_cache(vma, address, pte);
402}
403
404/* __PHX__ FIXME, SWAP, this probably doesn't work */
405
406/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
407/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
408
409#define __swp_type(x)			(((x).val >> 5) & 0x7f)
410#define __swp_offset(x)			((x).val >> 12)
411#define __swp_entry(type, offset) \
412	((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
413#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
414#define __swp_entry_to_pte(x)		((pte_t) { (x).val })
415
416#define kern_addr_valid(addr)           (1)
417
418typedef pte_t *pte_addr_t;
419
420#endif /* __ASSEMBLY__ */
421#endif /* __ASM_OPENRISC_PGTABLE_H */
422