1/*
2 * Code to handle IP32 IRQs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2001 Keith M Wesolowski
10 */
11#include <linux/init.h>
12#include <linux/kernel_stat.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/bitops.h>
17#include <linux/kernel.h>
18#include <linux/mm.h>
19#include <linux/random.h>
20#include <linux/sched.h>
21#include <linux/sched/debug.h>
22
23#include <asm/irq_cpu.h>
24#include <asm/mipsregs.h>
25#include <asm/signal.h>
26#include <asm/time.h>
27#include <asm/ip32/crime.h>
28#include <asm/ip32/mace.h>
29#include <asm/ip32/ip32_ints.h>
30
31/* issue a PIO read to make sure no PIO writes are pending */
32static inline void flush_crime_bus(void)
33{
34	crime->control;
35}
36
37static inline void flush_mace_bus(void)
38{
39	mace->perif.ctrl.misc;
40}
41
42/*
43 * O2 irq map
44 *
45 * IP0 -> software (ignored)
46 * IP1 -> software (ignored)
47 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
48 * IP3 -> (irq1) X unknown
49 * IP4 -> (irq2) X unknown
50 * IP5 -> (irq3) X unknown
51 * IP6 -> (irq4) X unknown
52 * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
53 *
54 * crime: (C)
55 *
56 * CRIME_INT_STAT 31:0:
57 *
58 * 0  ->  8  Video in 1
59 * 1  ->  9 Video in 2
60 * 2  -> 10  Video out
61 * 3  -> 11  Mace ethernet
62 * 4  -> S  SuperIO sub-interrupt
63 * 5  -> M  Miscellaneous sub-interrupt
64 * 6  -> A  Audio sub-interrupt
65 * 7  -> 15  PCI bridge errors
66 * 8  -> 16  PCI SCSI aic7xxx 0
67 * 9  -> 17 PCI SCSI aic7xxx 1
68 * 10 -> 18 PCI slot 0
69 * 11 -> 19 unused (PCI slot 1)
70 * 12 -> 20 unused (PCI slot 2)
71 * 13 -> 21 unused (PCI shared 0)
72 * 14 -> 22 unused (PCI shared 1)
73 * 15 -> 23 unused (PCI shared 2)
74 * 16 -> 24 GBE0 (E)
75 * 17 -> 25 GBE1 (E)
76 * 18 -> 26 GBE2 (E)
77 * 19 -> 27 GBE3 (E)
78 * 20 -> 28 CPU errors
79 * 21 -> 29 Memory errors
80 * 22 -> 30 RE empty edge (E)
81 * 23 -> 31 RE full edge (E)
82 * 24 -> 32 RE idle edge (E)
83 * 25 -> 33 RE empty level
84 * 26 -> 34 RE full level
85 * 27 -> 35 RE idle level
86 * 28 -> 36 unused (software 0) (E)
87 * 29 -> 37 unused (software 1) (E)
88 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
89 * 31 -> 39 VICE
90 *
91 * S, M, A: Use the MACE ISA interrupt register
92 * MACE_ISA_INT_STAT 31:0
93 *
94 * 0-7 -> 40-47 Audio
95 * 8 -> 48 RTC
96 * 9 -> 49 Keyboard
97 * 10 -> X Keyboard polled
98 * 11 -> 51 Mouse
99 * 12 -> X Mouse polled
100 * 13-15 -> 53-55 Count/compare timers
101 * 16-19 -> 56-59 Parallel (16 E)
102 * 20-25 -> 60-62 Serial 1 (22 E)
103 * 26-31 -> 66-71 Serial 2 (28 E)
104 *
105 * Note that this means IRQs 12-14, 50, and 52 do not exist.  This is a
106 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
107 * is quite different anyway.
108 */
109
110/* Some initial interrupts to set up */
111extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
112extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
113
114/*
115 * This is for pure CRIME interrupts - ie not MACE.  The advantage?
116 * We get to split the register in half and do faster lookups.
117 */
118
119static uint64_t crime_mask;
120
121static inline void crime_enable_irq(struct irq_data *d)
122{
123	unsigned int bit = d->irq - CRIME_IRQ_BASE;
124
125	crime_mask |= 1 << bit;
126	crime->imask = crime_mask;
127}
128
129static inline void crime_disable_irq(struct irq_data *d)
130{
131	unsigned int bit = d->irq - CRIME_IRQ_BASE;
132
133	crime_mask &= ~(1 << bit);
134	crime->imask = crime_mask;
135	flush_crime_bus();
136}
137
138static struct irq_chip crime_level_interrupt = {
139	.name		= "IP32 CRIME",
140	.irq_mask	= crime_disable_irq,
141	.irq_unmask	= crime_enable_irq,
142};
143
144static void crime_edge_mask_and_ack_irq(struct irq_data *d)
145{
146	unsigned int bit = d->irq - CRIME_IRQ_BASE;
147	uint64_t crime_int;
148
149	/* Edge triggered interrupts must be cleared. */
150	crime_int = crime->hard_int;
151	crime_int &= ~(1 << bit);
152	crime->hard_int = crime_int;
153
154	crime_disable_irq(d);
155}
156
157static struct irq_chip crime_edge_interrupt = {
158	.name		= "IP32 CRIME",
159	.irq_ack	= crime_edge_mask_and_ack_irq,
160	.irq_mask	= crime_disable_irq,
161	.irq_mask_ack	= crime_edge_mask_and_ack_irq,
162	.irq_unmask	= crime_enable_irq,
163};
164
165/*
166 * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
167 * as close to the source as possible.	This also means we can take the
168 * next chunk of the CRIME register in one piece.
169 */
170
171static unsigned long macepci_mask;
172
173static void enable_macepci_irq(struct irq_data *d)
174{
175	macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
176	mace->pci.control = macepci_mask;
177	crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE);
178	crime->imask = crime_mask;
179}
180
181static void disable_macepci_irq(struct irq_data *d)
182{
183	crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE));
184	crime->imask = crime_mask;
185	flush_crime_bus();
186	macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
187	mace->pci.control = macepci_mask;
188	flush_mace_bus();
189}
190
191static struct irq_chip ip32_macepci_interrupt = {
192	.name = "IP32 MACE PCI",
193	.irq_mask = disable_macepci_irq,
194	.irq_unmask = enable_macepci_irq,
195};
196
197/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
198 * CRIME register.
199 */
200
201#define MACEISA_AUDIO_INT	(MACEISA_AUDIO_SW_INT |		\
202				 MACEISA_AUDIO_SC_INT |		\
203				 MACEISA_AUDIO1_DMAT_INT |	\
204				 MACEISA_AUDIO1_OF_INT |	\
205				 MACEISA_AUDIO2_DMAT_INT |	\
206				 MACEISA_AUDIO2_MERR_INT |	\
207				 MACEISA_AUDIO3_DMAT_INT |	\
208				 MACEISA_AUDIO3_MERR_INT)
209#define MACEISA_MISC_INT	(MACEISA_RTC_INT |		\
210				 MACEISA_KEYB_INT |		\
211				 MACEISA_KEYB_POLL_INT |	\
212				 MACEISA_MOUSE_INT |		\
213				 MACEISA_MOUSE_POLL_INT |	\
214				 MACEISA_TIMER0_INT |		\
215				 MACEISA_TIMER1_INT |		\
216				 MACEISA_TIMER2_INT)
217#define MACEISA_SUPERIO_INT	(MACEISA_PARALLEL_INT |		\
218				 MACEISA_PAR_CTXA_INT |		\
219				 MACEISA_PAR_CTXB_INT |		\
220				 MACEISA_PAR_MERR_INT |		\
221				 MACEISA_SERIAL1_INT |		\
222				 MACEISA_SERIAL1_TDMAT_INT |	\
223				 MACEISA_SERIAL1_TDMAPR_INT |	\
224				 MACEISA_SERIAL1_TDMAME_INT |	\
225				 MACEISA_SERIAL1_RDMAT_INT |	\
226				 MACEISA_SERIAL1_RDMAOR_INT |	\
227				 MACEISA_SERIAL2_INT |		\
228				 MACEISA_SERIAL2_TDMAT_INT |	\
229				 MACEISA_SERIAL2_TDMAPR_INT |	\
230				 MACEISA_SERIAL2_TDMAME_INT |	\
231				 MACEISA_SERIAL2_RDMAT_INT |	\
232				 MACEISA_SERIAL2_RDMAOR_INT)
233
234static unsigned long maceisa_mask;
235
236static void enable_maceisa_irq(struct irq_data *d)
237{
238	unsigned int crime_int = 0;
239
240	pr_debug("maceisa enable: %u\n", d->irq);
241
242	switch (d->irq) {
243	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
244		crime_int = MACE_AUDIO_INT;
245		break;
246	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
247		crime_int = MACE_MISC_INT;
248		break;
249	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
250		crime_int = MACE_SUPERIO_INT;
251		break;
252	}
253	pr_debug("crime_int %08x enabled\n", crime_int);
254	crime_mask |= crime_int;
255	crime->imask = crime_mask;
256	maceisa_mask |= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ);
257	mace->perif.ctrl.imask = maceisa_mask;
258}
259
260static void disable_maceisa_irq(struct irq_data *d)
261{
262	unsigned int crime_int = 0;
263
264	maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
265	if (!(maceisa_mask & MACEISA_AUDIO_INT))
266		crime_int |= MACE_AUDIO_INT;
267	if (!(maceisa_mask & MACEISA_MISC_INT))
268		crime_int |= MACE_MISC_INT;
269	if (!(maceisa_mask & MACEISA_SUPERIO_INT))
270		crime_int |= MACE_SUPERIO_INT;
271	crime_mask &= ~crime_int;
272	crime->imask = crime_mask;
273	flush_crime_bus();
274	mace->perif.ctrl.imask = maceisa_mask;
275	flush_mace_bus();
276}
277
278static void mask_and_ack_maceisa_irq(struct irq_data *d)
279{
280	unsigned long mace_int;
281
282	/* edge triggered */
283	mace_int = mace->perif.ctrl.istat;
284	mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
285	mace->perif.ctrl.istat = mace_int;
286
287	disable_maceisa_irq(d);
288}
289
290static struct irq_chip ip32_maceisa_level_interrupt = {
291	.name		= "IP32 MACE ISA",
292	.irq_mask	= disable_maceisa_irq,
293	.irq_unmask	= enable_maceisa_irq,
294};
295
296static struct irq_chip ip32_maceisa_edge_interrupt = {
297	.name		= "IP32 MACE ISA",
298	.irq_ack	= mask_and_ack_maceisa_irq,
299	.irq_mask	= disable_maceisa_irq,
300	.irq_mask_ack	= mask_and_ack_maceisa_irq,
301	.irq_unmask	= enable_maceisa_irq,
302};
303
304/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
305 * bits 0-3 and 7 in the CRIME register.
306 */
307
308static void enable_mace_irq(struct irq_data *d)
309{
310	unsigned int bit = d->irq - CRIME_IRQ_BASE;
311
312	crime_mask |= (1 << bit);
313	crime->imask = crime_mask;
314}
315
316static void disable_mace_irq(struct irq_data *d)
317{
318	unsigned int bit = d->irq - CRIME_IRQ_BASE;
319
320	crime_mask &= ~(1 << bit);
321	crime->imask = crime_mask;
322	flush_crime_bus();
323}
324
325static struct irq_chip ip32_mace_interrupt = {
326	.name = "IP32 MACE",
327	.irq_mask = disable_mace_irq,
328	.irq_unmask = enable_mace_irq,
329};
330
331static void ip32_unknown_interrupt(void)
332{
333	printk("Unknown interrupt occurred!\n");
334	printk("cp0_status: %08x\n", read_c0_status());
335	printk("cp0_cause: %08x\n", read_c0_cause());
336	printk("CRIME intr mask: %016lx\n", crime->imask);
337	printk("CRIME intr status: %016lx\n", crime->istat);
338	printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
339	printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
340	printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
341	printk("MACE PCI control register: %08x\n", mace->pci.control);
342
343	printk("Register dump:\n");
344	show_regs(get_irq_regs());
345
346	printk("Please mail this report to linux-mips@linux-mips.org\n");
347	printk("Spinning...");
348	while(1) ;
349}
350
351/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
352/* change this to loop over all edge-triggered irqs, exception masked out ones */
353static void ip32_irq0(void)
354{
355	uint64_t crime_int;
356	int irq = 0;
357
358	/*
359	 * Sanity check interrupt numbering enum.
360	 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
361	 * chained.
362	 */
363	BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
364	BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
365
366	crime_int = crime->istat & crime_mask;
367
368	/* crime sometime delivers spurious interrupts, ignore them */
369	if (unlikely(crime_int == 0))
370		return;
371
372	irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
373
374	if (crime_int & CRIME_MACEISA_INT_MASK) {
375		unsigned long mace_int = mace->perif.ctrl.istat;
376		irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
377	}
378
379	pr_debug("*irq %u*\n", irq);
380	do_IRQ(irq);
381}
382
383static void ip32_irq1(void)
384{
385	ip32_unknown_interrupt();
386}
387
388static void ip32_irq2(void)
389{
390	ip32_unknown_interrupt();
391}
392
393static void ip32_irq3(void)
394{
395	ip32_unknown_interrupt();
396}
397
398static void ip32_irq4(void)
399{
400	ip32_unknown_interrupt();
401}
402
403static void ip32_irq5(void)
404{
405	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
406}
407
408asmlinkage void plat_irq_dispatch(void)
409{
410	unsigned int pending = read_c0_status() & read_c0_cause();
411
412	if (likely(pending & IE_IRQ0))
413		ip32_irq0();
414	else if (unlikely(pending & IE_IRQ1))
415		ip32_irq1();
416	else if (unlikely(pending & IE_IRQ2))
417		ip32_irq2();
418	else if (unlikely(pending & IE_IRQ3))
419		ip32_irq3();
420	else if (unlikely(pending & IE_IRQ4))
421		ip32_irq4();
422	else if (likely(pending & IE_IRQ5))
423		ip32_irq5();
424}
425
426void __init arch_init_irq(void)
427{
428	unsigned int irq;
429
430	/* Install our interrupt handler, then clear and disable all
431	 * CRIME and MACE interrupts. */
432	crime->imask = 0;
433	crime->hard_int = 0;
434	crime->soft_int = 0;
435	mace->perif.ctrl.istat = 0;
436	mace->perif.ctrl.imask = 0;
437
438	mips_cpu_irq_init();
439	for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
440		switch (irq) {
441		case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
442			irq_set_chip_and_handler_name(irq,
443						      &ip32_mace_interrupt,
444						      handle_level_irq,
445						      "level");
446			break;
447
448		case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
449			irq_set_chip_and_handler_name(irq,
450						      &ip32_macepci_interrupt,
451						      handle_level_irq,
452						      "level");
453			break;
454
455		case CRIME_CPUERR_IRQ:
456		case CRIME_MEMERR_IRQ:
457			irq_set_chip_and_handler_name(irq,
458						      &crime_level_interrupt,
459						      handle_level_irq,
460						      "level");
461			break;
462
463		case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
464		case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
465		case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
466		case CRIME_VICE_IRQ:
467			irq_set_chip_and_handler_name(irq,
468						      &crime_edge_interrupt,
469						      handle_edge_irq,
470						      "edge");
471			break;
472
473		case MACEISA_PARALLEL_IRQ:
474		case MACEISA_SERIAL1_TDMAPR_IRQ:
475		case MACEISA_SERIAL2_TDMAPR_IRQ:
476			irq_set_chip_and_handler_name(irq,
477						      &ip32_maceisa_edge_interrupt,
478						      handle_edge_irq,
479						      "edge");
480			break;
481
482		default:
483			irq_set_chip_and_handler_name(irq,
484						      &ip32_maceisa_level_interrupt,
485						      handle_level_irq,
486						      "level");
487			break;
488		}
489	}
490	if (request_irq(CRIME_MEMERR_IRQ, crime_memerr_intr, 0,
491			"CRIME memory error", NULL))
492		pr_err("Failed to register CRIME memory error interrupt\n");
493	if (request_irq(CRIME_CPUERR_IRQ, crime_cpuerr_intr, 0,
494			"CRIME CPU error", NULL))
495		pr_err("Failed to register CRIME CPU error interrupt\n");
496
497#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
498	change_c0_status(ST0_IM, ALLINTS);
499}
500