18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * setup.c - boot time setup code 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#include <linux/init.h> 78c2ecf20Sopenharmony_ci#include <linux/export.h> 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#include <asm/bootinfo.h> 108c2ecf20Sopenharmony_ci#include <asm/reboot.h> 118c2ecf20Sopenharmony_ci#include <asm/time.h> 128c2ecf20Sopenharmony_ci#include <linux/ioport.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#include <asm/mach-rc32434/rb.h> 158c2ecf20Sopenharmony_ci#include <asm/mach-rc32434/pci.h> 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_cistruct pci_reg __iomem *pci_reg; 188c2ecf20Sopenharmony_ciEXPORT_SYMBOL(pci_reg); 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_cistatic struct resource pci0_res[] = { 218c2ecf20Sopenharmony_ci { 228c2ecf20Sopenharmony_ci .name = "pci_reg0", 238c2ecf20Sopenharmony_ci .start = PCI0_BASE_ADDR, 248c2ecf20Sopenharmony_ci .end = PCI0_BASE_ADDR + sizeof(struct pci_reg), 258c2ecf20Sopenharmony_ci .flags = IORESOURCE_MEM, 268c2ecf20Sopenharmony_ci } 278c2ecf20Sopenharmony_ci}; 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_cistatic void rb_machine_restart(char *command) 308c2ecf20Sopenharmony_ci{ 318c2ecf20Sopenharmony_ci /* just jump to the reset vector */ 328c2ecf20Sopenharmony_ci writel(0x80000001, IDT434_REG_BASE + RST); 338c2ecf20Sopenharmony_ci ((void (*)(void)) KSEG1ADDR(0x1FC00000u))(); 348c2ecf20Sopenharmony_ci} 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_cistatic void rb_machine_halt(void) 378c2ecf20Sopenharmony_ci{ 388c2ecf20Sopenharmony_ci for (;;) 398c2ecf20Sopenharmony_ci continue; 408c2ecf20Sopenharmony_ci} 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_civoid __init plat_mem_setup(void) 438c2ecf20Sopenharmony_ci{ 448c2ecf20Sopenharmony_ci u32 val; 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci _machine_restart = rb_machine_restart; 478c2ecf20Sopenharmony_ci _machine_halt = rb_machine_halt; 488c2ecf20Sopenharmony_ci pm_power_off = rb_machine_halt; 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci set_io_port_base(KSEG1); 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci pci_reg = ioremap(pci0_res[0].start, 538c2ecf20Sopenharmony_ci pci0_res[0].end - pci0_res[0].start); 548c2ecf20Sopenharmony_ci if (!pci_reg) { 558c2ecf20Sopenharmony_ci printk(KERN_ERR "Could not remap PCI registers\n"); 568c2ecf20Sopenharmony_ci return; 578c2ecf20Sopenharmony_ci } 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ci val = __raw_readl(&pci_reg->pcic); 608c2ecf20Sopenharmony_ci val &= 0xFFFFFF7; 618c2ecf20Sopenharmony_ci __raw_writel(val, (void *)&pci_reg->pcic); 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci#ifdef CONFIG_PCI 648c2ecf20Sopenharmony_ci /* Enable PCI interrupts in EPLD Mask register */ 658c2ecf20Sopenharmony_ci *epld_mask = 0x0; 668c2ecf20Sopenharmony_ci *(epld_mask + 1) = 0x0; 678c2ecf20Sopenharmony_ci#endif 688c2ecf20Sopenharmony_ci write_c0_wired(0); 698c2ecf20Sopenharmony_ci} 708c2ecf20Sopenharmony_ci 718c2ecf20Sopenharmony_ciconst char *get_system_type(void) 728c2ecf20Sopenharmony_ci{ 738c2ecf20Sopenharmony_ci switch (mips_machtype) { 748c2ecf20Sopenharmony_ci case MACH_MIKROTIK_RB532A: 758c2ecf20Sopenharmony_ci return "Mikrotik RB532A"; 768c2ecf20Sopenharmony_ci break; 778c2ecf20Sopenharmony_ci default: 788c2ecf20Sopenharmony_ci return "Mikrotik RB532"; 798c2ecf20Sopenharmony_ci break; 808c2ecf20Sopenharmony_ci } 818c2ecf20Sopenharmony_ci} 82