18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups. 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@linux-mips.org> 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci#include <linux/init.h> 88c2ecf20Sopenharmony_ci#include <linux/pci.h> 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#include <asm/vr41xx/giu.h> 118c2ecf20Sopenharmony_ci#include <asm/vr41xx/tb0226.h> 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciint pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 148c2ecf20Sopenharmony_ci{ 158c2ecf20Sopenharmony_ci int irq = -1; 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci switch (slot) { 188c2ecf20Sopenharmony_ci case 12: 198c2ecf20Sopenharmony_ci vr41xx_set_irq_trigger(GD82559_1_PIN, 208c2ecf20Sopenharmony_ci IRQ_TRIGGER_LEVEL, 218c2ecf20Sopenharmony_ci IRQ_SIGNAL_THROUGH); 228c2ecf20Sopenharmony_ci vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW); 238c2ecf20Sopenharmony_ci irq = GD82559_1_IRQ; 248c2ecf20Sopenharmony_ci break; 258c2ecf20Sopenharmony_ci case 13: 268c2ecf20Sopenharmony_ci vr41xx_set_irq_trigger(GD82559_2_PIN, 278c2ecf20Sopenharmony_ci IRQ_TRIGGER_LEVEL, 288c2ecf20Sopenharmony_ci IRQ_SIGNAL_THROUGH); 298c2ecf20Sopenharmony_ci vr41xx_set_irq_level(GD82559_2_PIN, IRQ_LEVEL_LOW); 308c2ecf20Sopenharmony_ci irq = GD82559_2_IRQ; 318c2ecf20Sopenharmony_ci break; 328c2ecf20Sopenharmony_ci case 14: 338c2ecf20Sopenharmony_ci switch (pin) { 348c2ecf20Sopenharmony_ci case 1: 358c2ecf20Sopenharmony_ci vr41xx_set_irq_trigger(UPD720100_INTA_PIN, 368c2ecf20Sopenharmony_ci IRQ_TRIGGER_LEVEL, 378c2ecf20Sopenharmony_ci IRQ_SIGNAL_THROUGH); 388c2ecf20Sopenharmony_ci vr41xx_set_irq_level(UPD720100_INTA_PIN, 398c2ecf20Sopenharmony_ci IRQ_LEVEL_LOW); 408c2ecf20Sopenharmony_ci irq = UPD720100_INTA_IRQ; 418c2ecf20Sopenharmony_ci break; 428c2ecf20Sopenharmony_ci case 2: 438c2ecf20Sopenharmony_ci vr41xx_set_irq_trigger(UPD720100_INTB_PIN, 448c2ecf20Sopenharmony_ci IRQ_TRIGGER_LEVEL, 458c2ecf20Sopenharmony_ci IRQ_SIGNAL_THROUGH); 468c2ecf20Sopenharmony_ci vr41xx_set_irq_level(UPD720100_INTB_PIN, 478c2ecf20Sopenharmony_ci IRQ_LEVEL_LOW); 488c2ecf20Sopenharmony_ci irq = UPD720100_INTB_IRQ; 498c2ecf20Sopenharmony_ci break; 508c2ecf20Sopenharmony_ci case 3: 518c2ecf20Sopenharmony_ci vr41xx_set_irq_trigger(UPD720100_INTC_PIN, 528c2ecf20Sopenharmony_ci IRQ_TRIGGER_LEVEL, 538c2ecf20Sopenharmony_ci IRQ_SIGNAL_THROUGH); 548c2ecf20Sopenharmony_ci vr41xx_set_irq_level(UPD720100_INTC_PIN, 558c2ecf20Sopenharmony_ci IRQ_LEVEL_LOW); 568c2ecf20Sopenharmony_ci irq = UPD720100_INTC_IRQ; 578c2ecf20Sopenharmony_ci break; 588c2ecf20Sopenharmony_ci default: 598c2ecf20Sopenharmony_ci break; 608c2ecf20Sopenharmony_ci } 618c2ecf20Sopenharmony_ci break; 628c2ecf20Sopenharmony_ci default: 638c2ecf20Sopenharmony_ci break; 648c2ecf20Sopenharmony_ci } 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ci return irq; 678c2ecf20Sopenharmony_ci} 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_ci/* Do platform specific device initialization at pci_enable_device() time */ 708c2ecf20Sopenharmony_ciint pcibios_plat_dev_init(struct pci_dev *dev) 718c2ecf20Sopenharmony_ci{ 728c2ecf20Sopenharmony_ci return 0; 738c2ecf20Sopenharmony_ci} 74