18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
28c2ecf20Sopenharmony_ci#include <linux/init.h>
38c2ecf20Sopenharmony_ci#include <linux/kernel.h>
48c2ecf20Sopenharmony_ci#include <linux/pci.h>
58c2ecf20Sopenharmony_ci#include <asm/ip32/ip32_ints.h>
68c2ecf20Sopenharmony_ci/*
78c2ecf20Sopenharmony_ci * O2 has up to 5 PCI devices connected into the MACE bridge.  The device
88c2ecf20Sopenharmony_ci * map looks like this:
98c2ecf20Sopenharmony_ci *
108c2ecf20Sopenharmony_ci * 0  aic7xxx 0
118c2ecf20Sopenharmony_ci * 1  aic7xxx 1
128c2ecf20Sopenharmony_ci * 2  expansion slot
138c2ecf20Sopenharmony_ci * 3  N/C
148c2ecf20Sopenharmony_ci * 4  N/C
158c2ecf20Sopenharmony_ci */
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ci#define SCSI0  MACEPCI_SCSI0_IRQ
188c2ecf20Sopenharmony_ci#define SCSI1  MACEPCI_SCSI1_IRQ
198c2ecf20Sopenharmony_ci#define INTA0  MACEPCI_SLOT0_IRQ
208c2ecf20Sopenharmony_ci#define INTA1  MACEPCI_SLOT1_IRQ
218c2ecf20Sopenharmony_ci#define INTA2  MACEPCI_SLOT2_IRQ
228c2ecf20Sopenharmony_ci#define INTB   MACEPCI_SHARED0_IRQ
238c2ecf20Sopenharmony_ci#define INTC   MACEPCI_SHARED1_IRQ
248c2ecf20Sopenharmony_ci#define INTD   MACEPCI_SHARED2_IRQ
258c2ecf20Sopenharmony_cistatic char irq_tab_mace[][5] = {
268c2ecf20Sopenharmony_ci      /* Dummy	INT#A  INT#B  INT#C  INT#D */
278c2ecf20Sopenharmony_ci	{0,	    0,	   0,	  0,	 0}, /* This is placeholder row - never used */
288c2ecf20Sopenharmony_ci	{0,	SCSI0, SCSI0, SCSI0, SCSI0},
298c2ecf20Sopenharmony_ci	{0,	SCSI1, SCSI1, SCSI1, SCSI1},
308c2ecf20Sopenharmony_ci	{0,	INTA0,	INTB,  INTC,  INTD},
318c2ecf20Sopenharmony_ci	{0,	INTA1,	INTC,  INTD,  INTB},
328c2ecf20Sopenharmony_ci	{0,	INTA2,	INTD,  INTB,  INTC},
338c2ecf20Sopenharmony_ci};
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ci/*
378c2ecf20Sopenharmony_ci * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
388c2ecf20Sopenharmony_ci * the device (1-4 => A-D), tell what irq to use.  Note that we don't
398c2ecf20Sopenharmony_ci * in theory have slots 4 and 5, and we never normally use the shared
408c2ecf20Sopenharmony_ci * irqs.  I suppose a device without a pin A will thank us for doing it
418c2ecf20Sopenharmony_ci * right if there exists such a broken piece of crap.
428c2ecf20Sopenharmony_ci */
438c2ecf20Sopenharmony_ciint pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
448c2ecf20Sopenharmony_ci{
458c2ecf20Sopenharmony_ci	return irq_tab_mace[slot][pin];
468c2ecf20Sopenharmony_ci}
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci/* Do platform specific device initialization at pci_enable_device() time */
498c2ecf20Sopenharmony_ciint pcibios_plat_dev_init(struct pci_dev *dev)
508c2ecf20Sopenharmony_ci{
518c2ecf20Sopenharmony_ci	return 0;
528c2ecf20Sopenharmony_ci}
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