1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Carsten Langgaard, carstenl@mips.com 4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 5 * Copyright (C) 2008 Dmitri Vorobiev 6 */ 7#include <linux/cpu.h> 8#include <linux/init.h> 9#include <linux/sched.h> 10#include <linux/ioport.h> 11#include <linux/irq.h> 12#include <linux/of_fdt.h> 13#include <linux/pci.h> 14#include <linux/screen_info.h> 15#include <linux/time.h> 16 17#include <asm/dma-coherence.h> 18#include <asm/fw/fw.h> 19#include <asm/mips-cps.h> 20#include <asm/mips-boards/generic.h> 21#include <asm/mips-boards/malta.h> 22#include <asm/mips-boards/maltaint.h> 23#include <asm/dma.h> 24#include <asm/prom.h> 25#include <asm/traps.h> 26#ifdef CONFIG_VT 27#include <linux/console.h> 28#endif 29 30#define ROCIT_CONFIG_GEN0 0x1f403000 31#define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7) 32 33static struct resource standard_io_resources[] = { 34 { 35 .name = "dma1", 36 .start = 0x00, 37 .end = 0x1f, 38 .flags = IORESOURCE_IO | IORESOURCE_BUSY 39 }, 40 { 41 .name = "timer", 42 .start = 0x40, 43 .end = 0x5f, 44 .flags = IORESOURCE_IO | IORESOURCE_BUSY 45 }, 46 { 47 .name = "keyboard", 48 .start = 0x60, 49 .end = 0x6f, 50 .flags = IORESOURCE_IO | IORESOURCE_BUSY 51 }, 52 { 53 .name = "dma page reg", 54 .start = 0x80, 55 .end = 0x8f, 56 .flags = IORESOURCE_IO | IORESOURCE_BUSY 57 }, 58 { 59 .name = "dma2", 60 .start = 0xc0, 61 .end = 0xdf, 62 .flags = IORESOURCE_IO | IORESOURCE_BUSY 63 }, 64}; 65 66const char *get_system_type(void) 67{ 68 return "MIPS Malta"; 69} 70 71#ifdef CONFIG_BLK_DEV_FD 72static void __init fd_activate(void) 73{ 74 /* 75 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O 76 * Controller. 77 * Done by YAMON 2.00 onwards 78 */ 79 /* Entering config state. */ 80 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); 81 82 /* Activate floppy controller. */ 83 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); 84 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); 85 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); 86 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); 87 88 /* Exit config state. */ 89 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); 90} 91#endif 92 93static int __init plat_enable_iocoherency(void) 94{ 95 int supported = 0; 96 u32 cfg; 97 98 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { 99 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { 100 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; 101 pr_info("Enabled Bonito CPU coherency\n"); 102 supported = 1; 103 } 104 if (strstr(fw_getcmdline(), "iobcuncached")) { 105 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; 106 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 107 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 108 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 109 pr_info("Disabled Bonito IOBC coherency\n"); 110 } else { 111 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; 112 BONITO_PCIMEMBASECFG |= 113 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 114 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 115 pr_info("Enabled Bonito IOBC coherency\n"); 116 } 117 } else if (mips_cps_numiocu(0) != 0) { 118 /* Nothing special needs to be done to enable coherency */ 119 pr_info("CMP IOCU detected\n"); 120 cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); 121 if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) { 122 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); 123 return 0; 124 } 125 supported = 1; 126 } 127 hw_coherentio = supported; 128 return supported; 129} 130 131static void __init plat_setup_iocoherency(void) 132{ 133 if (plat_enable_iocoherency()) { 134 if (coherentio == IO_COHERENCE_DISABLED) 135 pr_info("Hardware DMA cache coherency disabled\n"); 136 else 137 pr_info("Hardware DMA cache coherency enabled\n"); 138 } else { 139 if (coherentio == IO_COHERENCE_ENABLED) 140 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); 141 else 142 pr_info("Software DMA cache coherency enabled\n"); 143 } 144} 145 146static void __init pci_clock_check(void) 147{ 148 unsigned int __iomem *jmpr_p = 149 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); 150 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; 151 static const int pciclocks[] __initconst = { 152 33, 20, 25, 30, 12, 16, 37, 10 153 }; 154 int pciclock = pciclocks[jmpr]; 155 char *optptr, *argptr = fw_getcmdline(); 156 157 /* 158 * If user passed a pci_clock= option, don't tack on another one 159 */ 160 optptr = strstr(argptr, "pci_clock="); 161 if (optptr && (optptr == argptr || optptr[-1] == ' ')) 162 return; 163 164 if (pciclock != 33) { 165 pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n", 166 pciclock); 167 argptr += strlen(argptr); 168 sprintf(argptr, " pci_clock=%d", pciclock); 169 if (pciclock < 20 || pciclock > 66) 170 pr_warn("WARNING: IDE timing calculations will be " 171 "incorrect\n"); 172 } 173} 174 175#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 176static void __init screen_info_setup(void) 177{ 178 screen_info = (struct screen_info) { 179 .orig_x = 0, 180 .orig_y = 25, 181 .ext_mem_k = 0, 182 .orig_video_page = 0, 183 .orig_video_mode = 0, 184 .orig_video_cols = 80, 185 .unused2 = 0, 186 .orig_video_ega_bx = 0, 187 .unused3 = 0, 188 .orig_video_lines = 25, 189 .orig_video_isVGA = VIDEO_TYPE_VGAC, 190 .orig_video_points = 16 191 }; 192} 193#endif 194 195static void __init bonito_quirks_setup(void) 196{ 197 char *argptr; 198 199 argptr = fw_getcmdline(); 200 if (strstr(argptr, "debug")) { 201 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; 202 pr_info("Enabled Bonito debug mode\n"); 203 } else 204 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; 205} 206 207void __init *plat_get_fdt(void) 208{ 209 return (void *)__dtb_start; 210} 211 212void __init plat_mem_setup(void) 213{ 214 unsigned int i; 215 void *fdt = plat_get_fdt(); 216 217 fdt = malta_dt_shim(fdt); 218 __dt_setup_arch(fdt); 219 220 if (IS_ENABLED(CONFIG_EVA)) 221 /* EVA has already been configured in mach-malta/kernel-init.h */ 222 pr_info("Enhanced Virtual Addressing (EVA) activated\n"); 223 224 mips_pcibios_init(); 225 226 /* Request I/O space for devices used on the Malta board. */ 227 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) 228 request_resource(&ioport_resource, standard_io_resources+i); 229 230 /* 231 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. 232 */ 233 enable_dma(4); 234 235 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) 236 bonito_quirks_setup(); 237 238 plat_setup_iocoherency(); 239 240 pci_clock_check(); 241 242#ifdef CONFIG_BLK_DEV_FD 243 fd_activate(); 244#endif 245 246#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 247 screen_info_setup(); 248#endif 249} 250