18c2ecf20Sopenharmony_ci/*
28c2ecf20Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General Public
38c2ecf20Sopenharmony_ci * License.  See the file "COPYING" in the main directory of this archive
48c2ecf20Sopenharmony_ci * for more details.
58c2ecf20Sopenharmony_ci *
68c2ecf20Sopenharmony_ci * Copyright (C) 2006, 07 MIPS Technologies, Inc.
78c2ecf20Sopenharmony_ci *   written by Ralf Baechle (ralf@linux-mips.org)
88c2ecf20Sopenharmony_ci *     written by Ralf Baechle <ralf@linux-mips.org>
98c2ecf20Sopenharmony_ci *
108c2ecf20Sopenharmony_ci * Copyright (C) 2008 Wind River Systems, Inc.
118c2ecf20Sopenharmony_ci *   updated by Tiejun Chen <tiejun.chen@windriver.com>
128c2ecf20Sopenharmony_ci *
138c2ecf20Sopenharmony_ci * 1. Probe driver for the Malta's UART ports:
148c2ecf20Sopenharmony_ci *
158c2ecf20Sopenharmony_ci *   o 2 ports in the SMC SuperIO
168c2ecf20Sopenharmony_ci *   o 1 port in the CBUS UART, a discrete 16550 which normally is only used
178c2ecf20Sopenharmony_ci *     for bringups.
188c2ecf20Sopenharmony_ci *
198c2ecf20Sopenharmony_ci * We don't use 8250_platform.c on Malta as it would result in the CBUS
208c2ecf20Sopenharmony_ci * UART becoming ttyS0.
218c2ecf20Sopenharmony_ci *
228c2ecf20Sopenharmony_ci * 2. Register RTC-CMOS platform device on Malta.
238c2ecf20Sopenharmony_ci */
248c2ecf20Sopenharmony_ci#include <linux/init.h>
258c2ecf20Sopenharmony_ci#include <linux/serial_8250.h>
268c2ecf20Sopenharmony_ci#include <linux/irq.h>
278c2ecf20Sopenharmony_ci#include <linux/platform_device.h>
288c2ecf20Sopenharmony_ci#include <asm/mips-boards/maltaint.h>
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci#define SMC_PORT(base, int)						\
318c2ecf20Sopenharmony_ci{									\
328c2ecf20Sopenharmony_ci	.iobase		= base,						\
338c2ecf20Sopenharmony_ci	.irq		= int,						\
348c2ecf20Sopenharmony_ci	.uartclk	= 1843200,					\
358c2ecf20Sopenharmony_ci	.iotype		= UPIO_PORT,					\
368c2ecf20Sopenharmony_ci	.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,		\
378c2ecf20Sopenharmony_ci	.regshift	= 0,						\
388c2ecf20Sopenharmony_ci}
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ci#define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_cistatic struct plat_serial8250_port uart8250_data[] = {
438c2ecf20Sopenharmony_ci	SMC_PORT(0x3F8, 4),
448c2ecf20Sopenharmony_ci	SMC_PORT(0x2F8, 3),
458c2ecf20Sopenharmony_ci#ifndef CONFIG_MIPS_CMP
468c2ecf20Sopenharmony_ci	{
478c2ecf20Sopenharmony_ci		.mapbase	= 0x1f000900,	/* The CBUS UART */
488c2ecf20Sopenharmony_ci		.irq		= MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
498c2ecf20Sopenharmony_ci		.uartclk	= 3686400,	/* Twice the usual clk! */
508c2ecf20Sopenharmony_ci		.iotype		= IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) ?
518c2ecf20Sopenharmony_ci				  UPIO_MEM32BE : UPIO_MEM32,
528c2ecf20Sopenharmony_ci		.flags		= CBUS_UART_FLAGS,
538c2ecf20Sopenharmony_ci		.regshift	= 3,
548c2ecf20Sopenharmony_ci	},
558c2ecf20Sopenharmony_ci#endif
568c2ecf20Sopenharmony_ci	{ },
578c2ecf20Sopenharmony_ci};
588c2ecf20Sopenharmony_ci
598c2ecf20Sopenharmony_cistatic struct platform_device malta_uart8250_device = {
608c2ecf20Sopenharmony_ci	.name			= "serial8250",
618c2ecf20Sopenharmony_ci	.id			= PLAT8250_DEV_PLATFORM,
628c2ecf20Sopenharmony_ci	.dev			= {
638c2ecf20Sopenharmony_ci		.platform_data	= uart8250_data,
648c2ecf20Sopenharmony_ci	},
658c2ecf20Sopenharmony_ci};
668c2ecf20Sopenharmony_ci
678c2ecf20Sopenharmony_cistatic struct platform_device *malta_devices[] __initdata = {
688c2ecf20Sopenharmony_ci	&malta_uart8250_device,
698c2ecf20Sopenharmony_ci};
708c2ecf20Sopenharmony_ci
718c2ecf20Sopenharmony_cistatic int __init malta_add_devices(void)
728c2ecf20Sopenharmony_ci{
738c2ecf20Sopenharmony_ci	return platform_add_devices(malta_devices, ARRAY_SIZE(malta_devices));
748c2ecf20Sopenharmony_ci}
758c2ecf20Sopenharmony_ci
768c2ecf20Sopenharmony_cidevice_initcall(malta_add_devices);
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