1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* 3 * Format of an instruction in memory. 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 * 9 * Copyright (C) 1996, 2000 by Ralf Baechle 10 * Copyright (C) 2006 by Thiemo Seufer 11 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 12 * Copyright (C) 2014 Imagination Technologies Ltd. 13 */ 14#ifndef _UAPI_ASM_INST_H 15#define _UAPI_ASM_INST_H 16 17#include <asm/bitfield.h> 18 19/* 20 * Major opcodes; before MIPS IV cop1x was called cop3. 21 */ 22enum major_op { 23 spec_op, bcond_op, j_op, jal_op, 24 beq_op, bne_op, blez_op, bgtz_op, 25 addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op, 26 andi_op, ori_op, xori_op, lui_op, 27 cop0_op, cop1_op, cop2_op, cop1x_op, 28 beql_op, bnel_op, blezl_op, bgtzl_op, 29 daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op, 30 spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op, 31 lb_op, lh_op, lwl_op, lw_op, 32 lbu_op, lhu_op, lwr_op, lwu_op, 33 sb_op, sh_op, swl_op, sw_op, 34 sdl_op, sdr_op, swr_op, cache_op, 35 ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op, 36 lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op, 37 sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op, 38 scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op 39}; 40 41/* 42 * func field of spec opcode. 43 */ 44enum spec_op { 45 sll_op, movc_op, srl_op, sra_op, 46 sllv_op, pmon_op, srlv_op, srav_op, 47 jr_op, jalr_op, movz_op, movn_op, 48 syscall_op, break_op, spim_op, sync_op, 49 mfhi_op, mthi_op, mflo_op, mtlo_op, 50 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, 51 mult_op, multu_op, div_op, divu_op, 52 dmult_op, dmultu_op, ddiv_op, ddivu_op, 53 add_op, addu_op, sub_op, subu_op, 54 and_op, or_op, xor_op, nor_op, 55 spec3_unused_op, spec4_unused_op, slt_op, sltu_op, 56 dadd_op, daddu_op, dsub_op, dsubu_op, 57 tge_op, tgeu_op, tlt_op, tltu_op, 58 teq_op, seleqz_op, tne_op, selnez_op, 59 dsll_op, spec5_unused_op, dsrl_op, dsra_op, 60 dsll32_op, spec6_unused_op, dsrl32_op, dsra32_op 61}; 62 63/* 64 * func field of spec2 opcode. 65 */ 66enum spec2_op { 67 madd_op, maddu_op, mul_op, spec2_3_unused_op, 68 msub_op, msubu_op, /* more unused ops */ 69 clz_op = 0x20, clo_op, 70 dclz_op = 0x24, dclo_op, 71 sdbpp_op = 0x3f 72}; 73 74/* 75 * func field of spec3 opcode. 76 */ 77enum spec3_op { 78 ext_op, dextm_op, dextu_op, dext_op, 79 ins_op, dinsm_op, dinsu_op, dins_op, 80 yield_op = 0x09, lx_op = 0x0a, 81 lwle_op = 0x19, lwre_op = 0x1a, 82 cachee_op = 0x1b, sbe_op = 0x1c, 83 she_op = 0x1d, sce_op = 0x1e, 84 swe_op = 0x1f, bshfl_op = 0x20, 85 swle_op = 0x21, swre_op = 0x22, 86 prefe_op = 0x23, dbshfl_op = 0x24, 87 cache6_op = 0x25, sc6_op = 0x26, 88 scd6_op = 0x27, lbue_op = 0x28, 89 lhue_op = 0x29, lbe_op = 0x2c, 90 lhe_op = 0x2d, lle_op = 0x2e, 91 lwe_op = 0x2f, pref6_op = 0x35, 92 ll6_op = 0x36, lld6_op = 0x37, 93 rdhwr_op = 0x3b 94}; 95 96/* 97 * Bits 10-6 minor opcode for r6 spec mult/div encodings 98 */ 99enum mult_op { 100 mult_mult_op = 0x0, 101 mult_mul_op = 0x2, 102 mult_muh_op = 0x3, 103}; 104enum multu_op { 105 multu_multu_op = 0x0, 106 multu_mulu_op = 0x2, 107 multu_muhu_op = 0x3, 108}; 109enum div_op { 110 div_div_op = 0x0, 111 div_div6_op = 0x2, 112 div_mod_op = 0x3, 113}; 114enum divu_op { 115 divu_divu_op = 0x0, 116 divu_divu6_op = 0x2, 117 divu_modu_op = 0x3, 118}; 119enum dmult_op { 120 dmult_dmult_op = 0x0, 121 dmult_dmul_op = 0x2, 122 dmult_dmuh_op = 0x3, 123}; 124enum dmultu_op { 125 dmultu_dmultu_op = 0x0, 126 dmultu_dmulu_op = 0x2, 127 dmultu_dmuhu_op = 0x3, 128}; 129enum ddiv_op { 130 ddiv_ddiv_op = 0x0, 131 ddiv_ddiv6_op = 0x2, 132 ddiv_dmod_op = 0x3, 133}; 134enum ddivu_op { 135 ddivu_ddivu_op = 0x0, 136 ddivu_ddivu6_op = 0x2, 137 ddivu_dmodu_op = 0x3, 138}; 139 140/* 141 * rt field of bcond opcodes. 142 */ 143enum rt_op { 144 bltz_op, bgez_op, bltzl_op, bgezl_op, 145 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, 146 tgei_op, tgeiu_op, tlti_op, tltiu_op, 147 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, 148 bltzal_op, bgezal_op, bltzall_op, bgezall_op, 149 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, 150 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, 151 bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op 152}; 153 154/* 155 * rs field of cop opcodes. 156 */ 157enum cop_op { 158 mfc_op = 0x00, dmfc_op = 0x01, 159 cfc_op = 0x02, mfhc0_op = 0x02, 160 mfhc_op = 0x03, mtc_op = 0x04, 161 dmtc_op = 0x05, ctc_op = 0x06, 162 mthc0_op = 0x06, mthc_op = 0x07, 163 bc_op = 0x08, bc1eqz_op = 0x09, 164 mfmc0_op = 0x0b, bc1nez_op = 0x0d, 165 wrpgpr_op = 0x0e, cop_op = 0x10, 166 copm_op = 0x18 167}; 168 169/* 170 * rt field of cop.bc_op opcodes 171 */ 172enum bcop_op { 173 bcf_op, bct_op, bcfl_op, bctl_op 174}; 175 176/* 177 * func field of cop0 coi opcodes. 178 */ 179enum cop0_coi_func { 180 tlbr_op = 0x01, tlbwi_op = 0x02, 181 tlbwr_op = 0x06, tlbp_op = 0x08, 182 rfe_op = 0x10, eret_op = 0x18, 183 wait_op = 0x20, hypcall_op = 0x28 184}; 185 186/* 187 * func field of cop0 com opcodes. 188 */ 189enum cop0_com_func { 190 tlbr1_op = 0x01, tlbw_op = 0x02, 191 tlbp1_op = 0x08, dctr_op = 0x09, 192 dctw_op = 0x0a 193}; 194 195/* 196 * fmt field of cop1 opcodes. 197 */ 198enum cop1_fmt { 199 s_fmt, d_fmt, e_fmt, q_fmt, 200 w_fmt, l_fmt 201}; 202 203/* 204 * func field of cop1 instructions using d, s or w format. 205 */ 206enum cop1_sdw_func { 207 fadd_op = 0x00, fsub_op = 0x01, 208 fmul_op = 0x02, fdiv_op = 0x03, 209 fsqrt_op = 0x04, fabs_op = 0x05, 210 fmov_op = 0x06, fneg_op = 0x07, 211 froundl_op = 0x08, ftruncl_op = 0x09, 212 fceill_op = 0x0a, ffloorl_op = 0x0b, 213 fround_op = 0x0c, ftrunc_op = 0x0d, 214 fceil_op = 0x0e, ffloor_op = 0x0f, 215 fsel_op = 0x10, 216 fmovc_op = 0x11, fmovz_op = 0x12, 217 fmovn_op = 0x13, fseleqz_op = 0x14, 218 frecip_op = 0x15, frsqrt_op = 0x16, 219 fselnez_op = 0x17, fmaddf_op = 0x18, 220 fmsubf_op = 0x19, frint_op = 0x1a, 221 fclass_op = 0x1b, fmin_op = 0x1c, 222 fmina_op = 0x1d, fmax_op = 0x1e, 223 fmaxa_op = 0x1f, fcvts_op = 0x20, 224 fcvtd_op = 0x21, fcvte_op = 0x22, 225 fcvtw_op = 0x24, fcvtl_op = 0x25, 226 fcmp_op = 0x30 227}; 228 229/* 230 * func field of cop1x opcodes (MIPS IV). 231 */ 232enum cop1x_func { 233 lwxc1_op = 0x00, ldxc1_op = 0x01, 234 swxc1_op = 0x08, sdxc1_op = 0x09, 235 pfetch_op = 0x0f, madd_s_op = 0x20, 236 madd_d_op = 0x21, madd_e_op = 0x22, 237 msub_s_op = 0x28, msub_d_op = 0x29, 238 msub_e_op = 0x2a, nmadd_s_op = 0x30, 239 nmadd_d_op = 0x31, nmadd_e_op = 0x32, 240 nmsub_s_op = 0x38, nmsub_d_op = 0x39, 241 nmsub_e_op = 0x3a 242}; 243 244/* 245 * func field for mad opcodes (MIPS IV). 246 */ 247enum mad_func { 248 madd_fp_op = 0x08, msub_fp_op = 0x0a, 249 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e 250}; 251 252/* 253 * func field for page table walker (Loongson-3). 254 */ 255enum ptw_func { 256 lwdir_op = 0x00, 257 lwpte_op = 0x01, 258 lddir_op = 0x02, 259 ldpte_op = 0x03, 260}; 261 262/* 263 * func field for special3 lx opcodes (Cavium Octeon). 264 */ 265enum lx_func { 266 lwx_op = 0x00, 267 lhx_op = 0x04, 268 lbux_op = 0x06, 269 ldx_op = 0x08, 270 lwux_op = 0x10, 271 lhux_op = 0x14, 272 lbx_op = 0x16, 273}; 274 275/* 276 * BSHFL opcodes 277 */ 278enum bshfl_func { 279 wsbh_op = 0x2, 280 seb_op = 0x10, 281 seh_op = 0x18, 282}; 283 284/* 285 * DBSHFL opcodes 286 */ 287enum dbshfl_func { 288 dsbh_op = 0x2, 289 dshd_op = 0x5, 290}; 291 292/* 293 * MSA minor opcodes. 294 */ 295enum msa_func { 296 msa_elm_op = 0x19, 297}; 298 299/* 300 * MSA ELM opcodes. 301 */ 302enum msa_elm { 303 msa_ctc_op = 0x3e, 304 msa_cfc_op = 0x7e, 305}; 306 307/* 308 * func field for MSA MI10 format. 309 */ 310enum msa_mi10_func { 311 msa_ld_op = 8, 312 msa_st_op = 9, 313}; 314 315/* 316 * MSA 2 bit format fields. 317 */ 318enum msa_2b_fmt { 319 msa_fmt_b = 0, 320 msa_fmt_h = 1, 321 msa_fmt_w = 2, 322 msa_fmt_d = 3, 323}; 324 325/* 326 * (microMIPS) Major opcodes. 327 */ 328enum mm_major_op { 329 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, 330 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, 331 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, 332 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, 333 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, 334 mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op, 335 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, 336 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, 337 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, 338 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, 339 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, 340 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, 341 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, 342 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, 343 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, 344 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, 345}; 346 347/* 348 * (microMIPS) POOL32I minor opcodes. 349 */ 350enum mm_32i_minor_op { 351 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, 352 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, 353 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, 354 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, 355 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, 356 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, 357 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, 358 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, 359 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, 360}; 361 362/* 363 * (microMIPS) POOL32A minor opcodes. 364 */ 365enum mm_32a_minor_op { 366 mm_sll32_op = 0x000, 367 mm_ins_op = 0x00c, 368 mm_sllv32_op = 0x010, 369 mm_ext_op = 0x02c, 370 mm_pool32axf_op = 0x03c, 371 mm_srl32_op = 0x040, 372 mm_srlv32_op = 0x050, 373 mm_sra_op = 0x080, 374 mm_srav_op = 0x090, 375 mm_rotr_op = 0x0c0, 376 mm_lwxs_op = 0x118, 377 mm_addu32_op = 0x150, 378 mm_subu32_op = 0x1d0, 379 mm_wsbh_op = 0x1ec, 380 mm_mul_op = 0x210, 381 mm_and_op = 0x250, 382 mm_or32_op = 0x290, 383 mm_xor32_op = 0x310, 384 mm_slt_op = 0x350, 385 mm_sltu_op = 0x390, 386}; 387 388/* 389 * (microMIPS) POOL32B functions. 390 */ 391enum mm_32b_func { 392 mm_lwc2_func = 0x0, 393 mm_lwp_func = 0x1, 394 mm_ldc2_func = 0x2, 395 mm_ldp_func = 0x4, 396 mm_lwm32_func = 0x5, 397 mm_cache_func = 0x6, 398 mm_ldm_func = 0x7, 399 mm_swc2_func = 0x8, 400 mm_swp_func = 0x9, 401 mm_sdc2_func = 0xa, 402 mm_sdp_func = 0xc, 403 mm_swm32_func = 0xd, 404 mm_sdm_func = 0xf, 405}; 406 407/* 408 * (microMIPS) POOL32C functions. 409 */ 410enum mm_32c_func { 411 mm_pref_func = 0x2, 412 mm_ll_func = 0x3, 413 mm_swr_func = 0x9, 414 mm_sc_func = 0xb, 415 mm_lwu_func = 0xe, 416}; 417 418/* 419 * (microMIPS) POOL32AXF minor opcodes. 420 */ 421enum mm_32axf_minor_op { 422 mm_mfc0_op = 0x003, 423 mm_mtc0_op = 0x00b, 424 mm_tlbp_op = 0x00d, 425 mm_mfhi32_op = 0x035, 426 mm_jalr_op = 0x03c, 427 mm_tlbr_op = 0x04d, 428 mm_mflo32_op = 0x075, 429 mm_jalrhb_op = 0x07c, 430 mm_tlbwi_op = 0x08d, 431 mm_mthi32_op = 0x0b5, 432 mm_tlbwr_op = 0x0cd, 433 mm_mtlo32_op = 0x0f5, 434 mm_di_op = 0x11d, 435 mm_jalrs_op = 0x13c, 436 mm_jalrshb_op = 0x17c, 437 mm_sync_op = 0x1ad, 438 mm_syscall_op = 0x22d, 439 mm_wait_op = 0x24d, 440 mm_eret_op = 0x3cd, 441 mm_divu_op = 0x5dc, 442}; 443 444/* 445 * (microMIPS) POOL32F minor opcodes. 446 */ 447enum mm_32f_minor_op { 448 mm_32f_00_op = 0x00, 449 mm_32f_01_op = 0x01, 450 mm_32f_02_op = 0x02, 451 mm_32f_10_op = 0x08, 452 mm_32f_11_op = 0x09, 453 mm_32f_12_op = 0x0a, 454 mm_32f_20_op = 0x10, 455 mm_32f_30_op = 0x18, 456 mm_32f_40_op = 0x20, 457 mm_32f_41_op = 0x21, 458 mm_32f_42_op = 0x22, 459 mm_32f_50_op = 0x28, 460 mm_32f_51_op = 0x29, 461 mm_32f_52_op = 0x2a, 462 mm_32f_60_op = 0x30, 463 mm_32f_70_op = 0x38, 464 mm_32f_73_op = 0x3b, 465 mm_32f_74_op = 0x3c, 466}; 467 468/* 469 * (microMIPS) POOL32F secondary minor opcodes. 470 */ 471enum mm_32f_10_minor_op { 472 mm_lwxc1_op = 0x1, 473 mm_swxc1_op, 474 mm_ldxc1_op, 475 mm_sdxc1_op, 476 mm_luxc1_op, 477 mm_suxc1_op, 478}; 479 480enum mm_32f_func { 481 mm_lwxc1_func = 0x048, 482 mm_swxc1_func = 0x088, 483 mm_ldxc1_func = 0x0c8, 484 mm_sdxc1_func = 0x108, 485}; 486 487/* 488 * (microMIPS) POOL32F secondary minor opcodes. 489 */ 490enum mm_32f_40_minor_op { 491 mm_fmovf_op, 492 mm_fmovt_op, 493}; 494 495/* 496 * (microMIPS) POOL32F secondary minor opcodes. 497 */ 498enum mm_32f_60_minor_op { 499 mm_fadd_op, 500 mm_fsub_op, 501 mm_fmul_op, 502 mm_fdiv_op, 503}; 504 505/* 506 * (microMIPS) POOL32F secondary minor opcodes. 507 */ 508enum mm_32f_70_minor_op { 509 mm_fmovn_op, 510 mm_fmovz_op, 511}; 512 513/* 514 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. 515 */ 516enum mm_32f_73_minor_op { 517 mm_fmov0_op = 0x01, 518 mm_fcvtl_op = 0x04, 519 mm_movf0_op = 0x05, 520 mm_frsqrt_op = 0x08, 521 mm_ffloorl_op = 0x0c, 522 mm_fabs0_op = 0x0d, 523 mm_fcvtw_op = 0x24, 524 mm_movt0_op = 0x25, 525 mm_fsqrt_op = 0x28, 526 mm_ffloorw_op = 0x2c, 527 mm_fneg0_op = 0x2d, 528 mm_cfc1_op = 0x40, 529 mm_frecip_op = 0x48, 530 mm_fceill_op = 0x4c, 531 mm_fcvtd0_op = 0x4d, 532 mm_ctc1_op = 0x60, 533 mm_fceilw_op = 0x6c, 534 mm_fcvts0_op = 0x6d, 535 mm_mfc1_op = 0x80, 536 mm_fmov1_op = 0x81, 537 mm_movf1_op = 0x85, 538 mm_ftruncl_op = 0x8c, 539 mm_fabs1_op = 0x8d, 540 mm_mtc1_op = 0xa0, 541 mm_movt1_op = 0xa5, 542 mm_ftruncw_op = 0xac, 543 mm_fneg1_op = 0xad, 544 mm_mfhc1_op = 0xc0, 545 mm_froundl_op = 0xcc, 546 mm_fcvtd1_op = 0xcd, 547 mm_mthc1_op = 0xe0, 548 mm_froundw_op = 0xec, 549 mm_fcvts1_op = 0xed, 550}; 551 552/* 553 * (microMIPS) POOL32S minor opcodes. 554 */ 555enum mm_32s_minor_op { 556 mm_32s_elm_op = 0x16, 557}; 558 559/* 560 * (microMIPS) POOL16C minor opcodes. 561 */ 562enum mm_16c_minor_op { 563 mm_lwm16_op = 0x04, 564 mm_swm16_op = 0x05, 565 mm_jr16_op = 0x0c, 566 mm_jrc_op = 0x0d, 567 mm_jalr16_op = 0x0e, 568 mm_jalrs16_op = 0x0f, 569 mm_jraddiusp_op = 0x18, 570}; 571 572/* 573 * (microMIPS) POOL16D minor opcodes. 574 */ 575enum mm_16d_minor_op { 576 mm_addius5_func, 577 mm_addiusp_func, 578}; 579 580/* 581 * (MIPS16e) opcodes. 582 */ 583enum MIPS16e_ops { 584 MIPS16e_jal_op = 003, 585 MIPS16e_ld_op = 007, 586 MIPS16e_i8_op = 014, 587 MIPS16e_sd_op = 017, 588 MIPS16e_lb_op = 020, 589 MIPS16e_lh_op = 021, 590 MIPS16e_lwsp_op = 022, 591 MIPS16e_lw_op = 023, 592 MIPS16e_lbu_op = 024, 593 MIPS16e_lhu_op = 025, 594 MIPS16e_lwpc_op = 026, 595 MIPS16e_lwu_op = 027, 596 MIPS16e_sb_op = 030, 597 MIPS16e_sh_op = 031, 598 MIPS16e_swsp_op = 032, 599 MIPS16e_sw_op = 033, 600 MIPS16e_rr_op = 035, 601 MIPS16e_extend_op = 036, 602 MIPS16e_i64_op = 037, 603}; 604 605enum MIPS16e_i64_func { 606 MIPS16e_ldsp_func, 607 MIPS16e_sdsp_func, 608 MIPS16e_sdrasp_func, 609 MIPS16e_dadjsp_func, 610 MIPS16e_ldpc_func, 611}; 612 613enum MIPS16e_rr_func { 614 MIPS16e_jr_func, 615}; 616 617enum MIPS6e_i8_func { 618 MIPS16e_swrasp_func = 02, 619}; 620 621/* 622 * (microMIPS) NOP instruction. 623 */ 624#define MM_NOP16 0x0c00 625 626struct j_format { 627 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ 628 __BITFIELD_FIELD(unsigned int target : 26, 629 ;)) 630}; 631 632struct i_format { /* signed immediate format */ 633 __BITFIELD_FIELD(unsigned int opcode : 6, 634 __BITFIELD_FIELD(unsigned int rs : 5, 635 __BITFIELD_FIELD(unsigned int rt : 5, 636 __BITFIELD_FIELD(signed int simmediate : 16, 637 ;)))) 638}; 639 640struct u_format { /* unsigned immediate format */ 641 __BITFIELD_FIELD(unsigned int opcode : 6, 642 __BITFIELD_FIELD(unsigned int rs : 5, 643 __BITFIELD_FIELD(unsigned int rt : 5, 644 __BITFIELD_FIELD(unsigned int uimmediate : 16, 645 ;)))) 646}; 647 648struct c_format { /* Cache (>= R6000) format */ 649 __BITFIELD_FIELD(unsigned int opcode : 6, 650 __BITFIELD_FIELD(unsigned int rs : 5, 651 __BITFIELD_FIELD(unsigned int c_op : 3, 652 __BITFIELD_FIELD(unsigned int cache : 2, 653 __BITFIELD_FIELD(unsigned int simmediate : 16, 654 ;))))) 655}; 656 657struct r_format { /* Register format */ 658 __BITFIELD_FIELD(unsigned int opcode : 6, 659 __BITFIELD_FIELD(unsigned int rs : 5, 660 __BITFIELD_FIELD(unsigned int rt : 5, 661 __BITFIELD_FIELD(unsigned int rd : 5, 662 __BITFIELD_FIELD(unsigned int re : 5, 663 __BITFIELD_FIELD(unsigned int func : 6, 664 ;)))))) 665}; 666 667struct c0r_format { /* C0 register format */ 668 __BITFIELD_FIELD(unsigned int opcode : 6, 669 __BITFIELD_FIELD(unsigned int rs : 5, 670 __BITFIELD_FIELD(unsigned int rt : 5, 671 __BITFIELD_FIELD(unsigned int rd : 5, 672 __BITFIELD_FIELD(unsigned int z: 8, 673 __BITFIELD_FIELD(unsigned int sel : 3, 674 ;)))))) 675}; 676 677struct mfmc0_format { /* MFMC0 register format */ 678 __BITFIELD_FIELD(unsigned int opcode : 6, 679 __BITFIELD_FIELD(unsigned int rs : 5, 680 __BITFIELD_FIELD(unsigned int rt : 5, 681 __BITFIELD_FIELD(unsigned int rd : 5, 682 __BITFIELD_FIELD(unsigned int re : 5, 683 __BITFIELD_FIELD(unsigned int sc : 1, 684 __BITFIELD_FIELD(unsigned int : 2, 685 __BITFIELD_FIELD(unsigned int sel : 3, 686 ;)))))))) 687}; 688 689struct co_format { /* C0 CO format */ 690 __BITFIELD_FIELD(unsigned int opcode : 6, 691 __BITFIELD_FIELD(unsigned int co : 1, 692 __BITFIELD_FIELD(unsigned int code : 19, 693 __BITFIELD_FIELD(unsigned int func : 6, 694 ;)))) 695}; 696 697struct p_format { /* Performance counter format (R10000) */ 698 __BITFIELD_FIELD(unsigned int opcode : 6, 699 __BITFIELD_FIELD(unsigned int rs : 5, 700 __BITFIELD_FIELD(unsigned int rt : 5, 701 __BITFIELD_FIELD(unsigned int rd : 5, 702 __BITFIELD_FIELD(unsigned int re : 5, 703 __BITFIELD_FIELD(unsigned int func : 6, 704 ;)))))) 705}; 706 707struct f_format { /* FPU register format */ 708 __BITFIELD_FIELD(unsigned int opcode : 6, 709 __BITFIELD_FIELD(unsigned int : 1, 710 __BITFIELD_FIELD(unsigned int fmt : 4, 711 __BITFIELD_FIELD(unsigned int rt : 5, 712 __BITFIELD_FIELD(unsigned int rd : 5, 713 __BITFIELD_FIELD(unsigned int re : 5, 714 __BITFIELD_FIELD(unsigned int func : 6, 715 ;))))))) 716}; 717 718struct ma_format { /* FPU multiply and add format (MIPS IV) */ 719 __BITFIELD_FIELD(unsigned int opcode : 6, 720 __BITFIELD_FIELD(unsigned int fr : 5, 721 __BITFIELD_FIELD(unsigned int ft : 5, 722 __BITFIELD_FIELD(unsigned int fs : 5, 723 __BITFIELD_FIELD(unsigned int fd : 5, 724 __BITFIELD_FIELD(unsigned int func : 4, 725 __BITFIELD_FIELD(unsigned int fmt : 2, 726 ;))))))) 727}; 728 729struct b_format { /* BREAK and SYSCALL */ 730 __BITFIELD_FIELD(unsigned int opcode : 6, 731 __BITFIELD_FIELD(unsigned int code : 20, 732 __BITFIELD_FIELD(unsigned int func : 6, 733 ;))) 734}; 735 736struct ps_format { /* MIPS-3D / paired single format */ 737 __BITFIELD_FIELD(unsigned int opcode : 6, 738 __BITFIELD_FIELD(unsigned int rs : 5, 739 __BITFIELD_FIELD(unsigned int ft : 5, 740 __BITFIELD_FIELD(unsigned int fs : 5, 741 __BITFIELD_FIELD(unsigned int fd : 5, 742 __BITFIELD_FIELD(unsigned int func : 6, 743 ;)))))) 744}; 745 746struct v_format { /* MDMX vector format */ 747 __BITFIELD_FIELD(unsigned int opcode : 6, 748 __BITFIELD_FIELD(unsigned int sel : 4, 749 __BITFIELD_FIELD(unsigned int fmt : 1, 750 __BITFIELD_FIELD(unsigned int vt : 5, 751 __BITFIELD_FIELD(unsigned int vs : 5, 752 __BITFIELD_FIELD(unsigned int vd : 5, 753 __BITFIELD_FIELD(unsigned int func : 6, 754 ;))))))) 755}; 756 757struct msa_mi10_format { /* MSA MI10 */ 758 __BITFIELD_FIELD(unsigned int opcode : 6, 759 __BITFIELD_FIELD(signed int s10 : 10, 760 __BITFIELD_FIELD(unsigned int rs : 5, 761 __BITFIELD_FIELD(unsigned int wd : 5, 762 __BITFIELD_FIELD(unsigned int func : 4, 763 __BITFIELD_FIELD(unsigned int df : 2, 764 ;)))))) 765}; 766 767struct dsp_format { /* SPEC3 DSP format instructions */ 768 __BITFIELD_FIELD(unsigned int opcode : 6, 769 __BITFIELD_FIELD(unsigned int base : 5, 770 __BITFIELD_FIELD(unsigned int index : 5, 771 __BITFIELD_FIELD(unsigned int rd : 5, 772 __BITFIELD_FIELD(unsigned int op : 5, 773 __BITFIELD_FIELD(unsigned int func : 6, 774 ;)))))) 775}; 776 777struct spec3_format { /* SPEC3 */ 778 __BITFIELD_FIELD(unsigned int opcode:6, 779 __BITFIELD_FIELD(unsigned int rs:5, 780 __BITFIELD_FIELD(unsigned int rt:5, 781 __BITFIELD_FIELD(signed int simmediate:9, 782 __BITFIELD_FIELD(unsigned int func:7, 783 ;))))) 784}; 785 786/* 787 * microMIPS instruction formats (32-bit length) 788 * 789 * NOTE: 790 * Parenthesis denote whether the format is a microMIPS instruction or 791 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. 792 */ 793struct fb_format { /* FPU branch format (MIPS32) */ 794 __BITFIELD_FIELD(unsigned int opcode : 6, 795 __BITFIELD_FIELD(unsigned int bc : 5, 796 __BITFIELD_FIELD(unsigned int cc : 3, 797 __BITFIELD_FIELD(unsigned int flag : 2, 798 __BITFIELD_FIELD(signed int simmediate : 16, 799 ;))))) 800}; 801 802struct fp0_format { /* FPU multiply and add format (MIPS32) */ 803 __BITFIELD_FIELD(unsigned int opcode : 6, 804 __BITFIELD_FIELD(unsigned int fmt : 5, 805 __BITFIELD_FIELD(unsigned int ft : 5, 806 __BITFIELD_FIELD(unsigned int fs : 5, 807 __BITFIELD_FIELD(unsigned int fd : 5, 808 __BITFIELD_FIELD(unsigned int func : 6, 809 ;)))))) 810}; 811 812struct mm_fp0_format { /* FPU multiply and add format (microMIPS) */ 813 __BITFIELD_FIELD(unsigned int opcode : 6, 814 __BITFIELD_FIELD(unsigned int ft : 5, 815 __BITFIELD_FIELD(unsigned int fs : 5, 816 __BITFIELD_FIELD(unsigned int fd : 5, 817 __BITFIELD_FIELD(unsigned int fmt : 3, 818 __BITFIELD_FIELD(unsigned int op : 2, 819 __BITFIELD_FIELD(unsigned int func : 6, 820 ;))))))) 821}; 822 823struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ 824 __BITFIELD_FIELD(unsigned int opcode : 6, 825 __BITFIELD_FIELD(unsigned int op : 5, 826 __BITFIELD_FIELD(unsigned int rt : 5, 827 __BITFIELD_FIELD(unsigned int fs : 5, 828 __BITFIELD_FIELD(unsigned int fd : 5, 829 __BITFIELD_FIELD(unsigned int func : 6, 830 ;)))))) 831}; 832 833struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ 834 __BITFIELD_FIELD(unsigned int opcode : 6, 835 __BITFIELD_FIELD(unsigned int rt : 5, 836 __BITFIELD_FIELD(unsigned int fs : 5, 837 __BITFIELD_FIELD(unsigned int fmt : 2, 838 __BITFIELD_FIELD(unsigned int op : 8, 839 __BITFIELD_FIELD(unsigned int func : 6, 840 ;)))))) 841}; 842 843struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ 844 __BITFIELD_FIELD(unsigned int opcode : 6, 845 __BITFIELD_FIELD(unsigned int fd : 5, 846 __BITFIELD_FIELD(unsigned int fs : 5, 847 __BITFIELD_FIELD(unsigned int cc : 3, 848 __BITFIELD_FIELD(unsigned int zero : 2, 849 __BITFIELD_FIELD(unsigned int fmt : 2, 850 __BITFIELD_FIELD(unsigned int op : 3, 851 __BITFIELD_FIELD(unsigned int func : 6, 852 ;)))))))) 853}; 854 855struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ 856 __BITFIELD_FIELD(unsigned int opcode : 6, 857 __BITFIELD_FIELD(unsigned int rt : 5, 858 __BITFIELD_FIELD(unsigned int fs : 5, 859 __BITFIELD_FIELD(unsigned int fmt : 3, 860 __BITFIELD_FIELD(unsigned int op : 7, 861 __BITFIELD_FIELD(unsigned int func : 6, 862 ;)))))) 863}; 864 865struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ 866 __BITFIELD_FIELD(unsigned int opcode : 6, 867 __BITFIELD_FIELD(unsigned int rt : 5, 868 __BITFIELD_FIELD(unsigned int fs : 5, 869 __BITFIELD_FIELD(unsigned int cc : 3, 870 __BITFIELD_FIELD(unsigned int fmt : 3, 871 __BITFIELD_FIELD(unsigned int cond : 4, 872 __BITFIELD_FIELD(unsigned int func : 6, 873 ;))))))) 874}; 875 876struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ 877 __BITFIELD_FIELD(unsigned int opcode : 6, 878 __BITFIELD_FIELD(unsigned int index : 5, 879 __BITFIELD_FIELD(unsigned int base : 5, 880 __BITFIELD_FIELD(unsigned int fd : 5, 881 __BITFIELD_FIELD(unsigned int op : 5, 882 __BITFIELD_FIELD(unsigned int func : 6, 883 ;)))))) 884}; 885 886struct fp6_format { /* FPU madd and msub format (MIPS IV) */ 887 __BITFIELD_FIELD(unsigned int opcode : 6, 888 __BITFIELD_FIELD(unsigned int fr : 5, 889 __BITFIELD_FIELD(unsigned int ft : 5, 890 __BITFIELD_FIELD(unsigned int fs : 5, 891 __BITFIELD_FIELD(unsigned int fd : 5, 892 __BITFIELD_FIELD(unsigned int func : 6, 893 ;)))))) 894}; 895 896struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ 897 __BITFIELD_FIELD(unsigned int opcode : 6, 898 __BITFIELD_FIELD(unsigned int ft : 5, 899 __BITFIELD_FIELD(unsigned int fs : 5, 900 __BITFIELD_FIELD(unsigned int fd : 5, 901 __BITFIELD_FIELD(unsigned int fr : 5, 902 __BITFIELD_FIELD(unsigned int func : 6, 903 ;)))))) 904}; 905 906struct mm_i_format { /* Immediate format (microMIPS) */ 907 __BITFIELD_FIELD(unsigned int opcode : 6, 908 __BITFIELD_FIELD(unsigned int rt : 5, 909 __BITFIELD_FIELD(unsigned int rs : 5, 910 __BITFIELD_FIELD(signed int simmediate : 16, 911 ;)))) 912}; 913 914struct mm_m_format { /* Multi-word load/store format (microMIPS) */ 915 __BITFIELD_FIELD(unsigned int opcode : 6, 916 __BITFIELD_FIELD(unsigned int rd : 5, 917 __BITFIELD_FIELD(unsigned int base : 5, 918 __BITFIELD_FIELD(unsigned int func : 4, 919 __BITFIELD_FIELD(signed int simmediate : 12, 920 ;))))) 921}; 922 923struct mm_x_format { /* Scaled indexed load format (microMIPS) */ 924 __BITFIELD_FIELD(unsigned int opcode : 6, 925 __BITFIELD_FIELD(unsigned int index : 5, 926 __BITFIELD_FIELD(unsigned int base : 5, 927 __BITFIELD_FIELD(unsigned int rd : 5, 928 __BITFIELD_FIELD(unsigned int func : 11, 929 ;))))) 930}; 931 932struct mm_a_format { /* ADDIUPC format (microMIPS) */ 933 __BITFIELD_FIELD(unsigned int opcode : 6, 934 __BITFIELD_FIELD(unsigned int rs : 3, 935 __BITFIELD_FIELD(signed int simmediate : 23, 936 ;))) 937}; 938 939/* 940 * microMIPS instruction formats (16-bit length) 941 */ 942struct mm_b0_format { /* Unconditional branch format (microMIPS) */ 943 __BITFIELD_FIELD(unsigned int opcode : 6, 944 __BITFIELD_FIELD(signed int simmediate : 10, 945 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 946 ;))) 947}; 948 949struct mm_b1_format { /* Conditional branch format (microMIPS) */ 950 __BITFIELD_FIELD(unsigned int opcode : 6, 951 __BITFIELD_FIELD(unsigned int rs : 3, 952 __BITFIELD_FIELD(signed int simmediate : 7, 953 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 954 ;)))) 955}; 956 957struct mm16_m_format { /* Multi-word load/store format */ 958 __BITFIELD_FIELD(unsigned int opcode : 6, 959 __BITFIELD_FIELD(unsigned int func : 4, 960 __BITFIELD_FIELD(unsigned int rlist : 2, 961 __BITFIELD_FIELD(unsigned int imm : 4, 962 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 963 ;))))) 964}; 965 966struct mm16_rb_format { /* Signed immediate format */ 967 __BITFIELD_FIELD(unsigned int opcode : 6, 968 __BITFIELD_FIELD(unsigned int rt : 3, 969 __BITFIELD_FIELD(unsigned int base : 3, 970 __BITFIELD_FIELD(signed int simmediate : 4, 971 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 972 ;))))) 973}; 974 975struct mm16_r3_format { /* Load from global pointer format */ 976 __BITFIELD_FIELD(unsigned int opcode : 6, 977 __BITFIELD_FIELD(unsigned int rt : 3, 978 __BITFIELD_FIELD(signed int simmediate : 7, 979 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 980 ;)))) 981}; 982 983struct mm16_r5_format { /* Load/store from stack pointer format */ 984 __BITFIELD_FIELD(unsigned int opcode : 6, 985 __BITFIELD_FIELD(unsigned int rt : 5, 986 __BITFIELD_FIELD(unsigned int imm : 5, 987 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 988 ;)))) 989}; 990 991/* 992 * Loongson-3 overridden COP2 instruction formats (32-bit length) 993 */ 994struct loongson3_lswc2_format { /* Loongson-3 overridden lwc2/swc2 Load/Store format */ 995 __BITFIELD_FIELD(unsigned int opcode : 6, 996 __BITFIELD_FIELD(unsigned int base : 5, 997 __BITFIELD_FIELD(unsigned int rt : 5, 998 __BITFIELD_FIELD(unsigned int fr : 1, 999 __BITFIELD_FIELD(unsigned int offset : 9, 1000 __BITFIELD_FIELD(unsigned int ls : 1, 1001 __BITFIELD_FIELD(unsigned int rq : 5, 1002 ;))))))) 1003}; 1004 1005struct loongson3_lsdc2_format { /* Loongson-3 overridden ldc2/sdc2 Load/Store format */ 1006 __BITFIELD_FIELD(unsigned int opcode : 6, 1007 __BITFIELD_FIELD(unsigned int base : 5, 1008 __BITFIELD_FIELD(unsigned int rt : 5, 1009 __BITFIELD_FIELD(unsigned int index : 5, 1010 __BITFIELD_FIELD(unsigned int offset : 8, 1011 __BITFIELD_FIELD(unsigned int opcode1 : 3, 1012 ;)))))) 1013}; 1014 1015struct loongson3_lscsr_format { /* Loongson-3 CPUCFG&CSR read/write format */ 1016 __BITFIELD_FIELD(unsigned int opcode : 6, 1017 __BITFIELD_FIELD(unsigned int rs : 5, 1018 __BITFIELD_FIELD(unsigned int fr : 5, 1019 __BITFIELD_FIELD(unsigned int rd : 5, 1020 __BITFIELD_FIELD(unsigned int fd : 5, 1021 __BITFIELD_FIELD(unsigned int func : 6, 1022 ;)))))) 1023}; 1024 1025/* 1026 * MIPS16e instruction formats (16-bit length) 1027 */ 1028struct m16e_rr { 1029 __BITFIELD_FIELD(unsigned int opcode : 5, 1030 __BITFIELD_FIELD(unsigned int rx : 3, 1031 __BITFIELD_FIELD(unsigned int nd : 1, 1032 __BITFIELD_FIELD(unsigned int l : 1, 1033 __BITFIELD_FIELD(unsigned int ra : 1, 1034 __BITFIELD_FIELD(unsigned int func : 5, 1035 ;)))))) 1036}; 1037 1038struct m16e_jal { 1039 __BITFIELD_FIELD(unsigned int opcode : 5, 1040 __BITFIELD_FIELD(unsigned int x : 1, 1041 __BITFIELD_FIELD(unsigned int imm20_16 : 5, 1042 __BITFIELD_FIELD(signed int imm25_21 : 5, 1043 ;)))) 1044}; 1045 1046struct m16e_i64 { 1047 __BITFIELD_FIELD(unsigned int opcode : 5, 1048 __BITFIELD_FIELD(unsigned int func : 3, 1049 __BITFIELD_FIELD(unsigned int imm : 8, 1050 ;))) 1051}; 1052 1053struct m16e_ri64 { 1054 __BITFIELD_FIELD(unsigned int opcode : 5, 1055 __BITFIELD_FIELD(unsigned int func : 3, 1056 __BITFIELD_FIELD(unsigned int ry : 3, 1057 __BITFIELD_FIELD(unsigned int imm : 5, 1058 ;)))) 1059}; 1060 1061struct m16e_ri { 1062 __BITFIELD_FIELD(unsigned int opcode : 5, 1063 __BITFIELD_FIELD(unsigned int rx : 3, 1064 __BITFIELD_FIELD(unsigned int imm : 8, 1065 ;))) 1066}; 1067 1068struct m16e_rri { 1069 __BITFIELD_FIELD(unsigned int opcode : 5, 1070 __BITFIELD_FIELD(unsigned int rx : 3, 1071 __BITFIELD_FIELD(unsigned int ry : 3, 1072 __BITFIELD_FIELD(unsigned int imm : 5, 1073 ;)))) 1074}; 1075 1076struct m16e_i8 { 1077 __BITFIELD_FIELD(unsigned int opcode : 5, 1078 __BITFIELD_FIELD(unsigned int func : 3, 1079 __BITFIELD_FIELD(unsigned int imm : 8, 1080 ;))) 1081}; 1082 1083union mips_instruction { 1084 unsigned int word; 1085 unsigned short halfword[2]; 1086 unsigned char byte[4]; 1087 struct j_format j_format; 1088 struct i_format i_format; 1089 struct u_format u_format; 1090 struct c_format c_format; 1091 struct r_format r_format; 1092 struct c0r_format c0r_format; 1093 struct mfmc0_format mfmc0_format; 1094 struct co_format co_format; 1095 struct p_format p_format; 1096 struct f_format f_format; 1097 struct ma_format ma_format; 1098 struct msa_mi10_format msa_mi10_format; 1099 struct b_format b_format; 1100 struct ps_format ps_format; 1101 struct v_format v_format; 1102 struct dsp_format dsp_format; 1103 struct spec3_format spec3_format; 1104 struct fb_format fb_format; 1105 struct fp0_format fp0_format; 1106 struct mm_fp0_format mm_fp0_format; 1107 struct fp1_format fp1_format; 1108 struct mm_fp1_format mm_fp1_format; 1109 struct mm_fp2_format mm_fp2_format; 1110 struct mm_fp3_format mm_fp3_format; 1111 struct mm_fp4_format mm_fp4_format; 1112 struct mm_fp5_format mm_fp5_format; 1113 struct fp6_format fp6_format; 1114 struct mm_fp6_format mm_fp6_format; 1115 struct mm_i_format mm_i_format; 1116 struct mm_m_format mm_m_format; 1117 struct mm_x_format mm_x_format; 1118 struct mm_a_format mm_a_format; 1119 struct mm_b0_format mm_b0_format; 1120 struct mm_b1_format mm_b1_format; 1121 struct mm16_m_format mm16_m_format ; 1122 struct mm16_rb_format mm16_rb_format; 1123 struct mm16_r3_format mm16_r3_format; 1124 struct mm16_r5_format mm16_r5_format; 1125 struct loongson3_lswc2_format loongson3_lswc2_format; 1126 struct loongson3_lsdc2_format loongson3_lsdc2_format; 1127 struct loongson3_lscsr_format loongson3_lscsr_format; 1128}; 1129 1130union mips16e_instruction { 1131 unsigned int full : 16; 1132 struct m16e_rr rr; 1133 struct m16e_jal jal; 1134 struct m16e_i64 i64; 1135 struct m16e_ri64 ri64; 1136 struct m16e_ri ri; 1137 struct m16e_rri rri; 1138 struct m16e_i8 i8; 1139}; 1140 1141#endif /* _UAPI_ASM_INST_H */ 1142