18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * include/asm-mips/txx9tmr.h 38c2ecf20Sopenharmony_ci * TX39/TX49 timer controller definitions. 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General Public 68c2ecf20Sopenharmony_ci * License. See the file "COPYING" in the main directory of this archive 78c2ecf20Sopenharmony_ci * for more details. 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci#ifndef __ASM_TXX9TMR_H 108c2ecf20Sopenharmony_ci#define __ASM_TXX9TMR_H 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <linux/types.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_cistruct txx9_tmr_reg { 158c2ecf20Sopenharmony_ci u32 tcr; 168c2ecf20Sopenharmony_ci u32 tisr; 178c2ecf20Sopenharmony_ci u32 cpra; 188c2ecf20Sopenharmony_ci u32 cprb; 198c2ecf20Sopenharmony_ci u32 itmr; 208c2ecf20Sopenharmony_ci u32 unused0[3]; 218c2ecf20Sopenharmony_ci u32 ccdr; 228c2ecf20Sopenharmony_ci u32 unused1[3]; 238c2ecf20Sopenharmony_ci u32 pgmr; 248c2ecf20Sopenharmony_ci u32 unused2[3]; 258c2ecf20Sopenharmony_ci u32 wtmr; 268c2ecf20Sopenharmony_ci u32 unused3[43]; 278c2ecf20Sopenharmony_ci u32 trr; 288c2ecf20Sopenharmony_ci}; 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci/* TMTCR : Timer Control */ 318c2ecf20Sopenharmony_ci#define TXx9_TMTCR_TCE 0x00000080 328c2ecf20Sopenharmony_ci#define TXx9_TMTCR_CCDE 0x00000040 338c2ecf20Sopenharmony_ci#define TXx9_TMTCR_CRE 0x00000020 348c2ecf20Sopenharmony_ci#define TXx9_TMTCR_ECES 0x00000008 358c2ecf20Sopenharmony_ci#define TXx9_TMTCR_CCS 0x00000004 368c2ecf20Sopenharmony_ci#define TXx9_TMTCR_TMODE_MASK 0x00000003 378c2ecf20Sopenharmony_ci#define TXx9_TMTCR_TMODE_ITVL 0x00000000 388c2ecf20Sopenharmony_ci#define TXx9_TMTCR_TMODE_PGEN 0x00000001 398c2ecf20Sopenharmony_ci#define TXx9_TMTCR_TMODE_WDOG 0x00000002 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci/* TMTISR : Timer Int. Status */ 428c2ecf20Sopenharmony_ci#define TXx9_TMTISR_TPIBS 0x00000004 438c2ecf20Sopenharmony_ci#define TXx9_TMTISR_TPIAS 0x00000002 448c2ecf20Sopenharmony_ci#define TXx9_TMTISR_TIIS 0x00000001 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci/* TMITMR : Interval Timer Mode */ 478c2ecf20Sopenharmony_ci#define TXx9_TMITMR_TIIE 0x00008000 488c2ecf20Sopenharmony_ci#define TXx9_TMITMR_TZCE 0x00000001 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci/* TMWTMR : Watchdog Timer Mode */ 518c2ecf20Sopenharmony_ci#define TXx9_TMWTMR_TWIE 0x00008000 528c2ecf20Sopenharmony_ci#define TXx9_TMWTMR_WDIS 0x00000080 538c2ecf20Sopenharmony_ci#define TXx9_TMWTMR_TWC 0x00000001 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_civoid txx9_clocksource_init(unsigned long baseaddr, 568c2ecf20Sopenharmony_ci unsigned int imbusclk); 578c2ecf20Sopenharmony_civoid txx9_clockevent_init(unsigned long baseaddr, int irq, 588c2ecf20Sopenharmony_ci unsigned int imbusclk); 598c2ecf20Sopenharmony_civoid txx9_tmr_init(unsigned long baseaddr); 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci#ifdef CONFIG_CPU_TX39XX 628c2ecf20Sopenharmony_ci#define TXX9_TIMER_BITS 24 638c2ecf20Sopenharmony_ci#else 648c2ecf20Sopenharmony_ci#define TXX9_TIMER_BITS 32 658c2ecf20Sopenharmony_ci#endif 668c2ecf20Sopenharmony_ci 678c2ecf20Sopenharmony_ci#endif /* __ASM_TXX9TMR_H */ 68