18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright 2002 Integrated Device Technology, Inc. 48c2ecf20Sopenharmony_ci * All rights reserved. 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * GPIO register definition. 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * Author : ryan.holmQVist@idt.com 98c2ecf20Sopenharmony_ci * Date : 20011005 108c2ecf20Sopenharmony_ci * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com> 118c2ecf20Sopenharmony_ci * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> 128c2ecf20Sopenharmony_ci */ 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#ifndef _RC32434_GPIO_H_ 158c2ecf20Sopenharmony_ci#define _RC32434_GPIO_H_ 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_cistruct rb532_gpio_reg { 188c2ecf20Sopenharmony_ci u32 gpiofunc; /* GPIO Function Register 198c2ecf20Sopenharmony_ci * gpiofunc[x]==0 bit = gpio 208c2ecf20Sopenharmony_ci * func[x]==1 bit = altfunc 218c2ecf20Sopenharmony_ci */ 228c2ecf20Sopenharmony_ci u32 gpiocfg; /* GPIO Configuration Register 238c2ecf20Sopenharmony_ci * gpiocfg[x]==0 bit = input 248c2ecf20Sopenharmony_ci * gpiocfg[x]==1 bit = output 258c2ecf20Sopenharmony_ci */ 268c2ecf20Sopenharmony_ci u32 gpiod; /* GPIO Data Register 278c2ecf20Sopenharmony_ci * gpiod[x] read/write gpio pinX status 288c2ecf20Sopenharmony_ci */ 298c2ecf20Sopenharmony_ci u32 gpioilevel; /* GPIO Interrupt Status Register 308c2ecf20Sopenharmony_ci * interrupt level (see gpioistat) 318c2ecf20Sopenharmony_ci */ 328c2ecf20Sopenharmony_ci u32 gpioistat; /* Gpio Interrupt Status Register 338c2ecf20Sopenharmony_ci * istat[x] = (gpiod[x] == level[x]) 348c2ecf20Sopenharmony_ci * cleared in ISR (STICKY bits) 358c2ecf20Sopenharmony_ci */ 368c2ecf20Sopenharmony_ci u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */ 378c2ecf20Sopenharmony_ci}; 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci/* UART GPIO signals */ 408c2ecf20Sopenharmony_ci#define RC32434_UART0_SOUT (1 << 0) 418c2ecf20Sopenharmony_ci#define RC32434_UART0_SIN (1 << 1) 428c2ecf20Sopenharmony_ci#define RC32434_UART0_RTS (1 << 2) 438c2ecf20Sopenharmony_ci#define RC32434_UART0_CTS (1 << 3) 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci/* M & P bus GPIO signals */ 468c2ecf20Sopenharmony_ci#define RC32434_MP_BIT_22 (1 << 4) 478c2ecf20Sopenharmony_ci#define RC32434_MP_BIT_23 (1 << 5) 488c2ecf20Sopenharmony_ci#define RC32434_MP_BIT_24 (1 << 6) 498c2ecf20Sopenharmony_ci#define RC32434_MP_BIT_25 (1 << 7) 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci/* CPU GPIO signals */ 528c2ecf20Sopenharmony_ci#define RC32434_CPU_GPIO (1 << 8) 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci/* Reserved GPIO signals */ 558c2ecf20Sopenharmony_ci#define RC32434_AF_SPARE_6 (1 << 9) 568c2ecf20Sopenharmony_ci#define RC32434_AF_SPARE_4 (1 << 10) 578c2ecf20Sopenharmony_ci#define RC32434_AF_SPARE_3 (1 << 11) 588c2ecf20Sopenharmony_ci#define RC32434_AF_SPARE_2 (1 << 12) 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci/* PCI messaging unit */ 618c2ecf20Sopenharmony_ci#define RC32434_PCI_MSU_GPIO (1 << 13) 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci/* NAND GPIO signals */ 648c2ecf20Sopenharmony_ci#define GPIO_RDY 8 658c2ecf20Sopenharmony_ci#define GPIO_WPX 9 668c2ecf20Sopenharmony_ci#define GPIO_ALE 10 678c2ecf20Sopenharmony_ci#define GPIO_CLE 11 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_ci/* Compact Flash GPIO pin */ 708c2ecf20Sopenharmony_ci#define CF_GPIO_NUM 13 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci/* S1 button GPIO (shared with UART0_SIN) */ 738c2ecf20Sopenharmony_ci#define GPIO_BTN_S1 1 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_ciextern void rb532_gpio_set_ilevel(int bit, unsigned gpio); 768c2ecf20Sopenharmony_ciextern void rb532_gpio_set_istat(int bit, unsigned gpio); 778c2ecf20Sopenharmony_ciextern void rb532_gpio_set_func(unsigned gpio); 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_ci#endif /* _RC32434_GPIO_H_ */ 80