18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> 48c2ecf20Sopenharmony_ci * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com> 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#ifndef __ASM_MACH_LOONGSON2EF_PCI_H_ 88c2ecf20Sopenharmony_ci#define __ASM_MACH_LOONGSON2EF_PCI_H_ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ciextern struct pci_ops loongson_pci_ops; 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci/* this is an offset from mips_io_port_base */ 138c2ecf20Sopenharmony_ci#define LOONGSON_PCI_IO_START 0x00004000UL 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci/* 188c2ecf20Sopenharmony_ci * we use address window2 to map cpu address space to pci space 198c2ecf20Sopenharmony_ci * window2: cpu [1G, 2G] -> pci [1G, 2G] 208c2ecf20Sopenharmony_ci * why not use window 0 & 1? because they are used by cpu when booting. 218c2ecf20Sopenharmony_ci * window0: cpu [0, 256M] -> ddr [0, 256M] 228c2ecf20Sopenharmony_ci * window1: cpu [256M, 512M] -> pci [256M, 512M] 238c2ecf20Sopenharmony_ci */ 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ 268c2ecf20Sopenharmony_ci#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ 278c2ecf20Sopenharmony_ci#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST 308c2ecf20Sopenharmony_ci#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ 338c2ecf20Sopenharmony_ci LOONGSON_PCI_MEM_START + 1) 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci#else /* loongson2f/32bit & loongson2e */ 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci/* this pci memory space is mapped by pcimap in pci.c */ 388c2ecf20Sopenharmony_ci#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE 398c2ecf20Sopenharmony_ci#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2) 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci/* this is an offset from mips_io_port_base */ 428c2ecf20Sopenharmony_ci#define LOONGSON_PCI_IO_START 0x00004000UL 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */ 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci#endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */ 47