18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci *	include/asm-mips/dec/kn05.h
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci *	DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
68c2ecf20Sopenharmony_ci *	or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
78c2ecf20Sopenharmony_ci *	KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
88c2ecf20Sopenharmony_ci *	definitions.
98c2ecf20Sopenharmony_ci *
108c2ecf20Sopenharmony_ci *	Copyright (C) 2002, 2003, 2005, 2008  Maciej W. Rozycki
118c2ecf20Sopenharmony_ci *
128c2ecf20Sopenharmony_ci *	WARNING!  All this information is pure guesswork based on the
138c2ecf20Sopenharmony_ci *	ROM.  It is provided here in hope it will give someone some
148c2ecf20Sopenharmony_ci *	food for thought.  No documentation for the KN05 nor the KN04
158c2ecf20Sopenharmony_ci *	module has been located so far.
168c2ecf20Sopenharmony_ci */
178c2ecf20Sopenharmony_ci#ifndef __ASM_MIPS_DEC_KN05_H
188c2ecf20Sopenharmony_ci#define __ASM_MIPS_DEC_KN05_H
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci#include <asm/dec/ioasic_addrs.h>
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ci/*
238c2ecf20Sopenharmony_ci * The oncard MB (Memory Buffer) ASIC provides an additional address
248c2ecf20Sopenharmony_ci * decoder.  Certain address ranges within the "high" 16 slots are
258c2ecf20Sopenharmony_ci * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
268c2ecf20Sopenharmony_ci * Others are handled locally.  "Low" slots are always passed.
278c2ecf20Sopenharmony_ci */
288c2ecf20Sopenharmony_ci#define KN4K_SLOT_BASE	0x1fc00000
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci#define KN4K_MB_ROM	(0*IOASIC_SLOT_SIZE)	/* KN05/KN04 card ROM */
318c2ecf20Sopenharmony_ci#define KN4K_IOCTL	(1*IOASIC_SLOT_SIZE)	/* I/O ASIC */
328c2ecf20Sopenharmony_ci#define KN4K_ESAR	(2*IOASIC_SLOT_SIZE)	/* LANCE MAC address chip */
338c2ecf20Sopenharmony_ci#define KN4K_LANCE	(3*IOASIC_SLOT_SIZE)	/* LANCE Ethernet */
348c2ecf20Sopenharmony_ci#define KN4K_MB_INT	(4*IOASIC_SLOT_SIZE)	/* MB interrupt register */
358c2ecf20Sopenharmony_ci#define KN4K_MB_EA	(5*IOASIC_SLOT_SIZE)	/* MB error address? */
368c2ecf20Sopenharmony_ci#define KN4K_MB_EC	(6*IOASIC_SLOT_SIZE)	/* MB error ??? */
378c2ecf20Sopenharmony_ci#define KN4K_MB_CSR	(7*IOASIC_SLOT_SIZE)	/* MB control & status */
388c2ecf20Sopenharmony_ci#define KN4K_RES_08	(8*IOASIC_SLOT_SIZE)	/* unused? */
398c2ecf20Sopenharmony_ci#define KN4K_RES_09	(9*IOASIC_SLOT_SIZE)	/* unused? */
408c2ecf20Sopenharmony_ci#define KN4K_RES_10	(10*IOASIC_SLOT_SIZE)	/* unused? */
418c2ecf20Sopenharmony_ci#define KN4K_RES_11	(11*IOASIC_SLOT_SIZE)	/* unused? */
428c2ecf20Sopenharmony_ci#define KN4K_SCSI	(12*IOASIC_SLOT_SIZE)	/* ASC SCSI */
438c2ecf20Sopenharmony_ci#define KN4K_RES_13	(13*IOASIC_SLOT_SIZE)	/* unused? */
448c2ecf20Sopenharmony_ci#define KN4K_RES_14	(14*IOASIC_SLOT_SIZE)	/* unused? */
458c2ecf20Sopenharmony_ci#define KN4K_RES_15	(15*IOASIC_SLOT_SIZE)	/* unused? */
468c2ecf20Sopenharmony_ci
478c2ecf20Sopenharmony_ci/*
488c2ecf20Sopenharmony_ci * MB ASIC interrupt bits.
498c2ecf20Sopenharmony_ci */
508c2ecf20Sopenharmony_ci#define KN4K_MB_INR_MB		4	/* ??? */
518c2ecf20Sopenharmony_ci#define KN4K_MB_INR_MT		3	/* memory, I/O bus read/write errors */
528c2ecf20Sopenharmony_ci#define KN4K_MB_INR_RES_2	2	/* unused */
538c2ecf20Sopenharmony_ci#define KN4K_MB_INR_RTC		1	/* RTC */
548c2ecf20Sopenharmony_ci#define KN4K_MB_INR_TC		0	/* I/O ASIC cascade */
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci/*
578c2ecf20Sopenharmony_ci * Bits for the MB interrupt register.
588c2ecf20Sopenharmony_ci * The register appears read-only.
598c2ecf20Sopenharmony_ci */
608c2ecf20Sopenharmony_ci#define KN4K_MB_INT_IRQ		(0x1f<<0)	/* CPU Int[4:0] status. */
618c2ecf20Sopenharmony_ci#define KN4K_MB_INT_IRQ_N(n)	(1<<(n))	/* Individual status bits. */
628c2ecf20Sopenharmony_ci
638c2ecf20Sopenharmony_ci/*
648c2ecf20Sopenharmony_ci * Bits for the MB control & status register.
658c2ecf20Sopenharmony_ci * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
668c2ecf20Sopenharmony_ci */
678c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_PF		(1<<0)		/* PreFetching enable? */
688c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_F		(1<<1)		/* ??? */
698c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_ECC		(0xff<<2)	/* ??? */
708c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_OD		(1<<10)		/* ??? */
718c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_CP		(1<<11)		/* ??? */
728c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_UNC		(1<<12)		/* ??? */
738c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_IM		(1<<13)		/* ??? */
748c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_NC		(1<<14)		/* ??? */
758c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_EE		(1<<15)		/* (bus) Exception Enable? */
768c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_MSK		(0x1f<<16)	/* CPU Int[4:0] mask */
778c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_MSK_N(n)	(1<<((n)+16))	/* Individual mask bits. */
788c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_FW		(1<<21)		/* ??? */
798c2ecf20Sopenharmony_ci#define KN4K_MB_CSR_W		(1<<31)		/* ??? */
808c2ecf20Sopenharmony_ci
818c2ecf20Sopenharmony_ci#endif /* __ASM_MIPS_DEC_KN05_H */
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