1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9#ifndef __ASM_CPU_FEATURES_H 10#define __ASM_CPU_FEATURES_H 11 12#include <asm/cpu.h> 13#include <asm/cpu-info.h> 14#include <asm/isa-rev.h> 15#include <cpu-feature-overrides.h> 16 17#define __ase(ase) (cpu_data[0].ases & (ase)) 18#define __isa(isa) (cpu_data[0].isa_level & (isa)) 19#define __opt(opt) (cpu_data[0].options & (opt)) 20 21/* 22 * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during 23 * boot (typically by cpu_probe()). 24 * 25 * Note that these should only be used in cases where a kernel built for an 26 * older ISA *cannot* run on a CPU which supports the feature in question. For 27 * example this may be used for features introduced with MIPSr6, since a kernel 28 * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used 29 * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a 30 * MIPSr2 CPU. 31 */ 32#define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) 33#define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt)) 34 35/* 36 * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during 37 * boot (typically by cpu_probe()). 38 * 39 * These are for use with features that are optional up until a particular ISA 40 * revision & then become required. 41 */ 42#define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) 43#define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt)) 44 45/* 46 * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during 47 * boot (typically by cpu_probe()). 48 * 49 * These are for use with features that are optional up until a particular ISA 50 * revision & are then removed - ie. no longer present in any CPU implementing 51 * the given ISA revision. 52 */ 53#define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) 54#define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt)) 55 56/* 57 * Similarly allow for ISA level checks that take into account knowledge of the 58 * ISA targeted by the kernel build, provided by MIPS_ISA_REV. 59 */ 60#define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag)) 61#define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag)) 62#define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag)) 63#define __isa_range(ge, lt) \ 64 ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) 65#define __isa_range_or_flag(ge, lt, flag) \ 66 (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) 67#define __isa_range_and_ase(ge, lt, ase) \ 68 (__isa_range(ge, lt) && __ase(ase)) 69 70/* 71 * SMP assumption: Options of CPU 0 are a superset of all processors. 72 * This is true for all known MIPS systems. 73 */ 74#ifndef cpu_has_tlb 75#define cpu_has_tlb __opt(MIPS_CPU_TLB) 76#endif 77#ifndef cpu_has_ftlb 78#define cpu_has_ftlb __opt(MIPS_CPU_FTLB) 79#endif 80#ifndef cpu_has_tlbinv 81#define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV) 82#endif 83#ifndef cpu_has_segments 84#define cpu_has_segments __opt(MIPS_CPU_SEGMENTS) 85#endif 86#ifndef cpu_has_eva 87#define cpu_has_eva __opt(MIPS_CPU_EVA) 88#endif 89#ifndef cpu_has_htw 90#define cpu_has_htw __opt(MIPS_CPU_HTW) 91#endif 92#ifndef cpu_has_ldpte 93#define cpu_has_ldpte __opt(MIPS_CPU_LDPTE) 94#endif 95#ifndef cpu_has_rixiex 96#define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX) 97#endif 98#ifndef cpu_has_maar 99#define cpu_has_maar __opt(MIPS_CPU_MAAR) 100#endif 101#ifndef cpu_has_rw_llb 102#define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB) 103#endif 104 105/* 106 * For the moment we don't consider R6000 and R8000 so we can assume that 107 * anything that doesn't support R4000-style exceptions and interrupts is 108 * R3000-like. Users should still treat these two macro definitions as 109 * opaque. 110 */ 111#ifndef cpu_has_3kex 112#define cpu_has_3kex (!cpu_has_4kex) 113#endif 114#ifndef cpu_has_4kex 115#define cpu_has_4kex __isa_ge_or_opt(1, MIPS_CPU_4KEX) 116#endif 117#ifndef cpu_has_3k_cache 118#define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) 119#endif 120#define cpu_has_6k_cache 0 121#define cpu_has_8k_cache 0 122#ifndef cpu_has_4k_cache 123#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) 124#endif 125#ifndef cpu_has_tx39_cache 126#define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE) 127#endif 128#ifndef cpu_has_octeon_cache 129#define cpu_has_octeon_cache \ 130({ \ 131 int __res; \ 132 \ 133 switch (boot_cpu_type()) { \ 134 case CPU_CAVIUM_OCTEON: \ 135 case CPU_CAVIUM_OCTEON_PLUS: \ 136 case CPU_CAVIUM_OCTEON2: \ 137 case CPU_CAVIUM_OCTEON3: \ 138 __res = 1; \ 139 break; \ 140 \ 141 default: \ 142 __res = 0; \ 143 } \ 144 \ 145 __res; \ 146}) 147#endif 148/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 149#ifndef cpu_has_fpu 150# ifdef CONFIG_MIPS_FP_SUPPORT 151# define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 152# define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 153# else 154# define cpu_has_fpu 0 155# define raw_cpu_has_fpu 0 156# endif 157#else 158# define raw_cpu_has_fpu cpu_has_fpu 159#endif 160#ifndef cpu_has_32fpr 161#define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR) 162#endif 163#ifndef cpu_has_counter 164#define cpu_has_counter __opt(MIPS_CPU_COUNTER) 165#endif 166#ifndef cpu_has_watch 167#define cpu_has_watch __opt(MIPS_CPU_WATCH) 168#endif 169#ifndef cpu_has_divec 170#define cpu_has_divec __isa_ge_or_opt(1, MIPS_CPU_DIVEC) 171#endif 172#ifndef cpu_has_vce 173#define cpu_has_vce __opt(MIPS_CPU_VCE) 174#endif 175#ifndef cpu_has_cache_cdex_p 176#define cpu_has_cache_cdex_p __opt(MIPS_CPU_CACHE_CDEX_P) 177#endif 178#ifndef cpu_has_cache_cdex_s 179#define cpu_has_cache_cdex_s __opt(MIPS_CPU_CACHE_CDEX_S) 180#endif 181#ifndef cpu_has_prefetch 182#define cpu_has_prefetch __isa_ge_or_opt(1, MIPS_CPU_PREFETCH) 183#endif 184#ifndef cpu_has_mcheck 185#define cpu_has_mcheck __isa_ge_or_opt(1, MIPS_CPU_MCHECK) 186#endif 187#ifndef cpu_has_ejtag 188#define cpu_has_ejtag __opt(MIPS_CPU_EJTAG) 189#endif 190#ifndef cpu_has_llsc 191#define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC) 192#endif 193#ifndef kernel_uses_llsc 194#define kernel_uses_llsc cpu_has_llsc 195#endif 196#ifndef cpu_has_guestctl0ext 197#define cpu_has_guestctl0ext __opt(MIPS_CPU_GUESTCTL0EXT) 198#endif 199#ifndef cpu_has_guestctl1 200#define cpu_has_guestctl1 __opt(MIPS_CPU_GUESTCTL1) 201#endif 202#ifndef cpu_has_guestctl2 203#define cpu_has_guestctl2 __opt(MIPS_CPU_GUESTCTL2) 204#endif 205#ifndef cpu_has_guestid 206#define cpu_has_guestid __opt(MIPS_CPU_GUESTID) 207#endif 208#ifndef cpu_has_drg 209#define cpu_has_drg __opt(MIPS_CPU_DRG) 210#endif 211#ifndef cpu_has_mips16 212#define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16) 213#endif 214#ifndef cpu_has_mips16e2 215#define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2) 216#endif 217#ifndef cpu_has_mdmx 218#define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX) 219#endif 220#ifndef cpu_has_mips3d 221#define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D) 222#endif 223#ifndef cpu_has_smartmips 224#define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS) 225#endif 226 227#ifndef cpu_has_rixi 228#define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI) 229#endif 230 231#ifndef cpu_has_mmips 232# if defined(__mips_micromips) 233# define cpu_has_mmips 1 234# elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 235# define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS) 236# else 237# define cpu_has_mmips 0 238# endif 239#endif 240 241#ifndef cpu_has_lpa 242#define cpu_has_lpa __opt(MIPS_CPU_LPA) 243#endif 244#ifndef cpu_has_mvh 245#define cpu_has_mvh __opt(MIPS_CPU_MVH) 246#endif 247#ifndef cpu_has_xpa 248#define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 249#endif 250#ifndef cpu_has_vtag_icache 251#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 252#endif 253#ifndef cpu_has_dc_aliases 254#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 255#endif 256#ifndef cpu_has_ic_fills_f_dc 257#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 258#endif 259#ifndef cpu_has_pindexed_dcache 260#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 261#endif 262 263/* 264 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 265 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 266 * don't. For maintaining I-cache coherency this means we need to flush the 267 * D-cache all the way back to whever the I-cache does refills from, so the 268 * I-cache has a chance to see the new data at all. Then we have to flush the 269 * I-cache also. 270 * Note we may have been rescheduled and may no longer be running on the CPU 271 * that did the store so we can't optimize this into only doing the flush on 272 * the local CPU. 273 */ 274#ifndef cpu_icache_snoops_remote_store 275#ifdef CONFIG_SMP 276#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 277#else 278#define cpu_icache_snoops_remote_store 1 279#endif 280#endif 281 282#ifndef cpu_has_mips_1 283# define cpu_has_mips_1 (MIPS_ISA_REV < 6) 284#endif 285#ifndef cpu_has_mips_2 286# define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II) 287#endif 288#ifndef cpu_has_mips_3 289# define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III) 290#endif 291#ifndef cpu_has_mips_4 292# define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV) 293#endif 294#ifndef cpu_has_mips_5 295# define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V) 296#endif 297#ifndef cpu_has_mips32r1 298# define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1) 299#endif 300#ifndef cpu_has_mips32r2 301# define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2) 302#endif 303#ifndef cpu_has_mips32r5 304# define cpu_has_mips32r5 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5) 305#endif 306#ifndef cpu_has_mips32r6 307# define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6) 308#endif 309#ifndef cpu_has_mips64r1 310# define cpu_has_mips64r1 (cpu_has_64bits && \ 311 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)) 312#endif 313#ifndef cpu_has_mips64r2 314# define cpu_has_mips64r2 (cpu_has_64bits && \ 315 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)) 316#endif 317#ifndef cpu_has_mips64r5 318# define cpu_has_mips64r5 (cpu_has_64bits && \ 319 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5)) 320#endif 321#ifndef cpu_has_mips64r6 322# define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6) 323#endif 324 325/* 326 * Shortcuts ... 327 */ 328#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 329#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 330#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 331 332#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 333#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 334#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 335#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 336 337#define cpu_has_mips_3_4_5_64_r2_r6 \ 338 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 339#define cpu_has_mips_4_5_64_r2_r6 \ 340 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 341 cpu_has_mips_r2 | cpu_has_mips_r5 | \ 342 cpu_has_mips_r6) 343 344#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 345 cpu_has_mips32r5 | cpu_has_mips32r6) 346#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | \ 347 cpu_has_mips64r5 | cpu_has_mips64r6) 348#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 349#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 350#define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5) 351#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 352#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 353 cpu_has_mips32r5 | cpu_has_mips32r6 | \ 354 cpu_has_mips64r1 | cpu_has_mips64r2 | \ 355 cpu_has_mips64r5 | cpu_has_mips64r6) 356 357/* MIPSR2 - MIPSR6 have a lot of similarities */ 358#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r5 | \ 359 cpu_has_mips_r6) 360 361/* 362 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 363 * 364 * Returns non-zero value if the current processor implementation requires 365 * an IHB instruction to deal with an instruction hazard as per MIPS R2 366 * architecture specification, zero otherwise. 367 */ 368#ifndef cpu_has_mips_r2_exec_hazard 369#define cpu_has_mips_r2_exec_hazard \ 370({ \ 371 int __res; \ 372 \ 373 switch (boot_cpu_type()) { \ 374 case CPU_M14KC: \ 375 case CPU_74K: \ 376 case CPU_1074K: \ 377 case CPU_PROAPTIV: \ 378 case CPU_P5600: \ 379 case CPU_M5150: \ 380 case CPU_QEMU_GENERIC: \ 381 case CPU_CAVIUM_OCTEON: \ 382 case CPU_CAVIUM_OCTEON_PLUS: \ 383 case CPU_CAVIUM_OCTEON2: \ 384 case CPU_CAVIUM_OCTEON3: \ 385 __res = 0; \ 386 break; \ 387 \ 388 default: \ 389 __res = 1; \ 390 } \ 391 \ 392 __res; \ 393}) 394#endif 395 396/* 397 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 398 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 399 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 400 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 401 */ 402#ifndef cpu_has_clo_clz 403#define cpu_has_clo_clz cpu_has_mips_r 404#endif 405 406/* 407 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 408 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 409 * This indicates the availability of WSBH and in case of 64 bit CPUs also 410 * DSBH and DSHD. 411 */ 412#ifndef cpu_has_wsbh 413#define cpu_has_wsbh cpu_has_mips_r2 414#endif 415 416#ifndef cpu_has_dsp 417#define cpu_has_dsp __ase(MIPS_ASE_DSP) 418#endif 419 420#ifndef cpu_has_dsp2 421#define cpu_has_dsp2 __ase(MIPS_ASE_DSP2P) 422#endif 423 424#ifndef cpu_has_dsp3 425#define cpu_has_dsp3 __ase(MIPS_ASE_DSP3) 426#endif 427 428#ifndef cpu_has_loongson_mmi 429#define cpu_has_loongson_mmi __ase(MIPS_ASE_LOONGSON_MMI) 430#endif 431 432#ifndef cpu_has_loongson_cam 433#define cpu_has_loongson_cam __ase(MIPS_ASE_LOONGSON_CAM) 434#endif 435 436#ifndef cpu_has_loongson_ext 437#define cpu_has_loongson_ext __ase(MIPS_ASE_LOONGSON_EXT) 438#endif 439 440#ifndef cpu_has_loongson_ext2 441#define cpu_has_loongson_ext2 __ase(MIPS_ASE_LOONGSON_EXT2) 442#endif 443 444#ifndef cpu_has_mipsmt 445#define cpu_has_mipsmt __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT) 446#endif 447 448#ifndef cpu_has_vp 449#define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP) 450#endif 451 452#ifndef cpu_has_userlocal 453#define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI) 454#endif 455 456#ifdef CONFIG_32BIT 457# ifndef cpu_has_nofpuex 458# define cpu_has_nofpuex __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX) 459# endif 460# ifndef cpu_has_64bits 461# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 462# endif 463# ifndef cpu_has_64bit_zero_reg 464# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 465# endif 466# ifndef cpu_has_64bit_gp_regs 467# define cpu_has_64bit_gp_regs 0 468# endif 469# ifndef cpu_vmbits 470# define cpu_vmbits 31 471# endif 472#endif 473 474#ifdef CONFIG_64BIT 475# ifndef cpu_has_nofpuex 476# define cpu_has_nofpuex 0 477# endif 478# ifndef cpu_has_64bits 479# define cpu_has_64bits 1 480# endif 481# ifndef cpu_has_64bit_zero_reg 482# define cpu_has_64bit_zero_reg 1 483# endif 484# ifndef cpu_has_64bit_gp_regs 485# define cpu_has_64bit_gp_regs 1 486# endif 487# ifndef cpu_vmbits 488# define cpu_vmbits cpu_data[0].vmbits 489# define __NEED_VMBITS_PROBE 490# endif 491#endif 492 493#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 494# define cpu_has_vint __opt(MIPS_CPU_VINT) 495#elif !defined(cpu_has_vint) 496# define cpu_has_vint 0 497#endif 498 499#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 500# define cpu_has_veic __opt(MIPS_CPU_VEIC) 501#elif !defined(cpu_has_veic) 502# define cpu_has_veic 0 503#endif 504 505#ifndef cpu_has_inclusive_pcaches 506#define cpu_has_inclusive_pcaches __opt(MIPS_CPU_INCLUSIVE_CACHES) 507#endif 508 509#ifndef cpu_dcache_line_size 510#define cpu_dcache_line_size() cpu_data[0].dcache.linesz 511#endif 512#ifndef cpu_icache_line_size 513#define cpu_icache_line_size() cpu_data[0].icache.linesz 514#endif 515#ifndef cpu_scache_line_size 516#define cpu_scache_line_size() cpu_data[0].scache.linesz 517#endif 518#ifndef cpu_tcache_line_size 519#define cpu_tcache_line_size() cpu_data[0].tcache.linesz 520#endif 521 522#ifndef cpu_hwrena_impl_bits 523#define cpu_hwrena_impl_bits 0 524#endif 525 526#ifndef cpu_has_perf_cntr_intr_bit 527#define cpu_has_perf_cntr_intr_bit __opt(MIPS_CPU_PCI) 528#endif 529 530#ifndef cpu_has_vz 531#define cpu_has_vz __ase(MIPS_ASE_VZ) 532#endif 533 534#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 535# define cpu_has_msa __ase(MIPS_ASE_MSA) 536#elif !defined(cpu_has_msa) 537# define cpu_has_msa 0 538#endif 539 540#ifndef cpu_has_ufr 541# define cpu_has_ufr __opt(MIPS_CPU_UFR) 542#endif 543 544#ifndef cpu_has_fre 545# define cpu_has_fre __opt(MIPS_CPU_FRE) 546#endif 547 548#ifndef cpu_has_cdmm 549# define cpu_has_cdmm __opt(MIPS_CPU_CDMM) 550#endif 551 552#ifndef cpu_has_small_pages 553# define cpu_has_small_pages __opt(MIPS_CPU_SP) 554#endif 555 556#ifndef cpu_has_nan_legacy 557#define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY) 558#endif 559#ifndef cpu_has_nan_2008 560#define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008) 561#endif 562 563#ifndef cpu_has_ebase_wg 564# define cpu_has_ebase_wg __opt(MIPS_CPU_EBASE_WG) 565#endif 566 567#ifndef cpu_has_badinstr 568# define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR) 569#endif 570 571#ifndef cpu_has_badinstrp 572# define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP) 573#endif 574 575#ifndef cpu_has_contextconfig 576# define cpu_has_contextconfig __opt(MIPS_CPU_CTXTC) 577#endif 578 579#ifndef cpu_has_perf 580# define cpu_has_perf __opt(MIPS_CPU_PERF) 581#endif 582 583#ifndef cpu_has_mac2008_only 584# define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY) 585#endif 586 587#ifndef cpu_has_ftlbparex 588# define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX) 589#endif 590 591#ifndef cpu_has_gsexcex 592# define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX) 593#endif 594 595#ifdef CONFIG_SMP 596/* 597 * Some systems share FTLB RAMs between threads within a core (siblings in 598 * kernel parlance). This means that FTLB entries may become invalid at almost 599 * any point when an entry is evicted due to a sibling thread writing an entry 600 * to the shared FTLB RAM. 601 * 602 * This is only relevant to SMP systems, and the only systems that exhibit this 603 * property implement MIPSr6 or higher so we constrain support for this to 604 * kernels that will run on such systems. 605 */ 606# ifndef cpu_has_shared_ftlb_ram 607# define cpu_has_shared_ftlb_ram \ 608 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM) 609# endif 610 611/* 612 * Some systems take this a step further & share FTLB entries between siblings. 613 * This is implemented as TLB writes happening as usual, but if an entry 614 * written by a sibling exists in the shared FTLB for a translation which would 615 * otherwise cause a TLB refill exception then the CPU will use the entry 616 * written by its sibling rather than triggering a refill & writing a matching 617 * TLB entry for itself. 618 * 619 * This is naturally only valid if a TLB entry is known to be suitable for use 620 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use 621 * rather than ASIDs or when a TLB entry is marked global. 622 */ 623# ifndef cpu_has_shared_ftlb_entries 624# define cpu_has_shared_ftlb_entries \ 625 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES) 626# endif 627#endif /* SMP */ 628 629#ifndef cpu_has_shared_ftlb_ram 630# define cpu_has_shared_ftlb_ram 0 631#endif 632#ifndef cpu_has_shared_ftlb_entries 633# define cpu_has_shared_ftlb_entries 0 634#endif 635 636#ifdef CONFIG_MIPS_MT_SMP 637# define cpu_has_mipsmt_pertccounters \ 638 __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS) 639#else 640# define cpu_has_mipsmt_pertccounters 0 641#endif /* CONFIG_MIPS_MT_SMP */ 642 643/* 644 * We only enable MMID support for configurations which natively support 64 bit 645 * atomics because getting good performance from the allocator relies upon 646 * efficient atomic64_*() functions. 647 */ 648#ifndef cpu_has_mmid 649# ifdef CONFIG_GENERIC_ATOMIC64 650# define cpu_has_mmid 0 651# else 652# define cpu_has_mmid __isa_ge_and_opt(6, MIPS_CPU_MMID) 653# endif 654#endif 655 656#ifndef cpu_has_mm_sysad 657# define cpu_has_mm_sysad __opt(MIPS_CPU_MM_SYSAD) 658#endif 659 660#ifndef cpu_has_mm_full 661# define cpu_has_mm_full __opt(MIPS_CPU_MM_FULL) 662#endif 663 664/* 665 * Guest capabilities 666 */ 667#ifndef cpu_guest_has_conf1 668#define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 669#endif 670#ifndef cpu_guest_has_conf2 671#define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 672#endif 673#ifndef cpu_guest_has_conf3 674#define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 675#endif 676#ifndef cpu_guest_has_conf4 677#define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 678#endif 679#ifndef cpu_guest_has_conf5 680#define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 681#endif 682#ifndef cpu_guest_has_conf6 683#define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 684#endif 685#ifndef cpu_guest_has_conf7 686#define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 687#endif 688#ifndef cpu_guest_has_fpu 689#define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 690#endif 691#ifndef cpu_guest_has_watch 692#define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 693#endif 694#ifndef cpu_guest_has_contextconfig 695#define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 696#endif 697#ifndef cpu_guest_has_segments 698#define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 699#endif 700#ifndef cpu_guest_has_badinstr 701#define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 702#endif 703#ifndef cpu_guest_has_badinstrp 704#define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 705#endif 706#ifndef cpu_guest_has_htw 707#define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 708#endif 709#ifndef cpu_guest_has_ldpte 710#define cpu_guest_has_ldpte (cpu_data[0].guest.options & MIPS_CPU_LDPTE) 711#endif 712#ifndef cpu_guest_has_mvh 713#define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH) 714#endif 715#ifndef cpu_guest_has_msa 716#define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 717#endif 718#ifndef cpu_guest_has_kscr 719#define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 720#endif 721#ifndef cpu_guest_has_rw_llb 722#define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 723#endif 724#ifndef cpu_guest_has_perf 725#define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 726#endif 727#ifndef cpu_guest_has_maar 728#define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 729#endif 730#ifndef cpu_guest_has_userlocal 731#define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI) 732#endif 733 734/* 735 * Guest dynamic capabilities 736 */ 737#ifndef cpu_guest_has_dyn_fpu 738#define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 739#endif 740#ifndef cpu_guest_has_dyn_watch 741#define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 742#endif 743#ifndef cpu_guest_has_dyn_contextconfig 744#define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 745#endif 746#ifndef cpu_guest_has_dyn_perf 747#define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 748#endif 749#ifndef cpu_guest_has_dyn_msa 750#define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 751#endif 752#ifndef cpu_guest_has_dyn_maar 753#define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 754#endif 755 756#endif /* __ASM_CPU_FEATURES_H */ 757