1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2016 Cavium, Inc. 7 */ 8 9#include <linux/of_address.h> 10#include <linux/interrupt.h> 11#include <linux/irqdomain.h> 12#include <linux/bitops.h> 13#include <linux/of_irq.h> 14#include <linux/percpu.h> 15#include <linux/slab.h> 16#include <linux/irq.h> 17#include <linux/smp.h> 18#include <linux/of.h> 19 20#include <asm/octeon/octeon.h> 21#include <asm/octeon/cvmx-ciu2-defs.h> 22#include <asm/octeon/cvmx-ciu3-defs.h> 23 24static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror); 25static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror); 26static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock); 27static DEFINE_PER_CPU(unsigned int, octeon_irq_ciu3_idt_ip2); 28 29static DEFINE_PER_CPU(unsigned int, octeon_irq_ciu3_idt_ip3); 30static DEFINE_PER_CPU(struct octeon_ciu3_info *, octeon_ciu3_info); 31#define CIU3_MBOX_PER_CORE 10 32 33/* 34 * The 8 most significant bits of the intsn identify the interrupt major block. 35 * Each major block might use its own interrupt domain. Thus 256 domains are 36 * needed. 37 */ 38#define MAX_CIU3_DOMAINS 256 39 40typedef irq_hw_number_t (*octeon_ciu3_intsn2hw_t)(struct irq_domain *, unsigned int); 41 42/* Information for each ciu3 in the system */ 43struct octeon_ciu3_info { 44 u64 ciu3_addr; 45 int node; 46 struct irq_domain *domain[MAX_CIU3_DOMAINS]; 47 octeon_ciu3_intsn2hw_t intsn2hw[MAX_CIU3_DOMAINS]; 48}; 49 50/* Each ciu3 in the system uses its own data (one ciu3 per node) */ 51static struct octeon_ciu3_info *octeon_ciu3_info_per_node[4]; 52 53struct octeon_irq_ciu_domain_data { 54 int num_sum; /* number of sum registers (2 or 3). */ 55}; 56 57/* Register offsets from ciu3_addr */ 58#define CIU3_CONST 0x220 59#define CIU3_IDT_CTL(_idt) ((_idt) * 8 + 0x110000) 60#define CIU3_IDT_PP(_idt, _idx) ((_idt) * 32 + (_idx) * 8 + 0x120000) 61#define CIU3_IDT_IO(_idt) ((_idt) * 8 + 0x130000) 62#define CIU3_DEST_PP_INT(_pp_ip) ((_pp_ip) * 8 + 0x200000) 63#define CIU3_DEST_IO_INT(_io) ((_io) * 8 + 0x210000) 64#define CIU3_ISC_CTL(_intsn) ((_intsn) * 8 + 0x80000000) 65#define CIU3_ISC_W1C(_intsn) ((_intsn) * 8 + 0x90000000) 66#define CIU3_ISC_W1S(_intsn) ((_intsn) * 8 + 0xa0000000) 67 68static __read_mostly int octeon_irq_ciu_to_irq[8][64]; 69 70struct octeon_ciu_chip_data { 71 union { 72 struct { /* only used for ciu3 */ 73 u64 ciu3_addr; 74 unsigned int intsn; 75 }; 76 struct { /* only used for ciu/ciu2 */ 77 u8 line; 78 u8 bit; 79 }; 80 }; 81 int gpio_line; 82 int current_cpu; /* Next CPU expected to take this irq */ 83 int ciu_node; /* NUMA node number of the CIU */ 84}; 85 86struct octeon_core_chip_data { 87 struct mutex core_irq_mutex; 88 bool current_en; 89 bool desired_en; 90 u8 bit; 91}; 92 93#define MIPS_CORE_IRQ_LINES 8 94 95static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; 96 97static int octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line, 98 struct irq_chip *chip, 99 irq_flow_handler_t handler) 100{ 101 struct octeon_ciu_chip_data *cd; 102 103 cd = kzalloc(sizeof(*cd), GFP_KERNEL); 104 if (!cd) 105 return -ENOMEM; 106 107 irq_set_chip_and_handler(irq, chip, handler); 108 109 cd->line = line; 110 cd->bit = bit; 111 cd->gpio_line = gpio_line; 112 113 irq_set_chip_data(irq, cd); 114 octeon_irq_ciu_to_irq[line][bit] = irq; 115 return 0; 116} 117 118static void octeon_irq_free_cd(struct irq_domain *d, unsigned int irq) 119{ 120 struct irq_data *data = irq_get_irq_data(irq); 121 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data); 122 123 irq_set_chip_data(irq, NULL); 124 kfree(cd); 125} 126 127static int octeon_irq_force_ciu_mapping(struct irq_domain *domain, 128 int irq, int line, int bit) 129{ 130 struct device_node *of_node; 131 int ret; 132 133 of_node = irq_domain_get_of_node(domain); 134 if (!of_node) 135 return -EINVAL; 136 ret = irq_alloc_desc_at(irq, of_node_to_nid(of_node)); 137 if (ret < 0) 138 return ret; 139 140 return irq_domain_associate(domain, irq, line << 6 | bit); 141} 142 143static int octeon_coreid_for_cpu(int cpu) 144{ 145#ifdef CONFIG_SMP 146 return cpu_logical_map(cpu); 147#else 148 return cvmx_get_core_num(); 149#endif 150} 151 152static int octeon_cpu_for_coreid(int coreid) 153{ 154#ifdef CONFIG_SMP 155 return cpu_number_map(coreid); 156#else 157 return smp_processor_id(); 158#endif 159} 160 161static void octeon_irq_core_ack(struct irq_data *data) 162{ 163 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); 164 unsigned int bit = cd->bit; 165 166 /* 167 * We don't need to disable IRQs to make these atomic since 168 * they are already disabled earlier in the low level 169 * interrupt code. 170 */ 171 clear_c0_status(0x100 << bit); 172 /* The two user interrupts must be cleared manually. */ 173 if (bit < 2) 174 clear_c0_cause(0x100 << bit); 175} 176 177static void octeon_irq_core_eoi(struct irq_data *data) 178{ 179 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); 180 181 /* 182 * We don't need to disable IRQs to make these atomic since 183 * they are already disabled earlier in the low level 184 * interrupt code. 185 */ 186 set_c0_status(0x100 << cd->bit); 187} 188 189static void octeon_irq_core_set_enable_local(void *arg) 190{ 191 struct irq_data *data = arg; 192 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); 193 unsigned int mask = 0x100 << cd->bit; 194 195 /* 196 * Interrupts are already disabled, so these are atomic. 197 */ 198 if (cd->desired_en) 199 set_c0_status(mask); 200 else 201 clear_c0_status(mask); 202 203} 204 205static void octeon_irq_core_disable(struct irq_data *data) 206{ 207 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); 208 cd->desired_en = false; 209} 210 211static void octeon_irq_core_enable(struct irq_data *data) 212{ 213 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); 214 cd->desired_en = true; 215} 216 217static void octeon_irq_core_bus_lock(struct irq_data *data) 218{ 219 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); 220 221 mutex_lock(&cd->core_irq_mutex); 222} 223 224static void octeon_irq_core_bus_sync_unlock(struct irq_data *data) 225{ 226 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); 227 228 if (cd->desired_en != cd->current_en) { 229 on_each_cpu(octeon_irq_core_set_enable_local, data, 1); 230 231 cd->current_en = cd->desired_en; 232 } 233 234 mutex_unlock(&cd->core_irq_mutex); 235} 236 237static struct irq_chip octeon_irq_chip_core = { 238 .name = "Core", 239 .irq_enable = octeon_irq_core_enable, 240 .irq_disable = octeon_irq_core_disable, 241 .irq_ack = octeon_irq_core_ack, 242 .irq_eoi = octeon_irq_core_eoi, 243 .irq_bus_lock = octeon_irq_core_bus_lock, 244 .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock, 245 246 .irq_cpu_online = octeon_irq_core_eoi, 247 .irq_cpu_offline = octeon_irq_core_ack, 248 .flags = IRQCHIP_ONOFFLINE_ENABLED, 249}; 250 251static void __init octeon_irq_init_core(void) 252{ 253 int i; 254 int irq; 255 struct octeon_core_chip_data *cd; 256 257 for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) { 258 cd = &octeon_irq_core_chip_data[i]; 259 cd->current_en = false; 260 cd->desired_en = false; 261 cd->bit = i; 262 mutex_init(&cd->core_irq_mutex); 263 264 irq = OCTEON_IRQ_SW0 + i; 265 irq_set_chip_data(irq, cd); 266 irq_set_chip_and_handler(irq, &octeon_irq_chip_core, 267 handle_percpu_irq); 268 } 269} 270 271static int next_cpu_for_irq(struct irq_data *data) 272{ 273 274#ifdef CONFIG_SMP 275 int cpu; 276 struct cpumask *mask = irq_data_get_affinity_mask(data); 277 int weight = cpumask_weight(mask); 278 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data); 279 280 if (weight > 1) { 281 cpu = cd->current_cpu; 282 for (;;) { 283 cpu = cpumask_next(cpu, mask); 284 if (cpu >= nr_cpu_ids) { 285 cpu = -1; 286 continue; 287 } else if (cpumask_test_cpu(cpu, cpu_online_mask)) { 288 break; 289 } 290 } 291 } else if (weight == 1) { 292 cpu = cpumask_first(mask); 293 } else { 294 cpu = smp_processor_id(); 295 } 296 cd->current_cpu = cpu; 297 return cpu; 298#else 299 return smp_processor_id(); 300#endif 301} 302 303static void octeon_irq_ciu_enable(struct irq_data *data) 304{ 305 int cpu = next_cpu_for_irq(data); 306 int coreid = octeon_coreid_for_cpu(cpu); 307 unsigned long *pen; 308 unsigned long flags; 309 struct octeon_ciu_chip_data *cd; 310 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); 311 312 cd = irq_data_get_irq_chip_data(data); 313 314 raw_spin_lock_irqsave(lock, flags); 315 if (cd->line == 0) { 316 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); 317 __set_bit(cd->bit, pen); 318 /* 319 * Must be visible to octeon_irq_ip{2,3}_ciu() before 320 * enabling the irq. 321 */ 322 wmb(); 323 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); 324 } else { 325 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); 326 __set_bit(cd->bit, pen); 327 /* 328 * Must be visible to octeon_irq_ip{2,3}_ciu() before 329 * enabling the irq. 330 */ 331 wmb(); 332 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); 333 } 334 raw_spin_unlock_irqrestore(lock, flags); 335} 336 337static void octeon_irq_ciu_enable_local(struct irq_data *data) 338{ 339 unsigned long *pen; 340 unsigned long flags; 341 struct octeon_ciu_chip_data *cd; 342 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock); 343 344 cd = irq_data_get_irq_chip_data(data); 345 346 raw_spin_lock_irqsave(lock, flags); 347 if (cd->line == 0) { 348 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror); 349 __set_bit(cd->bit, pen); 350 /* 351 * Must be visible to octeon_irq_ip{2,3}_ciu() before 352 * enabling the irq. 353 */ 354 wmb(); 355 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); 356 } else { 357 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror); 358 __set_bit(cd->bit, pen); 359 /* 360 * Must be visible to octeon_irq_ip{2,3}_ciu() before 361 * enabling the irq. 362 */ 363 wmb(); 364 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); 365 } 366 raw_spin_unlock_irqrestore(lock, flags); 367} 368 369static void octeon_irq_ciu_disable_local(struct irq_data *data) 370{ 371 unsigned long *pen; 372 unsigned long flags; 373 struct octeon_ciu_chip_data *cd; 374 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock); 375 376 cd = irq_data_get_irq_chip_data(data); 377 378 raw_spin_lock_irqsave(lock, flags); 379 if (cd->line == 0) { 380 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror); 381 __clear_bit(cd->bit, pen); 382 /* 383 * Must be visible to octeon_irq_ip{2,3}_ciu() before 384 * enabling the irq. 385 */ 386 wmb(); 387 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); 388 } else { 389 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror); 390 __clear_bit(cd->bit, pen); 391 /* 392 * Must be visible to octeon_irq_ip{2,3}_ciu() before 393 * enabling the irq. 394 */ 395 wmb(); 396 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); 397 } 398 raw_spin_unlock_irqrestore(lock, flags); 399} 400 401static void octeon_irq_ciu_disable_all(struct irq_data *data) 402{ 403 unsigned long flags; 404 unsigned long *pen; 405 int cpu; 406 struct octeon_ciu_chip_data *cd; 407 raw_spinlock_t *lock; 408 409 cd = irq_data_get_irq_chip_data(data); 410 411 for_each_online_cpu(cpu) { 412 int coreid = octeon_coreid_for_cpu(cpu); 413 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); 414 if (cd->line == 0) 415 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); 416 else 417 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); 418 419 raw_spin_lock_irqsave(lock, flags); 420 __clear_bit(cd->bit, pen); 421 /* 422 * Must be visible to octeon_irq_ip{2,3}_ciu() before 423 * enabling the irq. 424 */ 425 wmb(); 426 if (cd->line == 0) 427 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); 428 else 429 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); 430 raw_spin_unlock_irqrestore(lock, flags); 431 } 432} 433 434static void octeon_irq_ciu_enable_all(struct irq_data *data) 435{ 436 unsigned long flags; 437 unsigned long *pen; 438 int cpu; 439 struct octeon_ciu_chip_data *cd; 440 raw_spinlock_t *lock; 441 442 cd = irq_data_get_irq_chip_data(data); 443 444 for_each_online_cpu(cpu) { 445 int coreid = octeon_coreid_for_cpu(cpu); 446 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); 447 if (cd->line == 0) 448 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); 449 else 450 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); 451 452 raw_spin_lock_irqsave(lock, flags); 453 __set_bit(cd->bit, pen); 454 /* 455 * Must be visible to octeon_irq_ip{2,3}_ciu() before 456 * enabling the irq. 457 */ 458 wmb(); 459 if (cd->line == 0) 460 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); 461 else 462 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); 463 raw_spin_unlock_irqrestore(lock, flags); 464 } 465} 466 467/* 468 * Enable the irq on the next core in the affinity set for chips that 469 * have the EN*_W1{S,C} registers. 470 */ 471static void octeon_irq_ciu_enable_v2(struct irq_data *data) 472{ 473 u64 mask; 474 int cpu = next_cpu_for_irq(data); 475 struct octeon_ciu_chip_data *cd; 476 477 cd = irq_data_get_irq_chip_data(data); 478 mask = 1ull << (cd->bit); 479 480 /* 481 * Called under the desc lock, so these should never get out 482 * of sync. 483 */ 484 if (cd->line == 0) { 485 int index = octeon_coreid_for_cpu(cpu) * 2; 486 set_bit(cd->bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); 487 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 488 } else { 489 int index = octeon_coreid_for_cpu(cpu) * 2 + 1; 490 set_bit(cd->bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); 491 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 492 } 493} 494 495/* 496 * Enable the irq in the sum2 registers. 497 */ 498static void octeon_irq_ciu_enable_sum2(struct irq_data *data) 499{ 500 u64 mask; 501 int cpu = next_cpu_for_irq(data); 502 int index = octeon_coreid_for_cpu(cpu); 503 struct octeon_ciu_chip_data *cd; 504 505 cd = irq_data_get_irq_chip_data(data); 506 mask = 1ull << (cd->bit); 507 508 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); 509} 510 511/* 512 * Disable the irq in the sum2 registers. 513 */ 514static void octeon_irq_ciu_disable_local_sum2(struct irq_data *data) 515{ 516 u64 mask; 517 int cpu = next_cpu_for_irq(data); 518 int index = octeon_coreid_for_cpu(cpu); 519 struct octeon_ciu_chip_data *cd; 520 521 cd = irq_data_get_irq_chip_data(data); 522 mask = 1ull << (cd->bit); 523 524 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); 525} 526 527static void octeon_irq_ciu_ack_sum2(struct irq_data *data) 528{ 529 u64 mask; 530 int cpu = next_cpu_for_irq(data); 531 int index = octeon_coreid_for_cpu(cpu); 532 struct octeon_ciu_chip_data *cd; 533 534 cd = irq_data_get_irq_chip_data(data); 535 mask = 1ull << (cd->bit); 536 537 cvmx_write_csr(CVMX_CIU_SUM2_PPX_IP4(index), mask); 538} 539 540static void octeon_irq_ciu_disable_all_sum2(struct irq_data *data) 541{ 542 int cpu; 543 struct octeon_ciu_chip_data *cd; 544 u64 mask; 545 546 cd = irq_data_get_irq_chip_data(data); 547 mask = 1ull << (cd->bit); 548 549 for_each_online_cpu(cpu) { 550 int coreid = octeon_coreid_for_cpu(cpu); 551 552 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(coreid), mask); 553 } 554} 555 556/* 557 * Enable the irq on the current CPU for chips that 558 * have the EN*_W1{S,C} registers. 559 */ 560static void octeon_irq_ciu_enable_local_v2(struct irq_data *data) 561{ 562 u64 mask; 563 struct octeon_ciu_chip_data *cd; 564 565 cd = irq_data_get_irq_chip_data(data); 566 mask = 1ull << (cd->bit); 567 568 if (cd->line == 0) { 569 int index = cvmx_get_core_num() * 2; 570 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror)); 571 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 572 } else { 573 int index = cvmx_get_core_num() * 2 + 1; 574 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror)); 575 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 576 } 577} 578 579static void octeon_irq_ciu_disable_local_v2(struct irq_data *data) 580{ 581 u64 mask; 582 struct octeon_ciu_chip_data *cd; 583 584 cd = irq_data_get_irq_chip_data(data); 585 mask = 1ull << (cd->bit); 586 587 if (cd->line == 0) { 588 int index = cvmx_get_core_num() * 2; 589 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror)); 590 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 591 } else { 592 int index = cvmx_get_core_num() * 2 + 1; 593 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror)); 594 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); 595 } 596} 597 598/* 599 * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq. 600 */ 601static void octeon_irq_ciu_ack(struct irq_data *data) 602{ 603 u64 mask; 604 struct octeon_ciu_chip_data *cd; 605 606 cd = irq_data_get_irq_chip_data(data); 607 mask = 1ull << (cd->bit); 608 609 if (cd->line == 0) { 610 int index = cvmx_get_core_num() * 2; 611 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); 612 } else { 613 cvmx_write_csr(CVMX_CIU_INT_SUM1, mask); 614 } 615} 616 617/* 618 * Disable the irq on the all cores for chips that have the EN*_W1{S,C} 619 * registers. 620 */ 621static void octeon_irq_ciu_disable_all_v2(struct irq_data *data) 622{ 623 int cpu; 624 u64 mask; 625 struct octeon_ciu_chip_data *cd; 626 627 cd = irq_data_get_irq_chip_data(data); 628 mask = 1ull << (cd->bit); 629 630 if (cd->line == 0) { 631 for_each_online_cpu(cpu) { 632 int index = octeon_coreid_for_cpu(cpu) * 2; 633 clear_bit(cd->bit, 634 &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); 635 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 636 } 637 } else { 638 for_each_online_cpu(cpu) { 639 int index = octeon_coreid_for_cpu(cpu) * 2 + 1; 640 clear_bit(cd->bit, 641 &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); 642 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); 643 } 644 } 645} 646 647/* 648 * Enable the irq on the all cores for chips that have the EN*_W1{S,C} 649 * registers. 650 */ 651static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) 652{ 653 int cpu; 654 u64 mask; 655 struct octeon_ciu_chip_data *cd; 656 657 cd = irq_data_get_irq_chip_data(data); 658 mask = 1ull << (cd->bit); 659 660 if (cd->line == 0) { 661 for_each_online_cpu(cpu) { 662 int index = octeon_coreid_for_cpu(cpu) * 2; 663 set_bit(cd->bit, 664 &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); 665 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 666 } 667 } else { 668 for_each_online_cpu(cpu) { 669 int index = octeon_coreid_for_cpu(cpu) * 2 + 1; 670 set_bit(cd->bit, 671 &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); 672 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 673 } 674 } 675} 676 677static int octeon_irq_ciu_set_type(struct irq_data *data, unsigned int t) 678{ 679 irqd_set_trigger_type(data, t); 680 681 if (t & IRQ_TYPE_EDGE_BOTH) 682 irq_set_handler_locked(data, handle_edge_irq); 683 else 684 irq_set_handler_locked(data, handle_level_irq); 685 686 return IRQ_SET_MASK_OK; 687} 688 689static void octeon_irq_gpio_setup(struct irq_data *data) 690{ 691 union cvmx_gpio_bit_cfgx cfg; 692 struct octeon_ciu_chip_data *cd; 693 u32 t = irqd_get_trigger_type(data); 694 695 cd = irq_data_get_irq_chip_data(data); 696 697 cfg.u64 = 0; 698 cfg.s.int_en = 1; 699 cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0; 700 cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0; 701 702 /* 140 nS glitch filter*/ 703 cfg.s.fil_cnt = 7; 704 cfg.s.fil_sel = 3; 705 706 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), cfg.u64); 707} 708 709static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data) 710{ 711 octeon_irq_gpio_setup(data); 712 octeon_irq_ciu_enable_v2(data); 713} 714 715static void octeon_irq_ciu_enable_gpio(struct irq_data *data) 716{ 717 octeon_irq_gpio_setup(data); 718 octeon_irq_ciu_enable(data); 719} 720 721static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t) 722{ 723 irqd_set_trigger_type(data, t); 724 octeon_irq_gpio_setup(data); 725 726 if (t & IRQ_TYPE_EDGE_BOTH) 727 irq_set_handler_locked(data, handle_edge_irq); 728 else 729 irq_set_handler_locked(data, handle_level_irq); 730 731 return IRQ_SET_MASK_OK; 732} 733 734static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data) 735{ 736 struct octeon_ciu_chip_data *cd; 737 738 cd = irq_data_get_irq_chip_data(data); 739 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); 740 741 octeon_irq_ciu_disable_all_v2(data); 742} 743 744static void octeon_irq_ciu_disable_gpio(struct irq_data *data) 745{ 746 struct octeon_ciu_chip_data *cd; 747 748 cd = irq_data_get_irq_chip_data(data); 749 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); 750 751 octeon_irq_ciu_disable_all(data); 752} 753 754static void octeon_irq_ciu_gpio_ack(struct irq_data *data) 755{ 756 struct octeon_ciu_chip_data *cd; 757 u64 mask; 758 759 cd = irq_data_get_irq_chip_data(data); 760 mask = 1ull << (cd->gpio_line); 761 762 cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); 763} 764 765#ifdef CONFIG_SMP 766 767static void octeon_irq_cpu_offline_ciu(struct irq_data *data) 768{ 769 int cpu = smp_processor_id(); 770 cpumask_t new_affinity; 771 struct cpumask *mask = irq_data_get_affinity_mask(data); 772 773 if (!cpumask_test_cpu(cpu, mask)) 774 return; 775 776 if (cpumask_weight(mask) > 1) { 777 /* 778 * It has multi CPU affinity, just remove this CPU 779 * from the affinity set. 780 */ 781 cpumask_copy(&new_affinity, mask); 782 cpumask_clear_cpu(cpu, &new_affinity); 783 } else { 784 /* Otherwise, put it on lowest numbered online CPU. */ 785 cpumask_clear(&new_affinity); 786 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity); 787 } 788 irq_set_affinity_locked(data, &new_affinity, false); 789} 790 791static int octeon_irq_ciu_set_affinity(struct irq_data *data, 792 const struct cpumask *dest, bool force) 793{ 794 int cpu; 795 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); 796 unsigned long flags; 797 struct octeon_ciu_chip_data *cd; 798 unsigned long *pen; 799 raw_spinlock_t *lock; 800 801 cd = irq_data_get_irq_chip_data(data); 802 803 /* 804 * For non-v2 CIU, we will allow only single CPU affinity. 805 * This removes the need to do locking in the .ack/.eoi 806 * functions. 807 */ 808 if (cpumask_weight(dest) != 1) 809 return -EINVAL; 810 811 if (!enable_one) 812 return 0; 813 814 815 for_each_online_cpu(cpu) { 816 int coreid = octeon_coreid_for_cpu(cpu); 817 818 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); 819 raw_spin_lock_irqsave(lock, flags); 820 821 if (cd->line == 0) 822 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); 823 else 824 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); 825 826 if (cpumask_test_cpu(cpu, dest) && enable_one) { 827 enable_one = false; 828 __set_bit(cd->bit, pen); 829 } else { 830 __clear_bit(cd->bit, pen); 831 } 832 /* 833 * Must be visible to octeon_irq_ip{2,3}_ciu() before 834 * enabling the irq. 835 */ 836 wmb(); 837 838 if (cd->line == 0) 839 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); 840 else 841 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); 842 843 raw_spin_unlock_irqrestore(lock, flags); 844 } 845 return 0; 846} 847 848/* 849 * Set affinity for the irq for chips that have the EN*_W1{S,C} 850 * registers. 851 */ 852static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data, 853 const struct cpumask *dest, 854 bool force) 855{ 856 int cpu; 857 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); 858 u64 mask; 859 struct octeon_ciu_chip_data *cd; 860 861 if (!enable_one) 862 return 0; 863 864 cd = irq_data_get_irq_chip_data(data); 865 mask = 1ull << cd->bit; 866 867 if (cd->line == 0) { 868 for_each_online_cpu(cpu) { 869 unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); 870 int index = octeon_coreid_for_cpu(cpu) * 2; 871 if (cpumask_test_cpu(cpu, dest) && enable_one) { 872 enable_one = false; 873 set_bit(cd->bit, pen); 874 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 875 } else { 876 clear_bit(cd->bit, pen); 877 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 878 } 879 } 880 } else { 881 for_each_online_cpu(cpu) { 882 unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); 883 int index = octeon_coreid_for_cpu(cpu) * 2 + 1; 884 if (cpumask_test_cpu(cpu, dest) && enable_one) { 885 enable_one = false; 886 set_bit(cd->bit, pen); 887 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 888 } else { 889 clear_bit(cd->bit, pen); 890 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); 891 } 892 } 893 } 894 return 0; 895} 896 897static int octeon_irq_ciu_set_affinity_sum2(struct irq_data *data, 898 const struct cpumask *dest, 899 bool force) 900{ 901 int cpu; 902 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); 903 u64 mask; 904 struct octeon_ciu_chip_data *cd; 905 906 if (!enable_one) 907 return 0; 908 909 cd = irq_data_get_irq_chip_data(data); 910 mask = 1ull << cd->bit; 911 912 for_each_online_cpu(cpu) { 913 int index = octeon_coreid_for_cpu(cpu); 914 915 if (cpumask_test_cpu(cpu, dest) && enable_one) { 916 enable_one = false; 917 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); 918 } else { 919 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); 920 } 921 } 922 return 0; 923} 924#endif 925 926static unsigned int edge_startup(struct irq_data *data) 927{ 928 /* ack any pending edge-irq at startup, so there is 929 * an _edge_ to fire on when the event reappears. 930 */ 931 data->chip->irq_ack(data); 932 data->chip->irq_enable(data); 933 return 0; 934} 935 936/* 937 * Newer octeon chips have support for lockless CIU operation. 938 */ 939static struct irq_chip octeon_irq_chip_ciu_v2 = { 940 .name = "CIU", 941 .irq_enable = octeon_irq_ciu_enable_v2, 942 .irq_disable = octeon_irq_ciu_disable_all_v2, 943 .irq_mask = octeon_irq_ciu_disable_local_v2, 944 .irq_unmask = octeon_irq_ciu_enable_v2, 945#ifdef CONFIG_SMP 946 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, 947 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 948#endif 949}; 950 951static struct irq_chip octeon_irq_chip_ciu_v2_edge = { 952 .name = "CIU", 953 .irq_enable = octeon_irq_ciu_enable_v2, 954 .irq_disable = octeon_irq_ciu_disable_all_v2, 955 .irq_ack = octeon_irq_ciu_ack, 956 .irq_mask = octeon_irq_ciu_disable_local_v2, 957 .irq_unmask = octeon_irq_ciu_enable_v2, 958#ifdef CONFIG_SMP 959 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, 960 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 961#endif 962}; 963 964/* 965 * Newer octeon chips have support for lockless CIU operation. 966 */ 967static struct irq_chip octeon_irq_chip_ciu_sum2 = { 968 .name = "CIU", 969 .irq_enable = octeon_irq_ciu_enable_sum2, 970 .irq_disable = octeon_irq_ciu_disable_all_sum2, 971 .irq_mask = octeon_irq_ciu_disable_local_sum2, 972 .irq_unmask = octeon_irq_ciu_enable_sum2, 973#ifdef CONFIG_SMP 974 .irq_set_affinity = octeon_irq_ciu_set_affinity_sum2, 975 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 976#endif 977}; 978 979static struct irq_chip octeon_irq_chip_ciu_sum2_edge = { 980 .name = "CIU", 981 .irq_enable = octeon_irq_ciu_enable_sum2, 982 .irq_disable = octeon_irq_ciu_disable_all_sum2, 983 .irq_ack = octeon_irq_ciu_ack_sum2, 984 .irq_mask = octeon_irq_ciu_disable_local_sum2, 985 .irq_unmask = octeon_irq_ciu_enable_sum2, 986#ifdef CONFIG_SMP 987 .irq_set_affinity = octeon_irq_ciu_set_affinity_sum2, 988 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 989#endif 990}; 991 992static struct irq_chip octeon_irq_chip_ciu = { 993 .name = "CIU", 994 .irq_enable = octeon_irq_ciu_enable, 995 .irq_disable = octeon_irq_ciu_disable_all, 996 .irq_mask = octeon_irq_ciu_disable_local, 997 .irq_unmask = octeon_irq_ciu_enable, 998#ifdef CONFIG_SMP 999 .irq_set_affinity = octeon_irq_ciu_set_affinity, 1000 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 1001#endif 1002}; 1003 1004static struct irq_chip octeon_irq_chip_ciu_edge = { 1005 .name = "CIU", 1006 .irq_enable = octeon_irq_ciu_enable, 1007 .irq_disable = octeon_irq_ciu_disable_all, 1008 .irq_ack = octeon_irq_ciu_ack, 1009 .irq_mask = octeon_irq_ciu_disable_local, 1010 .irq_unmask = octeon_irq_ciu_enable, 1011#ifdef CONFIG_SMP 1012 .irq_set_affinity = octeon_irq_ciu_set_affinity, 1013 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 1014#endif 1015}; 1016 1017/* The mbox versions don't do any affinity or round-robin. */ 1018static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = { 1019 .name = "CIU-M", 1020 .irq_enable = octeon_irq_ciu_enable_all_v2, 1021 .irq_disable = octeon_irq_ciu_disable_all_v2, 1022 .irq_ack = octeon_irq_ciu_disable_local_v2, 1023 .irq_eoi = octeon_irq_ciu_enable_local_v2, 1024 1025 .irq_cpu_online = octeon_irq_ciu_enable_local_v2, 1026 .irq_cpu_offline = octeon_irq_ciu_disable_local_v2, 1027 .flags = IRQCHIP_ONOFFLINE_ENABLED, 1028}; 1029 1030static struct irq_chip octeon_irq_chip_ciu_mbox = { 1031 .name = "CIU-M", 1032 .irq_enable = octeon_irq_ciu_enable_all, 1033 .irq_disable = octeon_irq_ciu_disable_all, 1034 .irq_ack = octeon_irq_ciu_disable_local, 1035 .irq_eoi = octeon_irq_ciu_enable_local, 1036 1037 .irq_cpu_online = octeon_irq_ciu_enable_local, 1038 .irq_cpu_offline = octeon_irq_ciu_disable_local, 1039 .flags = IRQCHIP_ONOFFLINE_ENABLED, 1040}; 1041 1042static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = { 1043 .name = "CIU-GPIO", 1044 .irq_enable = octeon_irq_ciu_enable_gpio_v2, 1045 .irq_disable = octeon_irq_ciu_disable_gpio_v2, 1046 .irq_ack = octeon_irq_ciu_gpio_ack, 1047 .irq_mask = octeon_irq_ciu_disable_local_v2, 1048 .irq_unmask = octeon_irq_ciu_enable_v2, 1049 .irq_set_type = octeon_irq_ciu_gpio_set_type, 1050#ifdef CONFIG_SMP 1051 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, 1052 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 1053#endif 1054 .flags = IRQCHIP_SET_TYPE_MASKED, 1055}; 1056 1057static struct irq_chip octeon_irq_chip_ciu_gpio = { 1058 .name = "CIU-GPIO", 1059 .irq_enable = octeon_irq_ciu_enable_gpio, 1060 .irq_disable = octeon_irq_ciu_disable_gpio, 1061 .irq_mask = octeon_irq_ciu_disable_local, 1062 .irq_unmask = octeon_irq_ciu_enable, 1063 .irq_ack = octeon_irq_ciu_gpio_ack, 1064 .irq_set_type = octeon_irq_ciu_gpio_set_type, 1065#ifdef CONFIG_SMP 1066 .irq_set_affinity = octeon_irq_ciu_set_affinity, 1067 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 1068#endif 1069 .flags = IRQCHIP_SET_TYPE_MASKED, 1070}; 1071 1072/* 1073 * Watchdog interrupts are special. They are associated with a single 1074 * core, so we hardwire the affinity to that core. 1075 */ 1076static void octeon_irq_ciu_wd_enable(struct irq_data *data) 1077{ 1078 unsigned long flags; 1079 unsigned long *pen; 1080 int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 1081 int cpu = octeon_cpu_for_coreid(coreid); 1082 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); 1083 1084 raw_spin_lock_irqsave(lock, flags); 1085 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); 1086 __set_bit(coreid, pen); 1087 /* 1088 * Must be visible to octeon_irq_ip{2,3}_ciu() before enabling 1089 * the irq. 1090 */ 1091 wmb(); 1092 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); 1093 raw_spin_unlock_irqrestore(lock, flags); 1094} 1095 1096/* 1097 * Watchdog interrupts are special. They are associated with a single 1098 * core, so we hardwire the affinity to that core. 1099 */ 1100static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data) 1101{ 1102 int coreid = data->irq - OCTEON_IRQ_WDOG0; 1103 int cpu = octeon_cpu_for_coreid(coreid); 1104 1105 set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); 1106 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid); 1107} 1108 1109 1110static struct irq_chip octeon_irq_chip_ciu_wd_v2 = { 1111 .name = "CIU-W", 1112 .irq_enable = octeon_irq_ciu1_wd_enable_v2, 1113 .irq_disable = octeon_irq_ciu_disable_all_v2, 1114 .irq_mask = octeon_irq_ciu_disable_local_v2, 1115 .irq_unmask = octeon_irq_ciu_enable_local_v2, 1116}; 1117 1118static struct irq_chip octeon_irq_chip_ciu_wd = { 1119 .name = "CIU-W", 1120 .irq_enable = octeon_irq_ciu_wd_enable, 1121 .irq_disable = octeon_irq_ciu_disable_all, 1122 .irq_mask = octeon_irq_ciu_disable_local, 1123 .irq_unmask = octeon_irq_ciu_enable_local, 1124}; 1125 1126static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit) 1127{ 1128 bool edge = false; 1129 1130 if (line == 0) 1131 switch (bit) { 1132 case 48 ... 49: /* GMX DRP */ 1133 case 50: /* IPD_DRP */ 1134 case 52 ... 55: /* Timers */ 1135 case 58: /* MPI */ 1136 edge = true; 1137 break; 1138 default: 1139 break; 1140 } 1141 else /* line == 1 */ 1142 switch (bit) { 1143 case 47: /* PTP */ 1144 edge = true; 1145 break; 1146 default: 1147 break; 1148 } 1149 return edge; 1150} 1151 1152struct octeon_irq_gpio_domain_data { 1153 unsigned int base_hwirq; 1154}; 1155 1156static int octeon_irq_gpio_xlat(struct irq_domain *d, 1157 struct device_node *node, 1158 const u32 *intspec, 1159 unsigned int intsize, 1160 unsigned long *out_hwirq, 1161 unsigned int *out_type) 1162{ 1163 unsigned int type; 1164 unsigned int pin; 1165 unsigned int trigger; 1166 1167 if (irq_domain_get_of_node(d) != node) 1168 return -EINVAL; 1169 1170 if (intsize < 2) 1171 return -EINVAL; 1172 1173 pin = intspec[0]; 1174 if (pin >= 16) 1175 return -EINVAL; 1176 1177 trigger = intspec[1]; 1178 1179 switch (trigger) { 1180 case 1: 1181 type = IRQ_TYPE_EDGE_RISING; 1182 break; 1183 case 2: 1184 type = IRQ_TYPE_EDGE_FALLING; 1185 break; 1186 case 4: 1187 type = IRQ_TYPE_LEVEL_HIGH; 1188 break; 1189 case 8: 1190 type = IRQ_TYPE_LEVEL_LOW; 1191 break; 1192 default: 1193 pr_err("Error: (%pOFn) Invalid irq trigger specification: %x\n", 1194 node, 1195 trigger); 1196 type = IRQ_TYPE_LEVEL_LOW; 1197 break; 1198 } 1199 *out_type = type; 1200 *out_hwirq = pin; 1201 1202 return 0; 1203} 1204 1205static int octeon_irq_ciu_xlat(struct irq_domain *d, 1206 struct device_node *node, 1207 const u32 *intspec, 1208 unsigned int intsize, 1209 unsigned long *out_hwirq, 1210 unsigned int *out_type) 1211{ 1212 unsigned int ciu, bit; 1213 struct octeon_irq_ciu_domain_data *dd = d->host_data; 1214 1215 ciu = intspec[0]; 1216 bit = intspec[1]; 1217 1218 if (ciu >= dd->num_sum || bit > 63) 1219 return -EINVAL; 1220 1221 *out_hwirq = (ciu << 6) | bit; 1222 *out_type = 0; 1223 1224 return 0; 1225} 1226 1227static struct irq_chip *octeon_irq_ciu_chip; 1228static struct irq_chip *octeon_irq_ciu_chip_edge; 1229static struct irq_chip *octeon_irq_gpio_chip; 1230 1231static int octeon_irq_ciu_map(struct irq_domain *d, 1232 unsigned int virq, irq_hw_number_t hw) 1233{ 1234 int rv; 1235 unsigned int line = hw >> 6; 1236 unsigned int bit = hw & 63; 1237 struct octeon_irq_ciu_domain_data *dd = d->host_data; 1238 1239 if (line >= dd->num_sum || octeon_irq_ciu_to_irq[line][bit] != 0) 1240 return -EINVAL; 1241 1242 if (line == 2) { 1243 if (octeon_irq_ciu_is_edge(line, bit)) 1244 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, 1245 &octeon_irq_chip_ciu_sum2_edge, 1246 handle_edge_irq); 1247 else 1248 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, 1249 &octeon_irq_chip_ciu_sum2, 1250 handle_level_irq); 1251 } else { 1252 if (octeon_irq_ciu_is_edge(line, bit)) 1253 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, 1254 octeon_irq_ciu_chip_edge, 1255 handle_edge_irq); 1256 else 1257 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, 1258 octeon_irq_ciu_chip, 1259 handle_level_irq); 1260 } 1261 return rv; 1262} 1263 1264static int octeon_irq_gpio_map(struct irq_domain *d, 1265 unsigned int virq, irq_hw_number_t hw) 1266{ 1267 struct octeon_irq_gpio_domain_data *gpiod = d->host_data; 1268 unsigned int line, bit; 1269 int r; 1270 1271 line = (hw + gpiod->base_hwirq) >> 6; 1272 bit = (hw + gpiod->base_hwirq) & 63; 1273 if (line >= ARRAY_SIZE(octeon_irq_ciu_to_irq) || 1274 octeon_irq_ciu_to_irq[line][bit] != 0) 1275 return -EINVAL; 1276 1277 /* 1278 * Default to handle_level_irq. If the DT contains a different 1279 * trigger type, it will call the irq_set_type callback and 1280 * the handler gets updated. 1281 */ 1282 r = octeon_irq_set_ciu_mapping(virq, line, bit, hw, 1283 octeon_irq_gpio_chip, handle_level_irq); 1284 return r; 1285} 1286 1287static struct irq_domain_ops octeon_irq_domain_ciu_ops = { 1288 .map = octeon_irq_ciu_map, 1289 .unmap = octeon_irq_free_cd, 1290 .xlate = octeon_irq_ciu_xlat, 1291}; 1292 1293static struct irq_domain_ops octeon_irq_domain_gpio_ops = { 1294 .map = octeon_irq_gpio_map, 1295 .unmap = octeon_irq_free_cd, 1296 .xlate = octeon_irq_gpio_xlat, 1297}; 1298 1299static void octeon_irq_ip2_ciu(void) 1300{ 1301 const unsigned long core_id = cvmx_get_core_num(); 1302 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); 1303 1304 ciu_sum &= __this_cpu_read(octeon_irq_ciu0_en_mirror); 1305 if (likely(ciu_sum)) { 1306 int bit = fls64(ciu_sum) - 1; 1307 int irq = octeon_irq_ciu_to_irq[0][bit]; 1308 if (likely(irq)) 1309 do_IRQ(irq); 1310 else 1311 spurious_interrupt(); 1312 } else { 1313 spurious_interrupt(); 1314 } 1315} 1316 1317static void octeon_irq_ip3_ciu(void) 1318{ 1319 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); 1320 1321 ciu_sum &= __this_cpu_read(octeon_irq_ciu1_en_mirror); 1322 if (likely(ciu_sum)) { 1323 int bit = fls64(ciu_sum) - 1; 1324 int irq = octeon_irq_ciu_to_irq[1][bit]; 1325 if (likely(irq)) 1326 do_IRQ(irq); 1327 else 1328 spurious_interrupt(); 1329 } else { 1330 spurious_interrupt(); 1331 } 1332} 1333 1334static void octeon_irq_ip4_ciu(void) 1335{ 1336 int coreid = cvmx_get_core_num(); 1337 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_SUM2_PPX_IP4(coreid)); 1338 u64 ciu_en = cvmx_read_csr(CVMX_CIU_EN2_PPX_IP4(coreid)); 1339 1340 ciu_sum &= ciu_en; 1341 if (likely(ciu_sum)) { 1342 int bit = fls64(ciu_sum) - 1; 1343 int irq = octeon_irq_ciu_to_irq[2][bit]; 1344 1345 if (likely(irq)) 1346 do_IRQ(irq); 1347 else 1348 spurious_interrupt(); 1349 } else { 1350 spurious_interrupt(); 1351 } 1352} 1353 1354static bool octeon_irq_use_ip4; 1355 1356static void octeon_irq_local_enable_ip4(void *arg) 1357{ 1358 set_c0_status(STATUSF_IP4); 1359} 1360 1361static void octeon_irq_ip4_mask(void) 1362{ 1363 clear_c0_status(STATUSF_IP4); 1364 spurious_interrupt(); 1365} 1366 1367static void (*octeon_irq_ip2)(void); 1368static void (*octeon_irq_ip3)(void); 1369static void (*octeon_irq_ip4)(void); 1370 1371void (*octeon_irq_setup_secondary)(void); 1372 1373void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h) 1374{ 1375 octeon_irq_ip4 = h; 1376 octeon_irq_use_ip4 = true; 1377 on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1); 1378} 1379 1380static void octeon_irq_percpu_enable(void) 1381{ 1382 irq_cpu_online(); 1383} 1384 1385static void octeon_irq_init_ciu_percpu(void) 1386{ 1387 int coreid = cvmx_get_core_num(); 1388 1389 1390 __this_cpu_write(octeon_irq_ciu0_en_mirror, 0); 1391 __this_cpu_write(octeon_irq_ciu1_en_mirror, 0); 1392 wmb(); 1393 raw_spin_lock_init(this_cpu_ptr(&octeon_irq_ciu_spinlock)); 1394 /* 1395 * Disable All CIU Interrupts. The ones we need will be 1396 * enabled later. Read the SUM register so we know the write 1397 * completed. 1398 */ 1399 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); 1400 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); 1401 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); 1402 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); 1403 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); 1404} 1405 1406static void octeon_irq_init_ciu2_percpu(void) 1407{ 1408 u64 regx, ipx; 1409 int coreid = cvmx_get_core_num(); 1410 u64 base = CVMX_CIU2_EN_PPX_IP2_WRKQ(coreid); 1411 1412 /* 1413 * Disable All CIU2 Interrupts. The ones we need will be 1414 * enabled later. Read the SUM register so we know the write 1415 * completed. 1416 * 1417 * There are 9 registers and 3 IPX levels with strides 0x1000 1418 * and 0x200 respectivly. Use loops to clear them. 1419 */ 1420 for (regx = 0; regx <= 0x8000; regx += 0x1000) { 1421 for (ipx = 0; ipx <= 0x400; ipx += 0x200) 1422 cvmx_write_csr(base + regx + ipx, 0); 1423 } 1424 1425 cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)); 1426} 1427 1428static void octeon_irq_setup_secondary_ciu(void) 1429{ 1430 octeon_irq_init_ciu_percpu(); 1431 octeon_irq_percpu_enable(); 1432 1433 /* Enable the CIU lines */ 1434 set_c0_status(STATUSF_IP3 | STATUSF_IP2); 1435 if (octeon_irq_use_ip4) 1436 set_c0_status(STATUSF_IP4); 1437 else 1438 clear_c0_status(STATUSF_IP4); 1439} 1440 1441static void octeon_irq_setup_secondary_ciu2(void) 1442{ 1443 octeon_irq_init_ciu2_percpu(); 1444 octeon_irq_percpu_enable(); 1445 1446 /* Enable the CIU lines */ 1447 set_c0_status(STATUSF_IP3 | STATUSF_IP2); 1448 if (octeon_irq_use_ip4) 1449 set_c0_status(STATUSF_IP4); 1450 else 1451 clear_c0_status(STATUSF_IP4); 1452} 1453 1454static int __init octeon_irq_init_ciu( 1455 struct device_node *ciu_node, struct device_node *parent) 1456{ 1457 unsigned int i, r; 1458 struct irq_chip *chip; 1459 struct irq_chip *chip_edge; 1460 struct irq_chip *chip_mbox; 1461 struct irq_chip *chip_wd; 1462 struct irq_domain *ciu_domain = NULL; 1463 struct octeon_irq_ciu_domain_data *dd; 1464 1465 dd = kzalloc(sizeof(*dd), GFP_KERNEL); 1466 if (!dd) 1467 return -ENOMEM; 1468 1469 octeon_irq_init_ciu_percpu(); 1470 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; 1471 1472 octeon_irq_ip2 = octeon_irq_ip2_ciu; 1473 octeon_irq_ip3 = octeon_irq_ip3_ciu; 1474 if ((OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) 1475 && !OCTEON_IS_MODEL(OCTEON_CN63XX)) { 1476 octeon_irq_ip4 = octeon_irq_ip4_ciu; 1477 dd->num_sum = 3; 1478 octeon_irq_use_ip4 = true; 1479 } else { 1480 octeon_irq_ip4 = octeon_irq_ip4_mask; 1481 dd->num_sum = 2; 1482 octeon_irq_use_ip4 = false; 1483 } 1484 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || 1485 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || 1486 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || 1487 OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) { 1488 chip = &octeon_irq_chip_ciu_v2; 1489 chip_edge = &octeon_irq_chip_ciu_v2_edge; 1490 chip_mbox = &octeon_irq_chip_ciu_mbox_v2; 1491 chip_wd = &octeon_irq_chip_ciu_wd_v2; 1492 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2; 1493 } else { 1494 chip = &octeon_irq_chip_ciu; 1495 chip_edge = &octeon_irq_chip_ciu_edge; 1496 chip_mbox = &octeon_irq_chip_ciu_mbox; 1497 chip_wd = &octeon_irq_chip_ciu_wd; 1498 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio; 1499 } 1500 octeon_irq_ciu_chip = chip; 1501 octeon_irq_ciu_chip_edge = chip_edge; 1502 1503 /* Mips internal */ 1504 octeon_irq_init_core(); 1505 1506 ciu_domain = irq_domain_add_tree( 1507 ciu_node, &octeon_irq_domain_ciu_ops, dd); 1508 irq_set_default_host(ciu_domain); 1509 1510 /* CIU_0 */ 1511 for (i = 0; i < 16; i++) { 1512 r = octeon_irq_force_ciu_mapping( 1513 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0); 1514 if (r) 1515 goto err; 1516 } 1517 1518 r = octeon_irq_set_ciu_mapping( 1519 OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq); 1520 if (r) 1521 goto err; 1522 r = octeon_irq_set_ciu_mapping( 1523 OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq); 1524 if (r) 1525 goto err; 1526 1527 for (i = 0; i < 4; i++) { 1528 r = octeon_irq_force_ciu_mapping( 1529 ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36); 1530 if (r) 1531 goto err; 1532 } 1533 for (i = 0; i < 4; i++) { 1534 r = octeon_irq_force_ciu_mapping( 1535 ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40); 1536 if (r) 1537 goto err; 1538 } 1539 1540 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI, 0, 45); 1541 if (r) 1542 goto err; 1543 1544 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46); 1545 if (r) 1546 goto err; 1547 1548 for (i = 0; i < 4; i++) { 1549 r = octeon_irq_force_ciu_mapping( 1550 ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52); 1551 if (r) 1552 goto err; 1553 } 1554 1555 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI2, 0, 59); 1556 if (r) 1557 goto err; 1558 1559 /* CIU_1 */ 1560 for (i = 0; i < 16; i++) { 1561 r = octeon_irq_set_ciu_mapping( 1562 i + OCTEON_IRQ_WDOG0, 1, i + 0, 0, chip_wd, 1563 handle_level_irq); 1564 if (r) 1565 goto err; 1566 } 1567 1568 /* Enable the CIU lines */ 1569 set_c0_status(STATUSF_IP3 | STATUSF_IP2); 1570 if (octeon_irq_use_ip4) 1571 set_c0_status(STATUSF_IP4); 1572 else 1573 clear_c0_status(STATUSF_IP4); 1574 1575 return 0; 1576err: 1577 return r; 1578} 1579 1580static int __init octeon_irq_init_gpio( 1581 struct device_node *gpio_node, struct device_node *parent) 1582{ 1583 struct octeon_irq_gpio_domain_data *gpiod; 1584 u32 interrupt_cells; 1585 unsigned int base_hwirq; 1586 int r; 1587 1588 r = of_property_read_u32(parent, "#interrupt-cells", &interrupt_cells); 1589 if (r) 1590 return r; 1591 1592 if (interrupt_cells == 1) { 1593 u32 v; 1594 1595 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v); 1596 if (r) { 1597 pr_warn("No \"interrupts\" property.\n"); 1598 return r; 1599 } 1600 base_hwirq = v; 1601 } else if (interrupt_cells == 2) { 1602 u32 v0, v1; 1603 1604 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v0); 1605 if (r) { 1606 pr_warn("No \"interrupts\" property.\n"); 1607 return r; 1608 } 1609 r = of_property_read_u32_index(gpio_node, "interrupts", 1, &v1); 1610 if (r) { 1611 pr_warn("No \"interrupts\" property.\n"); 1612 return r; 1613 } 1614 base_hwirq = (v0 << 6) | v1; 1615 } else { 1616 pr_warn("Bad \"#interrupt-cells\" property: %u\n", 1617 interrupt_cells); 1618 return -EINVAL; 1619 } 1620 1621 gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL); 1622 if (gpiod) { 1623 /* gpio domain host_data is the base hwirq number. */ 1624 gpiod->base_hwirq = base_hwirq; 1625 irq_domain_add_linear( 1626 gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod); 1627 } else { 1628 pr_warn("Cannot allocate memory for GPIO irq_domain.\n"); 1629 return -ENOMEM; 1630 } 1631 1632 /* 1633 * Clear the OF_POPULATED flag that was set by of_irq_init() 1634 * so that all GPIO devices will be probed. 1635 */ 1636 of_node_clear_flag(gpio_node, OF_POPULATED); 1637 1638 return 0; 1639} 1640/* 1641 * Watchdog interrupts are special. They are associated with a single 1642 * core, so we hardwire the affinity to that core. 1643 */ 1644static void octeon_irq_ciu2_wd_enable(struct irq_data *data) 1645{ 1646 u64 mask; 1647 u64 en_addr; 1648 int coreid = data->irq - OCTEON_IRQ_WDOG0; 1649 struct octeon_ciu_chip_data *cd; 1650 1651 cd = irq_data_get_irq_chip_data(data); 1652 mask = 1ull << (cd->bit); 1653 1654 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + 1655 (0x1000ull * cd->line); 1656 cvmx_write_csr(en_addr, mask); 1657 1658} 1659 1660static void octeon_irq_ciu2_enable(struct irq_data *data) 1661{ 1662 u64 mask; 1663 u64 en_addr; 1664 int cpu = next_cpu_for_irq(data); 1665 int coreid = octeon_coreid_for_cpu(cpu); 1666 struct octeon_ciu_chip_data *cd; 1667 1668 cd = irq_data_get_irq_chip_data(data); 1669 mask = 1ull << (cd->bit); 1670 1671 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + 1672 (0x1000ull * cd->line); 1673 cvmx_write_csr(en_addr, mask); 1674} 1675 1676static void octeon_irq_ciu2_enable_local(struct irq_data *data) 1677{ 1678 u64 mask; 1679 u64 en_addr; 1680 int coreid = cvmx_get_core_num(); 1681 struct octeon_ciu_chip_data *cd; 1682 1683 cd = irq_data_get_irq_chip_data(data); 1684 mask = 1ull << (cd->bit); 1685 1686 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + 1687 (0x1000ull * cd->line); 1688 cvmx_write_csr(en_addr, mask); 1689 1690} 1691 1692static void octeon_irq_ciu2_disable_local(struct irq_data *data) 1693{ 1694 u64 mask; 1695 u64 en_addr; 1696 int coreid = cvmx_get_core_num(); 1697 struct octeon_ciu_chip_data *cd; 1698 1699 cd = irq_data_get_irq_chip_data(data); 1700 mask = 1ull << (cd->bit); 1701 1702 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(coreid) + 1703 (0x1000ull * cd->line); 1704 cvmx_write_csr(en_addr, mask); 1705 1706} 1707 1708static void octeon_irq_ciu2_ack(struct irq_data *data) 1709{ 1710 u64 mask; 1711 u64 en_addr; 1712 int coreid = cvmx_get_core_num(); 1713 struct octeon_ciu_chip_data *cd; 1714 1715 cd = irq_data_get_irq_chip_data(data); 1716 mask = 1ull << (cd->bit); 1717 1718 en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd->line); 1719 cvmx_write_csr(en_addr, mask); 1720 1721} 1722 1723static void octeon_irq_ciu2_disable_all(struct irq_data *data) 1724{ 1725 int cpu; 1726 u64 mask; 1727 struct octeon_ciu_chip_data *cd; 1728 1729 cd = irq_data_get_irq_chip_data(data); 1730 mask = 1ull << (cd->bit); 1731 1732 for_each_online_cpu(cpu) { 1733 u64 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C( 1734 octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd->line); 1735 cvmx_write_csr(en_addr, mask); 1736 } 1737} 1738 1739static void octeon_irq_ciu2_mbox_enable_all(struct irq_data *data) 1740{ 1741 int cpu; 1742 u64 mask; 1743 1744 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); 1745 1746 for_each_online_cpu(cpu) { 1747 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S( 1748 octeon_coreid_for_cpu(cpu)); 1749 cvmx_write_csr(en_addr, mask); 1750 } 1751} 1752 1753static void octeon_irq_ciu2_mbox_disable_all(struct irq_data *data) 1754{ 1755 int cpu; 1756 u64 mask; 1757 1758 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); 1759 1760 for_each_online_cpu(cpu) { 1761 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C( 1762 octeon_coreid_for_cpu(cpu)); 1763 cvmx_write_csr(en_addr, mask); 1764 } 1765} 1766 1767static void octeon_irq_ciu2_mbox_enable_local(struct irq_data *data) 1768{ 1769 u64 mask; 1770 u64 en_addr; 1771 int coreid = cvmx_get_core_num(); 1772 1773 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); 1774 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(coreid); 1775 cvmx_write_csr(en_addr, mask); 1776} 1777 1778static void octeon_irq_ciu2_mbox_disable_local(struct irq_data *data) 1779{ 1780 u64 mask; 1781 u64 en_addr; 1782 int coreid = cvmx_get_core_num(); 1783 1784 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); 1785 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(coreid); 1786 cvmx_write_csr(en_addr, mask); 1787} 1788 1789#ifdef CONFIG_SMP 1790static int octeon_irq_ciu2_set_affinity(struct irq_data *data, 1791 const struct cpumask *dest, bool force) 1792{ 1793 int cpu; 1794 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); 1795 u64 mask; 1796 struct octeon_ciu_chip_data *cd; 1797 1798 if (!enable_one) 1799 return 0; 1800 1801 cd = irq_data_get_irq_chip_data(data); 1802 mask = 1ull << cd->bit; 1803 1804 for_each_online_cpu(cpu) { 1805 u64 en_addr; 1806 if (cpumask_test_cpu(cpu, dest) && enable_one) { 1807 enable_one = false; 1808 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S( 1809 octeon_coreid_for_cpu(cpu)) + 1810 (0x1000ull * cd->line); 1811 } else { 1812 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C( 1813 octeon_coreid_for_cpu(cpu)) + 1814 (0x1000ull * cd->line); 1815 } 1816 cvmx_write_csr(en_addr, mask); 1817 } 1818 1819 return 0; 1820} 1821#endif 1822 1823static void octeon_irq_ciu2_enable_gpio(struct irq_data *data) 1824{ 1825 octeon_irq_gpio_setup(data); 1826 octeon_irq_ciu2_enable(data); 1827} 1828 1829static void octeon_irq_ciu2_disable_gpio(struct irq_data *data) 1830{ 1831 struct octeon_ciu_chip_data *cd; 1832 1833 cd = irq_data_get_irq_chip_data(data); 1834 1835 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); 1836 1837 octeon_irq_ciu2_disable_all(data); 1838} 1839 1840static struct irq_chip octeon_irq_chip_ciu2 = { 1841 .name = "CIU2-E", 1842 .irq_enable = octeon_irq_ciu2_enable, 1843 .irq_disable = octeon_irq_ciu2_disable_all, 1844 .irq_mask = octeon_irq_ciu2_disable_local, 1845 .irq_unmask = octeon_irq_ciu2_enable, 1846#ifdef CONFIG_SMP 1847 .irq_set_affinity = octeon_irq_ciu2_set_affinity, 1848 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 1849#endif 1850}; 1851 1852static struct irq_chip octeon_irq_chip_ciu2_edge = { 1853 .name = "CIU2-E", 1854 .irq_enable = octeon_irq_ciu2_enable, 1855 .irq_disable = octeon_irq_ciu2_disable_all, 1856 .irq_ack = octeon_irq_ciu2_ack, 1857 .irq_mask = octeon_irq_ciu2_disable_local, 1858 .irq_unmask = octeon_irq_ciu2_enable, 1859#ifdef CONFIG_SMP 1860 .irq_set_affinity = octeon_irq_ciu2_set_affinity, 1861 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 1862#endif 1863}; 1864 1865static struct irq_chip octeon_irq_chip_ciu2_mbox = { 1866 .name = "CIU2-M", 1867 .irq_enable = octeon_irq_ciu2_mbox_enable_all, 1868 .irq_disable = octeon_irq_ciu2_mbox_disable_all, 1869 .irq_ack = octeon_irq_ciu2_mbox_disable_local, 1870 .irq_eoi = octeon_irq_ciu2_mbox_enable_local, 1871 1872 .irq_cpu_online = octeon_irq_ciu2_mbox_enable_local, 1873 .irq_cpu_offline = octeon_irq_ciu2_mbox_disable_local, 1874 .flags = IRQCHIP_ONOFFLINE_ENABLED, 1875}; 1876 1877static struct irq_chip octeon_irq_chip_ciu2_wd = { 1878 .name = "CIU2-W", 1879 .irq_enable = octeon_irq_ciu2_wd_enable, 1880 .irq_disable = octeon_irq_ciu2_disable_all, 1881 .irq_mask = octeon_irq_ciu2_disable_local, 1882 .irq_unmask = octeon_irq_ciu2_enable_local, 1883}; 1884 1885static struct irq_chip octeon_irq_chip_ciu2_gpio = { 1886 .name = "CIU-GPIO", 1887 .irq_enable = octeon_irq_ciu2_enable_gpio, 1888 .irq_disable = octeon_irq_ciu2_disable_gpio, 1889 .irq_ack = octeon_irq_ciu_gpio_ack, 1890 .irq_mask = octeon_irq_ciu2_disable_local, 1891 .irq_unmask = octeon_irq_ciu2_enable, 1892 .irq_set_type = octeon_irq_ciu_gpio_set_type, 1893#ifdef CONFIG_SMP 1894 .irq_set_affinity = octeon_irq_ciu2_set_affinity, 1895 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 1896#endif 1897 .flags = IRQCHIP_SET_TYPE_MASKED, 1898}; 1899 1900static int octeon_irq_ciu2_xlat(struct irq_domain *d, 1901 struct device_node *node, 1902 const u32 *intspec, 1903 unsigned int intsize, 1904 unsigned long *out_hwirq, 1905 unsigned int *out_type) 1906{ 1907 unsigned int ciu, bit; 1908 1909 ciu = intspec[0]; 1910 bit = intspec[1]; 1911 1912 *out_hwirq = (ciu << 6) | bit; 1913 *out_type = 0; 1914 1915 return 0; 1916} 1917 1918static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit) 1919{ 1920 bool edge = false; 1921 1922 if (line == 3) /* MIO */ 1923 switch (bit) { 1924 case 2: /* IPD_DRP */ 1925 case 8 ... 11: /* Timers */ 1926 case 48: /* PTP */ 1927 edge = true; 1928 break; 1929 default: 1930 break; 1931 } 1932 else if (line == 6) /* PKT */ 1933 switch (bit) { 1934 case 52 ... 53: /* ILK_DRP */ 1935 case 8 ... 12: /* GMX_DRP */ 1936 edge = true; 1937 break; 1938 default: 1939 break; 1940 } 1941 return edge; 1942} 1943 1944static int octeon_irq_ciu2_map(struct irq_domain *d, 1945 unsigned int virq, irq_hw_number_t hw) 1946{ 1947 unsigned int line = hw >> 6; 1948 unsigned int bit = hw & 63; 1949 1950 /* 1951 * Don't map irq if it is reserved for GPIO. 1952 * (Line 7 are the GPIO lines.) 1953 */ 1954 if (line == 7) 1955 return 0; 1956 1957 if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0) 1958 return -EINVAL; 1959 1960 if (octeon_irq_ciu2_is_edge(line, bit)) 1961 octeon_irq_set_ciu_mapping(virq, line, bit, 0, 1962 &octeon_irq_chip_ciu2_edge, 1963 handle_edge_irq); 1964 else 1965 octeon_irq_set_ciu_mapping(virq, line, bit, 0, 1966 &octeon_irq_chip_ciu2, 1967 handle_level_irq); 1968 1969 return 0; 1970} 1971 1972static struct irq_domain_ops octeon_irq_domain_ciu2_ops = { 1973 .map = octeon_irq_ciu2_map, 1974 .unmap = octeon_irq_free_cd, 1975 .xlate = octeon_irq_ciu2_xlat, 1976}; 1977 1978static void octeon_irq_ciu2(void) 1979{ 1980 int line; 1981 int bit; 1982 int irq; 1983 u64 src_reg, src, sum; 1984 const unsigned long core_id = cvmx_get_core_num(); 1985 1986 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful; 1987 1988 if (unlikely(!sum)) 1989 goto spurious; 1990 1991 line = fls64(sum) - 1; 1992 src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core_id) + (0x1000 * line); 1993 src = cvmx_read_csr(src_reg); 1994 1995 if (unlikely(!src)) 1996 goto spurious; 1997 1998 bit = fls64(src) - 1; 1999 irq = octeon_irq_ciu_to_irq[line][bit]; 2000 if (unlikely(!irq)) 2001 goto spurious; 2002 2003 do_IRQ(irq); 2004 goto out; 2005 2006spurious: 2007 spurious_interrupt(); 2008out: 2009 /* CN68XX pass 1.x has an errata that accessing the ACK registers 2010 can stop interrupts from propagating */ 2011 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 2012 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY); 2013 else 2014 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id)); 2015 return; 2016} 2017 2018static void octeon_irq_ciu2_mbox(void) 2019{ 2020 int line; 2021 2022 const unsigned long core_id = cvmx_get_core_num(); 2023 u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60; 2024 2025 if (unlikely(!sum)) 2026 goto spurious; 2027 2028 line = fls64(sum) - 1; 2029 2030 do_IRQ(OCTEON_IRQ_MBOX0 + line); 2031 goto out; 2032 2033spurious: 2034 spurious_interrupt(); 2035out: 2036 /* CN68XX pass 1.x has an errata that accessing the ACK registers 2037 can stop interrupts from propagating */ 2038 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 2039 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY); 2040 else 2041 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id)); 2042 return; 2043} 2044 2045static int __init octeon_irq_init_ciu2( 2046 struct device_node *ciu_node, struct device_node *parent) 2047{ 2048 unsigned int i, r; 2049 struct irq_domain *ciu_domain = NULL; 2050 2051 octeon_irq_init_ciu2_percpu(); 2052 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu2; 2053 2054 octeon_irq_gpio_chip = &octeon_irq_chip_ciu2_gpio; 2055 octeon_irq_ip2 = octeon_irq_ciu2; 2056 octeon_irq_ip3 = octeon_irq_ciu2_mbox; 2057 octeon_irq_ip4 = octeon_irq_ip4_mask; 2058 2059 /* Mips internal */ 2060 octeon_irq_init_core(); 2061 2062 ciu_domain = irq_domain_add_tree( 2063 ciu_node, &octeon_irq_domain_ciu2_ops, NULL); 2064 irq_set_default_host(ciu_domain); 2065 2066 /* CUI2 */ 2067 for (i = 0; i < 64; i++) { 2068 r = octeon_irq_force_ciu_mapping( 2069 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i); 2070 if (r) 2071 goto err; 2072 } 2073 2074 for (i = 0; i < 32; i++) { 2075 r = octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i, 0, 2076 &octeon_irq_chip_ciu2_wd, handle_level_irq); 2077 if (r) 2078 goto err; 2079 } 2080 2081 for (i = 0; i < 4; i++) { 2082 r = octeon_irq_force_ciu_mapping( 2083 ciu_domain, i + OCTEON_IRQ_TIMER0, 3, i + 8); 2084 if (r) 2085 goto err; 2086 } 2087 2088 for (i = 0; i < 4; i++) { 2089 r = octeon_irq_force_ciu_mapping( 2090 ciu_domain, i + OCTEON_IRQ_PCI_INT0, 4, i); 2091 if (r) 2092 goto err; 2093 } 2094 2095 for (i = 0; i < 4; i++) { 2096 r = octeon_irq_force_ciu_mapping( 2097 ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 4, i + 8); 2098 if (r) 2099 goto err; 2100 } 2101 2102 irq_set_chip_and_handler(OCTEON_IRQ_MBOX0, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); 2103 irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); 2104 irq_set_chip_and_handler(OCTEON_IRQ_MBOX2, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); 2105 irq_set_chip_and_handler(OCTEON_IRQ_MBOX3, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq); 2106 2107 /* Enable the CIU lines */ 2108 set_c0_status(STATUSF_IP3 | STATUSF_IP2); 2109 clear_c0_status(STATUSF_IP4); 2110 return 0; 2111err: 2112 return r; 2113} 2114 2115struct octeon_irq_cib_host_data { 2116 raw_spinlock_t lock; 2117 u64 raw_reg; 2118 u64 en_reg; 2119 int max_bits; 2120}; 2121 2122struct octeon_irq_cib_chip_data { 2123 struct octeon_irq_cib_host_data *host_data; 2124 int bit; 2125}; 2126 2127static void octeon_irq_cib_enable(struct irq_data *data) 2128{ 2129 unsigned long flags; 2130 u64 en; 2131 struct octeon_irq_cib_chip_data *cd = irq_data_get_irq_chip_data(data); 2132 struct octeon_irq_cib_host_data *host_data = cd->host_data; 2133 2134 raw_spin_lock_irqsave(&host_data->lock, flags); 2135 en = cvmx_read_csr(host_data->en_reg); 2136 en |= 1ull << cd->bit; 2137 cvmx_write_csr(host_data->en_reg, en); 2138 raw_spin_unlock_irqrestore(&host_data->lock, flags); 2139} 2140 2141static void octeon_irq_cib_disable(struct irq_data *data) 2142{ 2143 unsigned long flags; 2144 u64 en; 2145 struct octeon_irq_cib_chip_data *cd = irq_data_get_irq_chip_data(data); 2146 struct octeon_irq_cib_host_data *host_data = cd->host_data; 2147 2148 raw_spin_lock_irqsave(&host_data->lock, flags); 2149 en = cvmx_read_csr(host_data->en_reg); 2150 en &= ~(1ull << cd->bit); 2151 cvmx_write_csr(host_data->en_reg, en); 2152 raw_spin_unlock_irqrestore(&host_data->lock, flags); 2153} 2154 2155static int octeon_irq_cib_set_type(struct irq_data *data, unsigned int t) 2156{ 2157 irqd_set_trigger_type(data, t); 2158 return IRQ_SET_MASK_OK; 2159} 2160 2161static struct irq_chip octeon_irq_chip_cib = { 2162 .name = "CIB", 2163 .irq_enable = octeon_irq_cib_enable, 2164 .irq_disable = octeon_irq_cib_disable, 2165 .irq_mask = octeon_irq_cib_disable, 2166 .irq_unmask = octeon_irq_cib_enable, 2167 .irq_set_type = octeon_irq_cib_set_type, 2168}; 2169 2170static int octeon_irq_cib_xlat(struct irq_domain *d, 2171 struct device_node *node, 2172 const u32 *intspec, 2173 unsigned int intsize, 2174 unsigned long *out_hwirq, 2175 unsigned int *out_type) 2176{ 2177 unsigned int type = 0; 2178 2179 if (intsize == 2) 2180 type = intspec[1]; 2181 2182 switch (type) { 2183 case 0: /* unofficial value, but we might as well let it work. */ 2184 case 4: /* official value for level triggering. */ 2185 *out_type = IRQ_TYPE_LEVEL_HIGH; 2186 break; 2187 case 1: /* official value for edge triggering. */ 2188 *out_type = IRQ_TYPE_EDGE_RISING; 2189 break; 2190 default: /* Nothing else is acceptable. */ 2191 return -EINVAL; 2192 } 2193 2194 *out_hwirq = intspec[0]; 2195 2196 return 0; 2197} 2198 2199static int octeon_irq_cib_map(struct irq_domain *d, 2200 unsigned int virq, irq_hw_number_t hw) 2201{ 2202 struct octeon_irq_cib_host_data *host_data = d->host_data; 2203 struct octeon_irq_cib_chip_data *cd; 2204 2205 if (hw >= host_data->max_bits) { 2206 pr_err("ERROR: %s mapping %u is too big!\n", 2207 irq_domain_get_of_node(d)->name, (unsigned)hw); 2208 return -EINVAL; 2209 } 2210 2211 cd = kzalloc(sizeof(*cd), GFP_KERNEL); 2212 if (!cd) 2213 return -ENOMEM; 2214 2215 cd->host_data = host_data; 2216 cd->bit = hw; 2217 2218 irq_set_chip_and_handler(virq, &octeon_irq_chip_cib, 2219 handle_simple_irq); 2220 irq_set_chip_data(virq, cd); 2221 return 0; 2222} 2223 2224static struct irq_domain_ops octeon_irq_domain_cib_ops = { 2225 .map = octeon_irq_cib_map, 2226 .unmap = octeon_irq_free_cd, 2227 .xlate = octeon_irq_cib_xlat, 2228}; 2229 2230/* Chain to real handler. */ 2231static irqreturn_t octeon_irq_cib_handler(int my_irq, void *data) 2232{ 2233 u64 en; 2234 u64 raw; 2235 u64 bits; 2236 int i; 2237 int irq; 2238 struct irq_domain *cib_domain = data; 2239 struct octeon_irq_cib_host_data *host_data = cib_domain->host_data; 2240 2241 en = cvmx_read_csr(host_data->en_reg); 2242 raw = cvmx_read_csr(host_data->raw_reg); 2243 2244 bits = en & raw; 2245 2246 for (i = 0; i < host_data->max_bits; i++) { 2247 if ((bits & 1ull << i) == 0) 2248 continue; 2249 irq = irq_find_mapping(cib_domain, i); 2250 if (!irq) { 2251 unsigned long flags; 2252 2253 pr_err("ERROR: CIB bit %d@%llx IRQ unhandled, disabling\n", 2254 i, host_data->raw_reg); 2255 raw_spin_lock_irqsave(&host_data->lock, flags); 2256 en = cvmx_read_csr(host_data->en_reg); 2257 en &= ~(1ull << i); 2258 cvmx_write_csr(host_data->en_reg, en); 2259 cvmx_write_csr(host_data->raw_reg, 1ull << i); 2260 raw_spin_unlock_irqrestore(&host_data->lock, flags); 2261 } else { 2262 struct irq_desc *desc = irq_to_desc(irq); 2263 struct irq_data *irq_data = irq_desc_get_irq_data(desc); 2264 /* If edge, acknowledge the bit we will be sending. */ 2265 if (irqd_get_trigger_type(irq_data) & 2266 IRQ_TYPE_EDGE_BOTH) 2267 cvmx_write_csr(host_data->raw_reg, 1ull << i); 2268 generic_handle_irq_desc(desc); 2269 } 2270 } 2271 2272 return IRQ_HANDLED; 2273} 2274 2275static int __init octeon_irq_init_cib(struct device_node *ciu_node, 2276 struct device_node *parent) 2277{ 2278 const __be32 *addr; 2279 u32 val; 2280 struct octeon_irq_cib_host_data *host_data; 2281 int parent_irq; 2282 int r; 2283 struct irq_domain *cib_domain; 2284 2285 parent_irq = irq_of_parse_and_map(ciu_node, 0); 2286 if (!parent_irq) { 2287 pr_err("ERROR: Couldn't acquire parent_irq for %pOFn\n", 2288 ciu_node); 2289 return -EINVAL; 2290 } 2291 2292 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); 2293 if (!host_data) 2294 return -ENOMEM; 2295 raw_spin_lock_init(&host_data->lock); 2296 2297 addr = of_get_address(ciu_node, 0, NULL, NULL); 2298 if (!addr) { 2299 pr_err("ERROR: Couldn't acquire reg(0) %pOFn\n", ciu_node); 2300 return -EINVAL; 2301 } 2302 host_data->raw_reg = (u64)phys_to_virt( 2303 of_translate_address(ciu_node, addr)); 2304 2305 addr = of_get_address(ciu_node, 1, NULL, NULL); 2306 if (!addr) { 2307 pr_err("ERROR: Couldn't acquire reg(1) %pOFn\n", ciu_node); 2308 return -EINVAL; 2309 } 2310 host_data->en_reg = (u64)phys_to_virt( 2311 of_translate_address(ciu_node, addr)); 2312 2313 r = of_property_read_u32(ciu_node, "cavium,max-bits", &val); 2314 if (r) { 2315 pr_err("ERROR: Couldn't read cavium,max-bits from %pOFn\n", 2316 ciu_node); 2317 return r; 2318 } 2319 host_data->max_bits = val; 2320 2321 cib_domain = irq_domain_add_linear(ciu_node, host_data->max_bits, 2322 &octeon_irq_domain_cib_ops, 2323 host_data); 2324 if (!cib_domain) { 2325 pr_err("ERROR: Couldn't irq_domain_add_linear()\n"); 2326 return -ENOMEM; 2327 } 2328 2329 cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */ 2330 cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */ 2331 2332 r = request_irq(parent_irq, octeon_irq_cib_handler, 2333 IRQF_NO_THREAD, "cib", cib_domain); 2334 if (r) { 2335 pr_err("request_irq cib failed %d\n", r); 2336 return r; 2337 } 2338 pr_info("CIB interrupt controller probed: %llx %d\n", 2339 host_data->raw_reg, host_data->max_bits); 2340 return 0; 2341} 2342 2343int octeon_irq_ciu3_xlat(struct irq_domain *d, 2344 struct device_node *node, 2345 const u32 *intspec, 2346 unsigned int intsize, 2347 unsigned long *out_hwirq, 2348 unsigned int *out_type) 2349{ 2350 struct octeon_ciu3_info *ciu3_info = d->host_data; 2351 unsigned int hwirq, type, intsn_major; 2352 union cvmx_ciu3_iscx_ctl isc; 2353 2354 if (intsize < 2) 2355 return -EINVAL; 2356 hwirq = intspec[0]; 2357 type = intspec[1]; 2358 2359 if (hwirq >= (1 << 20)) 2360 return -EINVAL; 2361 2362 intsn_major = hwirq >> 12; 2363 switch (intsn_major) { 2364 case 0x04: /* Software handled separately. */ 2365 return -EINVAL; 2366 default: 2367 break; 2368 } 2369 2370 isc.u64 = cvmx_read_csr(ciu3_info->ciu3_addr + CIU3_ISC_CTL(hwirq)); 2371 if (!isc.s.imp) 2372 return -EINVAL; 2373 2374 switch (type) { 2375 case 4: /* official value for level triggering. */ 2376 *out_type = IRQ_TYPE_LEVEL_HIGH; 2377 break; 2378 case 0: /* unofficial value, but we might as well let it work. */ 2379 case 1: /* official value for edge triggering. */ 2380 *out_type = IRQ_TYPE_EDGE_RISING; 2381 break; 2382 default: /* Nothing else is acceptable. */ 2383 return -EINVAL; 2384 } 2385 2386 *out_hwirq = hwirq; 2387 2388 return 0; 2389} 2390 2391void octeon_irq_ciu3_enable(struct irq_data *data) 2392{ 2393 int cpu; 2394 union cvmx_ciu3_iscx_ctl isc_ctl; 2395 union cvmx_ciu3_iscx_w1c isc_w1c; 2396 u64 isc_ctl_addr; 2397 2398 struct octeon_ciu_chip_data *cd; 2399 2400 cpu = next_cpu_for_irq(data); 2401 2402 cd = irq_data_get_irq_chip_data(data); 2403 2404 isc_w1c.u64 = 0; 2405 isc_w1c.s.en = 1; 2406 cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64); 2407 2408 isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn); 2409 isc_ctl.u64 = 0; 2410 isc_ctl.s.en = 1; 2411 isc_ctl.s.idt = per_cpu(octeon_irq_ciu3_idt_ip2, cpu); 2412 cvmx_write_csr(isc_ctl_addr, isc_ctl.u64); 2413 cvmx_read_csr(isc_ctl_addr); 2414} 2415 2416void octeon_irq_ciu3_disable(struct irq_data *data) 2417{ 2418 u64 isc_ctl_addr; 2419 union cvmx_ciu3_iscx_w1c isc_w1c; 2420 2421 struct octeon_ciu_chip_data *cd; 2422 2423 cd = irq_data_get_irq_chip_data(data); 2424 2425 isc_w1c.u64 = 0; 2426 isc_w1c.s.en = 1; 2427 2428 isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn); 2429 cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64); 2430 cvmx_write_csr(isc_ctl_addr, 0); 2431 cvmx_read_csr(isc_ctl_addr); 2432} 2433 2434void octeon_irq_ciu3_ack(struct irq_data *data) 2435{ 2436 u64 isc_w1c_addr; 2437 union cvmx_ciu3_iscx_w1c isc_w1c; 2438 struct octeon_ciu_chip_data *cd; 2439 u32 trigger_type = irqd_get_trigger_type(data); 2440 2441 /* 2442 * We use a single irq_chip, so we have to do nothing to ack a 2443 * level interrupt. 2444 */ 2445 if (!(trigger_type & IRQ_TYPE_EDGE_BOTH)) 2446 return; 2447 2448 cd = irq_data_get_irq_chip_data(data); 2449 2450 isc_w1c.u64 = 0; 2451 isc_w1c.s.raw = 1; 2452 2453 isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn); 2454 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); 2455 cvmx_read_csr(isc_w1c_addr); 2456} 2457 2458void octeon_irq_ciu3_mask(struct irq_data *data) 2459{ 2460 union cvmx_ciu3_iscx_w1c isc_w1c; 2461 u64 isc_w1c_addr; 2462 struct octeon_ciu_chip_data *cd; 2463 2464 cd = irq_data_get_irq_chip_data(data); 2465 2466 isc_w1c.u64 = 0; 2467 isc_w1c.s.en = 1; 2468 2469 isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn); 2470 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); 2471 cvmx_read_csr(isc_w1c_addr); 2472} 2473 2474void octeon_irq_ciu3_mask_ack(struct irq_data *data) 2475{ 2476 union cvmx_ciu3_iscx_w1c isc_w1c; 2477 u64 isc_w1c_addr; 2478 struct octeon_ciu_chip_data *cd; 2479 u32 trigger_type = irqd_get_trigger_type(data); 2480 2481 cd = irq_data_get_irq_chip_data(data); 2482 2483 isc_w1c.u64 = 0; 2484 isc_w1c.s.en = 1; 2485 2486 /* 2487 * We use a single irq_chip, so only ack an edge (!level) 2488 * interrupt. 2489 */ 2490 if (trigger_type & IRQ_TYPE_EDGE_BOTH) 2491 isc_w1c.s.raw = 1; 2492 2493 isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn); 2494 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); 2495 cvmx_read_csr(isc_w1c_addr); 2496} 2497 2498#ifdef CONFIG_SMP 2499static int octeon_irq_ciu3_set_affinity(struct irq_data *data, 2500 const struct cpumask *dest, bool force) 2501{ 2502 union cvmx_ciu3_iscx_ctl isc_ctl; 2503 union cvmx_ciu3_iscx_w1c isc_w1c; 2504 u64 isc_ctl_addr; 2505 int cpu; 2506 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); 2507 struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data); 2508 2509 if (!cpumask_subset(dest, cpumask_of_node(cd->ciu_node))) 2510 return -EINVAL; 2511 2512 if (!enable_one) 2513 return IRQ_SET_MASK_OK; 2514 2515 cd = irq_data_get_irq_chip_data(data); 2516 cpu = cpumask_first(dest); 2517 if (cpu >= nr_cpu_ids) 2518 cpu = smp_processor_id(); 2519 cd->current_cpu = cpu; 2520 2521 isc_w1c.u64 = 0; 2522 isc_w1c.s.en = 1; 2523 cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64); 2524 2525 isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn); 2526 isc_ctl.u64 = 0; 2527 isc_ctl.s.en = 1; 2528 isc_ctl.s.idt = per_cpu(octeon_irq_ciu3_idt_ip2, cpu); 2529 cvmx_write_csr(isc_ctl_addr, isc_ctl.u64); 2530 cvmx_read_csr(isc_ctl_addr); 2531 2532 return IRQ_SET_MASK_OK; 2533} 2534#endif 2535 2536static struct irq_chip octeon_irq_chip_ciu3 = { 2537 .name = "CIU3", 2538 .irq_startup = edge_startup, 2539 .irq_enable = octeon_irq_ciu3_enable, 2540 .irq_disable = octeon_irq_ciu3_disable, 2541 .irq_ack = octeon_irq_ciu3_ack, 2542 .irq_mask = octeon_irq_ciu3_mask, 2543 .irq_mask_ack = octeon_irq_ciu3_mask_ack, 2544 .irq_unmask = octeon_irq_ciu3_enable, 2545 .irq_set_type = octeon_irq_ciu_set_type, 2546#ifdef CONFIG_SMP 2547 .irq_set_affinity = octeon_irq_ciu3_set_affinity, 2548 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 2549#endif 2550}; 2551 2552int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq, 2553 irq_hw_number_t hw, struct irq_chip *chip) 2554{ 2555 struct octeon_ciu3_info *ciu3_info = d->host_data; 2556 struct octeon_ciu_chip_data *cd = kzalloc_node(sizeof(*cd), GFP_KERNEL, 2557 ciu3_info->node); 2558 if (!cd) 2559 return -ENOMEM; 2560 cd->intsn = hw; 2561 cd->current_cpu = -1; 2562 cd->ciu3_addr = ciu3_info->ciu3_addr; 2563 cd->ciu_node = ciu3_info->node; 2564 irq_set_chip_and_handler(virq, chip, handle_edge_irq); 2565 irq_set_chip_data(virq, cd); 2566 2567 return 0; 2568} 2569 2570static int octeon_irq_ciu3_map(struct irq_domain *d, 2571 unsigned int virq, irq_hw_number_t hw) 2572{ 2573 return octeon_irq_ciu3_mapx(d, virq, hw, &octeon_irq_chip_ciu3); 2574} 2575 2576static struct irq_domain_ops octeon_dflt_domain_ciu3_ops = { 2577 .map = octeon_irq_ciu3_map, 2578 .unmap = octeon_irq_free_cd, 2579 .xlate = octeon_irq_ciu3_xlat, 2580}; 2581 2582static void octeon_irq_ciu3_ip2(void) 2583{ 2584 union cvmx_ciu3_destx_pp_int dest_pp_int; 2585 struct octeon_ciu3_info *ciu3_info; 2586 u64 ciu3_addr; 2587 2588 ciu3_info = __this_cpu_read(octeon_ciu3_info); 2589 ciu3_addr = ciu3_info->ciu3_addr; 2590 2591 dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(3 * cvmx_get_local_core_num())); 2592 2593 if (likely(dest_pp_int.s.intr)) { 2594 irq_hw_number_t intsn = dest_pp_int.s.intsn; 2595 irq_hw_number_t hw; 2596 struct irq_domain *domain; 2597 /* Get the domain to use from the major block */ 2598 int block = intsn >> 12; 2599 int ret; 2600 2601 domain = ciu3_info->domain[block]; 2602 if (ciu3_info->intsn2hw[block]) 2603 hw = ciu3_info->intsn2hw[block](domain, intsn); 2604 else 2605 hw = intsn; 2606 2607 ret = handle_domain_irq(domain, hw, NULL); 2608 if (ret < 0) { 2609 union cvmx_ciu3_iscx_w1c isc_w1c; 2610 u64 isc_w1c_addr = ciu3_addr + CIU3_ISC_W1C(intsn); 2611 2612 isc_w1c.u64 = 0; 2613 isc_w1c.s.en = 1; 2614 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); 2615 cvmx_read_csr(isc_w1c_addr); 2616 spurious_interrupt(); 2617 } 2618 } else { 2619 spurious_interrupt(); 2620 } 2621} 2622 2623/* 2624 * 10 mbox per core starting from zero. 2625 * Base mbox is core * 10 2626 */ 2627static unsigned int octeon_irq_ciu3_base_mbox_intsn(int core) 2628{ 2629 /* SW (mbox) are 0x04 in bits 12..19 */ 2630 return 0x04000 + CIU3_MBOX_PER_CORE * core; 2631} 2632 2633static unsigned int octeon_irq_ciu3_mbox_intsn_for_core(int core, unsigned int mbox) 2634{ 2635 return octeon_irq_ciu3_base_mbox_intsn(core) + mbox; 2636} 2637 2638static unsigned int octeon_irq_ciu3_mbox_intsn_for_cpu(int cpu, unsigned int mbox) 2639{ 2640 int local_core = octeon_coreid_for_cpu(cpu) & 0x3f; 2641 2642 return octeon_irq_ciu3_mbox_intsn_for_core(local_core, mbox); 2643} 2644 2645static void octeon_irq_ciu3_mbox(void) 2646{ 2647 union cvmx_ciu3_destx_pp_int dest_pp_int; 2648 struct octeon_ciu3_info *ciu3_info; 2649 u64 ciu3_addr; 2650 int core = cvmx_get_local_core_num(); 2651 2652 ciu3_info = __this_cpu_read(octeon_ciu3_info); 2653 ciu3_addr = ciu3_info->ciu3_addr; 2654 2655 dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(1 + 3 * core)); 2656 2657 if (likely(dest_pp_int.s.intr)) { 2658 irq_hw_number_t intsn = dest_pp_int.s.intsn; 2659 int mbox = intsn - octeon_irq_ciu3_base_mbox_intsn(core); 2660 2661 if (likely(mbox >= 0 && mbox < CIU3_MBOX_PER_CORE)) { 2662 do_IRQ(mbox + OCTEON_IRQ_MBOX0); 2663 } else { 2664 union cvmx_ciu3_iscx_w1c isc_w1c; 2665 u64 isc_w1c_addr = ciu3_addr + CIU3_ISC_W1C(intsn); 2666 2667 isc_w1c.u64 = 0; 2668 isc_w1c.s.en = 1; 2669 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); 2670 cvmx_read_csr(isc_w1c_addr); 2671 spurious_interrupt(); 2672 } 2673 } else { 2674 spurious_interrupt(); 2675 } 2676} 2677 2678void octeon_ciu3_mbox_send(int cpu, unsigned int mbox) 2679{ 2680 struct octeon_ciu3_info *ciu3_info; 2681 unsigned int intsn; 2682 union cvmx_ciu3_iscx_w1s isc_w1s; 2683 u64 isc_w1s_addr; 2684 2685 if (WARN_ON_ONCE(mbox >= CIU3_MBOX_PER_CORE)) 2686 return; 2687 2688 intsn = octeon_irq_ciu3_mbox_intsn_for_cpu(cpu, mbox); 2689 ciu3_info = per_cpu(octeon_ciu3_info, cpu); 2690 isc_w1s_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1S(intsn); 2691 2692 isc_w1s.u64 = 0; 2693 isc_w1s.s.raw = 1; 2694 2695 cvmx_write_csr(isc_w1s_addr, isc_w1s.u64); 2696 cvmx_read_csr(isc_w1s_addr); 2697} 2698 2699static void octeon_irq_ciu3_mbox_set_enable(struct irq_data *data, int cpu, bool en) 2700{ 2701 struct octeon_ciu3_info *ciu3_info; 2702 unsigned int intsn; 2703 u64 isc_ctl_addr, isc_w1c_addr; 2704 union cvmx_ciu3_iscx_ctl isc_ctl; 2705 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0; 2706 2707 intsn = octeon_irq_ciu3_mbox_intsn_for_cpu(cpu, mbox); 2708 ciu3_info = per_cpu(octeon_ciu3_info, cpu); 2709 isc_w1c_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1C(intsn); 2710 isc_ctl_addr = ciu3_info->ciu3_addr + CIU3_ISC_CTL(intsn); 2711 2712 isc_ctl.u64 = 0; 2713 isc_ctl.s.en = 1; 2714 2715 cvmx_write_csr(isc_w1c_addr, isc_ctl.u64); 2716 cvmx_write_csr(isc_ctl_addr, 0); 2717 if (en) { 2718 unsigned int idt = per_cpu(octeon_irq_ciu3_idt_ip3, cpu); 2719 2720 isc_ctl.u64 = 0; 2721 isc_ctl.s.en = 1; 2722 isc_ctl.s.idt = idt; 2723 cvmx_write_csr(isc_ctl_addr, isc_ctl.u64); 2724 } 2725 cvmx_read_csr(isc_ctl_addr); 2726} 2727 2728static void octeon_irq_ciu3_mbox_enable(struct irq_data *data) 2729{ 2730 int cpu; 2731 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0; 2732 2733 WARN_ON(mbox >= CIU3_MBOX_PER_CORE); 2734 2735 for_each_online_cpu(cpu) 2736 octeon_irq_ciu3_mbox_set_enable(data, cpu, true); 2737} 2738 2739static void octeon_irq_ciu3_mbox_disable(struct irq_data *data) 2740{ 2741 int cpu; 2742 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0; 2743 2744 WARN_ON(mbox >= CIU3_MBOX_PER_CORE); 2745 2746 for_each_online_cpu(cpu) 2747 octeon_irq_ciu3_mbox_set_enable(data, cpu, false); 2748} 2749 2750static void octeon_irq_ciu3_mbox_ack(struct irq_data *data) 2751{ 2752 struct octeon_ciu3_info *ciu3_info; 2753 unsigned int intsn; 2754 u64 isc_w1c_addr; 2755 union cvmx_ciu3_iscx_w1c isc_w1c; 2756 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0; 2757 2758 intsn = octeon_irq_ciu3_mbox_intsn_for_core(cvmx_get_local_core_num(), mbox); 2759 2760 isc_w1c.u64 = 0; 2761 isc_w1c.s.raw = 1; 2762 2763 ciu3_info = __this_cpu_read(octeon_ciu3_info); 2764 isc_w1c_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1C(intsn); 2765 cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); 2766 cvmx_read_csr(isc_w1c_addr); 2767} 2768 2769static void octeon_irq_ciu3_mbox_cpu_online(struct irq_data *data) 2770{ 2771 octeon_irq_ciu3_mbox_set_enable(data, smp_processor_id(), true); 2772} 2773 2774static void octeon_irq_ciu3_mbox_cpu_offline(struct irq_data *data) 2775{ 2776 octeon_irq_ciu3_mbox_set_enable(data, smp_processor_id(), false); 2777} 2778 2779static int octeon_irq_ciu3_alloc_resources(struct octeon_ciu3_info *ciu3_info) 2780{ 2781 u64 b = ciu3_info->ciu3_addr; 2782 int idt_ip2, idt_ip3, idt_ip4; 2783 int unused_idt2; 2784 int core = cvmx_get_local_core_num(); 2785 int i; 2786 2787 __this_cpu_write(octeon_ciu3_info, ciu3_info); 2788 2789 /* 2790 * 4 idt per core starting from 1 because zero is reserved. 2791 * Base idt per core is 4 * core + 1 2792 */ 2793 idt_ip2 = core * 4 + 1; 2794 idt_ip3 = core * 4 + 2; 2795 idt_ip4 = core * 4 + 3; 2796 unused_idt2 = core * 4 + 4; 2797 __this_cpu_write(octeon_irq_ciu3_idt_ip2, idt_ip2); 2798 __this_cpu_write(octeon_irq_ciu3_idt_ip3, idt_ip3); 2799 2800 /* ip2 interrupts for this CPU */ 2801 cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip2), 0); 2802 cvmx_write_csr(b + CIU3_IDT_PP(idt_ip2, 0), 1ull << core); 2803 cvmx_write_csr(b + CIU3_IDT_IO(idt_ip2), 0); 2804 2805 /* ip3 interrupts for this CPU */ 2806 cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip3), 1); 2807 cvmx_write_csr(b + CIU3_IDT_PP(idt_ip3, 0), 1ull << core); 2808 cvmx_write_csr(b + CIU3_IDT_IO(idt_ip3), 0); 2809 2810 /* ip4 interrupts for this CPU */ 2811 cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip4), 2); 2812 cvmx_write_csr(b + CIU3_IDT_PP(idt_ip4, 0), 0); 2813 cvmx_write_csr(b + CIU3_IDT_IO(idt_ip4), 0); 2814 2815 cvmx_write_csr(b + CIU3_IDT_CTL(unused_idt2), 0); 2816 cvmx_write_csr(b + CIU3_IDT_PP(unused_idt2, 0), 0); 2817 cvmx_write_csr(b + CIU3_IDT_IO(unused_idt2), 0); 2818 2819 for (i = 0; i < CIU3_MBOX_PER_CORE; i++) { 2820 unsigned int intsn = octeon_irq_ciu3_mbox_intsn_for_core(core, i); 2821 2822 cvmx_write_csr(b + CIU3_ISC_W1C(intsn), 2); 2823 cvmx_write_csr(b + CIU3_ISC_CTL(intsn), 0); 2824 } 2825 2826 return 0; 2827} 2828 2829static void octeon_irq_setup_secondary_ciu3(void) 2830{ 2831 struct octeon_ciu3_info *ciu3_info; 2832 2833 ciu3_info = octeon_ciu3_info_per_node[cvmx_get_node_num()]; 2834 octeon_irq_ciu3_alloc_resources(ciu3_info); 2835 irq_cpu_online(); 2836 2837 /* Enable the CIU lines */ 2838 set_c0_status(STATUSF_IP3 | STATUSF_IP2); 2839 if (octeon_irq_use_ip4) 2840 set_c0_status(STATUSF_IP4); 2841 else 2842 clear_c0_status(STATUSF_IP4); 2843} 2844 2845static struct irq_chip octeon_irq_chip_ciu3_mbox = { 2846 .name = "CIU3-M", 2847 .irq_enable = octeon_irq_ciu3_mbox_enable, 2848 .irq_disable = octeon_irq_ciu3_mbox_disable, 2849 .irq_ack = octeon_irq_ciu3_mbox_ack, 2850 2851 .irq_cpu_online = octeon_irq_ciu3_mbox_cpu_online, 2852 .irq_cpu_offline = octeon_irq_ciu3_mbox_cpu_offline, 2853 .flags = IRQCHIP_ONOFFLINE_ENABLED, 2854}; 2855 2856static int __init octeon_irq_init_ciu3(struct device_node *ciu_node, 2857 struct device_node *parent) 2858{ 2859 int i; 2860 int node; 2861 struct irq_domain *domain; 2862 struct octeon_ciu3_info *ciu3_info; 2863 const __be32 *zero_addr; 2864 u64 base_addr; 2865 union cvmx_ciu3_const consts; 2866 2867 node = 0; /* of_node_to_nid(ciu_node); */ 2868 ciu3_info = kzalloc_node(sizeof(*ciu3_info), GFP_KERNEL, node); 2869 2870 if (!ciu3_info) 2871 return -ENOMEM; 2872 2873 zero_addr = of_get_address(ciu_node, 0, NULL, NULL); 2874 if (WARN_ON(!zero_addr)) 2875 return -EINVAL; 2876 2877 base_addr = of_translate_address(ciu_node, zero_addr); 2878 base_addr = (u64)phys_to_virt(base_addr); 2879 2880 ciu3_info->ciu3_addr = base_addr; 2881 ciu3_info->node = node; 2882 2883 consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST); 2884 2885 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu3; 2886 2887 octeon_irq_ip2 = octeon_irq_ciu3_ip2; 2888 octeon_irq_ip3 = octeon_irq_ciu3_mbox; 2889 octeon_irq_ip4 = octeon_irq_ip4_mask; 2890 2891 if (node == cvmx_get_node_num()) { 2892 /* Mips internal */ 2893 octeon_irq_init_core(); 2894 2895 /* Only do per CPU things if it is the CIU of the boot node. */ 2896 i = irq_alloc_descs_from(OCTEON_IRQ_MBOX0, 8, node); 2897 WARN_ON(i < 0); 2898 2899 for (i = 0; i < 8; i++) 2900 irq_set_chip_and_handler(i + OCTEON_IRQ_MBOX0, 2901 &octeon_irq_chip_ciu3_mbox, handle_percpu_irq); 2902 } 2903 2904 /* 2905 * Initialize all domains to use the default domain. Specific major 2906 * blocks will overwrite the default domain as needed. 2907 */ 2908 domain = irq_domain_add_tree(ciu_node, &octeon_dflt_domain_ciu3_ops, 2909 ciu3_info); 2910 for (i = 0; i < MAX_CIU3_DOMAINS; i++) 2911 ciu3_info->domain[i] = domain; 2912 2913 octeon_ciu3_info_per_node[node] = ciu3_info; 2914 2915 if (node == cvmx_get_node_num()) { 2916 /* Only do per CPU things if it is the CIU of the boot node. */ 2917 octeon_irq_ciu3_alloc_resources(ciu3_info); 2918 if (node == 0) 2919 irq_set_default_host(domain); 2920 2921 octeon_irq_use_ip4 = false; 2922 /* Enable the CIU lines */ 2923 set_c0_status(STATUSF_IP2 | STATUSF_IP3); 2924 clear_c0_status(STATUSF_IP4); 2925 } 2926 2927 return 0; 2928} 2929 2930static struct of_device_id ciu_types[] __initdata = { 2931 {.compatible = "cavium,octeon-3860-ciu", .data = octeon_irq_init_ciu}, 2932 {.compatible = "cavium,octeon-3860-gpio", .data = octeon_irq_init_gpio}, 2933 {.compatible = "cavium,octeon-6880-ciu2", .data = octeon_irq_init_ciu2}, 2934 {.compatible = "cavium,octeon-7890-ciu3", .data = octeon_irq_init_ciu3}, 2935 {.compatible = "cavium,octeon-7130-cib", .data = octeon_irq_init_cib}, 2936 {} 2937}; 2938 2939void __init arch_init_irq(void) 2940{ 2941#ifdef CONFIG_SMP 2942 /* Set the default affinity to the boot cpu. */ 2943 cpumask_clear(irq_default_affinity); 2944 cpumask_set_cpu(smp_processor_id(), irq_default_affinity); 2945#endif 2946 of_irq_init(ciu_types); 2947} 2948 2949asmlinkage void plat_irq_dispatch(void) 2950{ 2951 unsigned long cop0_cause; 2952 unsigned long cop0_status; 2953 2954 while (1) { 2955 cop0_cause = read_c0_cause(); 2956 cop0_status = read_c0_status(); 2957 cop0_cause &= cop0_status; 2958 cop0_cause &= ST0_IM; 2959 2960 if (cop0_cause & STATUSF_IP2) 2961 octeon_irq_ip2(); 2962 else if (cop0_cause & STATUSF_IP3) 2963 octeon_irq_ip3(); 2964 else if (cop0_cause & STATUSF_IP4) 2965 octeon_irq_ip4(); 2966 else if (cop0_cause) 2967 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); 2968 else 2969 break; 2970 } 2971} 2972 2973#ifdef CONFIG_HOTPLUG_CPU 2974 2975void octeon_fixup_irqs(void) 2976{ 2977 irq_cpu_offline(); 2978} 2979 2980#endif /* CONFIG_HOTPLUG_CPU */ 2981 2982struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block) 2983{ 2984 struct octeon_ciu3_info *ciu3_info; 2985 2986 ciu3_info = octeon_ciu3_info_per_node[node & CVMX_NODE_MASK]; 2987 return ciu3_info->domain[block]; 2988} 2989EXPORT_SYMBOL(octeon_irq_get_block_domain); 2990