18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
28c2ecf20Sopenharmony_ci/dts-v1/;
38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_ci#include <dt-bindings/interrupt-controller/irq.h>
58c2ecf20Sopenharmony_ci#include <dt-bindings/interrupt-controller/mips-gic.h>
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci/memreserve/ 0x00000000 0x00001000;	/* YAMON exception vectors */
88c2ecf20Sopenharmony_ci/memreserve/ 0x00001000 0x000ef000;	/* YAMON */
98c2ecf20Sopenharmony_ci/memreserve/ 0x000f0000 0x00010000;	/* PIIX4 ISA memory */
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci/ {
128c2ecf20Sopenharmony_ci	#address-cells = <1>;
138c2ecf20Sopenharmony_ci	#size-cells = <1>;
148c2ecf20Sopenharmony_ci	compatible = "mti,malta";
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci	cpu_intc: interrupt-controller {
178c2ecf20Sopenharmony_ci		compatible = "mti,cpu-interrupt-controller";
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci		interrupt-controller;
208c2ecf20Sopenharmony_ci		#interrupt-cells = <1>;
218c2ecf20Sopenharmony_ci	};
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci	gic: interrupt-controller@1bdc0000 {
248c2ecf20Sopenharmony_ci		compatible = "mti,gic";
258c2ecf20Sopenharmony_ci		reg = <0x1bdc0000 0x20000>;
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci		interrupt-controller;
288c2ecf20Sopenharmony_ci		#interrupt-cells = <3>;
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci		/*
318c2ecf20Sopenharmony_ci		 * Declare the interrupt-parent even though the mti,gic
328c2ecf20Sopenharmony_ci		 * binding doesn't require it, such that the kernel can
338c2ecf20Sopenharmony_ci		 * figure out that cpu_intc is the root interrupt
348c2ecf20Sopenharmony_ci		 * controller & should be probed first.
358c2ecf20Sopenharmony_ci		 */
368c2ecf20Sopenharmony_ci		interrupt-parent = <&cpu_intc>;
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ci		timer {
398c2ecf20Sopenharmony_ci			compatible = "mti,gic-timer";
408c2ecf20Sopenharmony_ci			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
418c2ecf20Sopenharmony_ci		};
428c2ecf20Sopenharmony_ci	};
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ci	i8259: interrupt-controller@20 {
458c2ecf20Sopenharmony_ci		compatible = "intel,i8259";
468c2ecf20Sopenharmony_ci
478c2ecf20Sopenharmony_ci		interrupt-controller;
488c2ecf20Sopenharmony_ci		#interrupt-cells = <1>;
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ci		interrupt-parent = <&gic>;
518c2ecf20Sopenharmony_ci		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
528c2ecf20Sopenharmony_ci	};
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci	flash@1e000000 {
558c2ecf20Sopenharmony_ci		compatible = "intel,dt28f160", "cfi-flash";
568c2ecf20Sopenharmony_ci		reg = <0x1e000000 0x400000>;
578c2ecf20Sopenharmony_ci		bank-width = <4>;
588c2ecf20Sopenharmony_ci		#address-cells = <1>;
598c2ecf20Sopenharmony_ci		#size-cells = <1>;
608c2ecf20Sopenharmony_ci
618c2ecf20Sopenharmony_ci		partitions {
628c2ecf20Sopenharmony_ci			compatible = "fixed-partitions";
638c2ecf20Sopenharmony_ci			#address-cells = <1>;
648c2ecf20Sopenharmony_ci			#size-cells = <1>;
658c2ecf20Sopenharmony_ci
668c2ecf20Sopenharmony_ci			yamon@0 {
678c2ecf20Sopenharmony_ci				label = "YAMON";
688c2ecf20Sopenharmony_ci				reg = <0x0 0x100000>;
698c2ecf20Sopenharmony_ci				read-only;
708c2ecf20Sopenharmony_ci			};
718c2ecf20Sopenharmony_ci
728c2ecf20Sopenharmony_ci			user-fs@100000 {
738c2ecf20Sopenharmony_ci				label = "User FS";
748c2ecf20Sopenharmony_ci				reg = <0x100000 0x2e0000>;
758c2ecf20Sopenharmony_ci			};
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_ci			board-config@3e0000 {
788c2ecf20Sopenharmony_ci				label = "Board Config";
798c2ecf20Sopenharmony_ci				reg = <0x3e0000 0x20000>;
808c2ecf20Sopenharmony_ci				read-only;
818c2ecf20Sopenharmony_ci			};
828c2ecf20Sopenharmony_ci		};
838c2ecf20Sopenharmony_ci	};
848c2ecf20Sopenharmony_ci
858c2ecf20Sopenharmony_ci	fpga_regs: system-controller@1f000000 {
868c2ecf20Sopenharmony_ci		compatible = "mti,malta-fpga", "syscon", "simple-mfd";
878c2ecf20Sopenharmony_ci		reg = <0x1f000000 0x1000>;
888c2ecf20Sopenharmony_ci		native-endian;
898c2ecf20Sopenharmony_ci
908c2ecf20Sopenharmony_ci		lcd@410 {
918c2ecf20Sopenharmony_ci			compatible = "mti,malta-lcd";
928c2ecf20Sopenharmony_ci			offset = <0x410>;
938c2ecf20Sopenharmony_ci		};
948c2ecf20Sopenharmony_ci
958c2ecf20Sopenharmony_ci		reboot {
968c2ecf20Sopenharmony_ci			compatible = "syscon-reboot";
978c2ecf20Sopenharmony_ci			regmap = <&fpga_regs>;
988c2ecf20Sopenharmony_ci			offset = <0x500>;
998c2ecf20Sopenharmony_ci			mask = <0x42>;
1008c2ecf20Sopenharmony_ci		};
1018c2ecf20Sopenharmony_ci	};
1028c2ecf20Sopenharmony_ci
1038c2ecf20Sopenharmony_ci	isa {
1048c2ecf20Sopenharmony_ci		compatible = "isa";
1058c2ecf20Sopenharmony_ci		#address-cells = <2>;
1068c2ecf20Sopenharmony_ci		#size-cells = <1>;
1078c2ecf20Sopenharmony_ci		ranges = <1 0 0 0x1000>;
1088c2ecf20Sopenharmony_ci
1098c2ecf20Sopenharmony_ci		rtc@70 {
1108c2ecf20Sopenharmony_ci			compatible = "motorola,mc146818";
1118c2ecf20Sopenharmony_ci			reg = <1 0x70 0x8>;
1128c2ecf20Sopenharmony_ci
1138c2ecf20Sopenharmony_ci			interrupt-parent = <&i8259>;
1148c2ecf20Sopenharmony_ci			interrupts = <8>;
1158c2ecf20Sopenharmony_ci		};
1168c2ecf20Sopenharmony_ci	};
1178c2ecf20Sopenharmony_ci};
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