1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. 7 * Copyright (C) 2006 FON Technology, SL. 8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org> 9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org> 10 * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com> 11 */ 12 13/* 14 * Platform devices for Atheros AR5312 SoCs 15 */ 16 17#include <linux/init.h> 18#include <linux/kernel.h> 19#include <linux/bitops.h> 20#include <linux/irqdomain.h> 21#include <linux/interrupt.h> 22#include <linux/memblock.h> 23#include <linux/platform_device.h> 24#include <linux/mtd/physmap.h> 25#include <linux/reboot.h> 26#include <asm/bootinfo.h> 27#include <asm/reboot.h> 28#include <asm/time.h> 29 30#include <ath25_platform.h> 31 32#include "devices.h" 33#include "ar5312.h" 34#include "ar5312_regs.h" 35 36static void __iomem *ar5312_rst_base; 37static struct irq_domain *ar5312_misc_irq_domain; 38 39static inline u32 ar5312_rst_reg_read(u32 reg) 40{ 41 return __raw_readl(ar5312_rst_base + reg); 42} 43 44static inline void ar5312_rst_reg_write(u32 reg, u32 val) 45{ 46 __raw_writel(val, ar5312_rst_base + reg); 47} 48 49static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val) 50{ 51 u32 ret = ar5312_rst_reg_read(reg); 52 53 ret &= ~mask; 54 ret |= val; 55 ar5312_rst_reg_write(reg, ret); 56} 57 58static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id) 59{ 60 u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1); 61 u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */ 62 u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1); 63 u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */ 64 65 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", 66 proc_addr, proc1, dma_addr, dma1); 67 68 machine_restart("AHB error"); /* Catastrophic failure */ 69 return IRQ_HANDLED; 70} 71 72static void ar5312_misc_irq_handler(struct irq_desc *desc) 73{ 74 u32 pending = ar5312_rst_reg_read(AR5312_ISR) & 75 ar5312_rst_reg_read(AR5312_IMR); 76 unsigned nr, misc_irq = 0; 77 78 if (pending) { 79 struct irq_domain *domain = irq_desc_get_handler_data(desc); 80 81 nr = __ffs(pending); 82 misc_irq = irq_find_mapping(domain, nr); 83 } 84 85 if (misc_irq) { 86 generic_handle_irq(misc_irq); 87 if (nr == AR5312_MISC_IRQ_TIMER) 88 ar5312_rst_reg_read(AR5312_TIMER); 89 } else { 90 spurious_interrupt(); 91 } 92} 93 94/* Enable the specified AR5312_MISC_IRQ interrupt */ 95static void ar5312_misc_irq_unmask(struct irq_data *d) 96{ 97 ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); 98} 99 100/* Disable the specified AR5312_MISC_IRQ interrupt */ 101static void ar5312_misc_irq_mask(struct irq_data *d) 102{ 103 ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); 104 ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */ 105} 106 107static struct irq_chip ar5312_misc_irq_chip = { 108 .name = "ar5312-misc", 109 .irq_unmask = ar5312_misc_irq_unmask, 110 .irq_mask = ar5312_misc_irq_mask, 111}; 112 113static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq, 114 irq_hw_number_t hw) 115{ 116 irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq); 117 return 0; 118} 119 120static struct irq_domain_ops ar5312_misc_irq_domain_ops = { 121 .map = ar5312_misc_irq_map, 122}; 123 124static void ar5312_irq_dispatch(void) 125{ 126 u32 pending = read_c0_status() & read_c0_cause(); 127 128 if (pending & CAUSEF_IP2) 129 do_IRQ(AR5312_IRQ_WLAN0); 130 else if (pending & CAUSEF_IP5) 131 do_IRQ(AR5312_IRQ_WLAN1); 132 else if (pending & CAUSEF_IP6) 133 do_IRQ(AR5312_IRQ_MISC); 134 else if (pending & CAUSEF_IP7) 135 do_IRQ(ATH25_IRQ_CPU_CLOCK); 136 else 137 spurious_interrupt(); 138} 139 140void __init ar5312_arch_init_irq(void) 141{ 142 struct irq_domain *domain; 143 unsigned irq; 144 145 ath25_irq_dispatch = ar5312_irq_dispatch; 146 147 domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT, 148 &ar5312_misc_irq_domain_ops, NULL); 149 if (!domain) 150 panic("Failed to add IRQ domain"); 151 152 irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC); 153 if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error", 154 NULL)) 155 pr_err("Failed to register ar5312-ahb-error interrupt\n"); 156 157 irq_set_chained_handler_and_data(AR5312_IRQ_MISC, 158 ar5312_misc_irq_handler, domain); 159 160 ar5312_misc_irq_domain = domain; 161} 162 163static struct physmap_flash_data ar5312_flash_data = { 164 .width = 2, 165}; 166 167static struct resource ar5312_flash_resource = { 168 .start = AR5312_FLASH_BASE, 169 .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1, 170 .flags = IORESOURCE_MEM, 171}; 172 173static struct platform_device ar5312_physmap_flash = { 174 .name = "physmap-flash", 175 .id = 0, 176 .dev.platform_data = &ar5312_flash_data, 177 .resource = &ar5312_flash_resource, 178 .num_resources = 1, 179}; 180 181static void __init ar5312_flash_init(void) 182{ 183 void __iomem *flashctl_base; 184 u32 ctl; 185 186 flashctl_base = ioremap(AR5312_FLASHCTL_BASE, 187 AR5312_FLASHCTL_SIZE); 188 189 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0); 190 ctl &= AR5312_FLASHCTL_MW; 191 192 /* fixup flash width */ 193 switch (ctl) { 194 case AR5312_FLASHCTL_MW16: 195 ar5312_flash_data.width = 2; 196 break; 197 case AR5312_FLASHCTL_MW8: 198 default: 199 ar5312_flash_data.width = 1; 200 break; 201 } 202 203 /* 204 * Configure flash bank 0. 205 * Assume 8M window size. Flash will be aliased if it's smaller 206 */ 207 ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE; 208 ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S; 209 ctl |= 0x07 << AR5312_FLASHCTL_WST1_S; 210 ctl |= 0x07 << AR5312_FLASHCTL_WST2_S; 211 __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0); 212 213 /* Disable other flash banks */ 214 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1); 215 ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC); 216 __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1); 217 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2); 218 ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC); 219 __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2); 220 221 iounmap(flashctl_base); 222} 223 224void __init ar5312_init_devices(void) 225{ 226 struct ath25_boarddata *config; 227 228 ar5312_flash_init(); 229 230 /* Locate board/radio config data */ 231 ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE); 232 config = ath25_board.config; 233 234 /* AR2313 has CPU minor rev. 10 */ 235 if ((current_cpu_data.processor_id & 0xff) == 0x0a) 236 ath25_soc = ATH25_SOC_AR2313; 237 238 /* AR2312 shares the same Silicon ID as AR5312 */ 239 else if (config->flags & BD_ISCASPER) 240 ath25_soc = ATH25_SOC_AR2312; 241 242 /* Everything else is probably AR5312 or compatible */ 243 else 244 ath25_soc = ATH25_SOC_AR5312; 245 246 platform_device_register(&ar5312_physmap_flash); 247 248 switch (ath25_soc) { 249 case ATH25_SOC_AR5312: 250 if (!ath25_board.radio) 251 return; 252 253 if (!(config->flags & BD_WLAN0)) 254 break; 255 256 ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0); 257 break; 258 case ATH25_SOC_AR2312: 259 case ATH25_SOC_AR2313: 260 if (!ath25_board.radio) 261 return; 262 break; 263 default: 264 break; 265 } 266 267 if (config->flags & BD_WLAN1) 268 ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1); 269} 270 271static void ar5312_restart(char *command) 272{ 273 /* reset the system */ 274 local_irq_disable(); 275 while (1) 276 ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM); 277} 278 279/* 280 * This table is indexed by bits 5..4 of the CLOCKCTL1 register 281 * to determine the predevisor value. 282 */ 283static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 }; 284 285static unsigned __init ar5312_cpu_frequency(void) 286{ 287 u32 scratch, devid, clock_ctl1; 288 u32 predivide_mask, multiplier_mask, doubler_mask; 289 unsigned predivide_shift, multiplier_shift; 290 unsigned predivide_select, predivisor, multiplier; 291 292 /* Trust the bootrom's idea of cpu frequency. */ 293 scratch = ar5312_rst_reg_read(AR5312_SCRATCH); 294 if (scratch) 295 return scratch; 296 297 devid = ar5312_rst_reg_read(AR5312_REV); 298 devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S; 299 if (devid == AR5312_REV_MAJ_AR2313) { 300 predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; 301 predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; 302 multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; 303 multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; 304 doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; 305 } else { /* AR5312 and AR2312 */ 306 predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; 307 predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; 308 multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; 309 multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; 310 doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; 311 } 312 313 /* 314 * Clocking is derived from a fixed 40MHz input clock. 315 * 316 * cpu_freq = input_clock * MULT (where MULT is PLL multiplier) 317 * sys_freq = cpu_freq / 4 (used for APB clock, serial, 318 * flash, Timer, Watchdog Timer) 319 * 320 * cnt_freq = cpu_freq / 2 (use for CPU count/compare) 321 * 322 * So, for example, with a PLL multiplier of 5, we have 323 * 324 * cpu_freq = 200MHz 325 * sys_freq = 50MHz 326 * cnt_freq = 100MHz 327 * 328 * We compute the CPU frequency, based on PLL settings. 329 */ 330 331 clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1); 332 predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift; 333 predivisor = clockctl1_predivide_table[predivide_select]; 334 multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift; 335 336 if (clock_ctl1 & doubler_mask) 337 multiplier <<= 1; 338 339 return (40000000 / predivisor) * multiplier; 340} 341 342static inline unsigned ar5312_sys_frequency(void) 343{ 344 return ar5312_cpu_frequency() / 4; 345} 346 347void __init ar5312_plat_time_init(void) 348{ 349 mips_hpt_frequency = ar5312_cpu_frequency() / 2; 350} 351 352void __init ar5312_plat_mem_setup(void) 353{ 354 void __iomem *sdram_base; 355 u32 memsize, memcfg, bank0_ac, bank1_ac; 356 u32 devid; 357 358 /* Detect memory size */ 359 sdram_base = ioremap(AR5312_SDRAMCTL_BASE, 360 AR5312_SDRAMCTL_SIZE); 361 memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1); 362 bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0); 363 bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1); 364 memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) + 365 (bank1_ac ? (1 << (bank1_ac + 1)) : 0); 366 memsize <<= 20; 367 memblock_add(0, memsize); 368 iounmap(sdram_base); 369 370 ar5312_rst_base = ioremap(AR5312_RST_BASE, AR5312_RST_SIZE); 371 372 devid = ar5312_rst_reg_read(AR5312_REV); 373 devid >>= AR5312_REV_WMAC_MIN_S; 374 devid &= AR5312_REV_CHIP; 375 ath25_board.devid = (u16)devid; 376 377 /* Clear any lingering AHB errors */ 378 ar5312_rst_reg_read(AR5312_PROCADDR); 379 ar5312_rst_reg_read(AR5312_DMAADDR); 380 ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE); 381 382 _machine_restart = ar5312_restart; 383} 384 385void __init ar5312_arch_init(void) 386{ 387 unsigned irq = irq_create_mapping(ar5312_misc_irq_domain, 388 AR5312_MISC_IRQ_UART0); 389 390 ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency()); 391} 392