1/*
2 *  Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 *	GPIOLIB support for Alchemy chips.
4 *
5 *  This program is free software; you can redistribute	 it and/or modify it
6 *  under  the terms of	 the GNU General  Public License as published by the
7 *  Free Software Foundation;  either version 2 of the	License, or (at your
8 *  option) any later version.
9 *
10 *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
11 *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
12 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
13 *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
14 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
16 *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
18 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 *  You should have received a copy of the  GNU General Public License along
22 *  with this program; if not, write  to the Free Software Foundation, Inc.,
23 *  675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *  Notes :
26 *	This file must ONLY be built when CONFIG_GPIOLIB=y and
27 *	 CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
28 *	au1000 SoC have only one GPIO block : GPIO1
29 *	Au1100, Au15x0, Au12x0 have a second one : GPIO2
30 *	Au1300 is totally different: 1 block with up to 128 GPIOs
31 */
32
33#include <linux/init.h>
34#include <linux/kernel.h>
35#include <linux/types.h>
36#include <linux/gpio.h>
37#include <asm/mach-au1x00/gpio-au1000.h>
38#include <asm/mach-au1x00/gpio-au1300.h>
39
40static int gpio2_get(struct gpio_chip *chip, unsigned offset)
41{
42	return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
43}
44
45static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
46{
47	alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
48}
49
50static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
51{
52	return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
53}
54
55static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
56				  int value)
57{
58	return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
59						value);
60}
61
62static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
63{
64	return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
65}
66
67
68static int gpio1_get(struct gpio_chip *chip, unsigned offset)
69{
70	return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
71}
72
73static void gpio1_set(struct gpio_chip *chip,
74				unsigned offset, int value)
75{
76	alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
77}
78
79static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
80{
81	return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
82}
83
84static int gpio1_direction_output(struct gpio_chip *chip,
85					unsigned offset, int value)
86{
87	return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
88					     value);
89}
90
91static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
92{
93	return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
94}
95
96struct gpio_chip alchemy_gpio_chip[] = {
97	[0] = {
98		.label			= "alchemy-gpio1",
99		.direction_input	= gpio1_direction_input,
100		.direction_output	= gpio1_direction_output,
101		.get			= gpio1_get,
102		.set			= gpio1_set,
103		.to_irq			= gpio1_to_irq,
104		.base			= ALCHEMY_GPIO1_BASE,
105		.ngpio			= ALCHEMY_GPIO1_NUM,
106	},
107	[1] = {
108		.label			= "alchemy-gpio2",
109		.direction_input	= gpio2_direction_input,
110		.direction_output	= gpio2_direction_output,
111		.get			= gpio2_get,
112		.set			= gpio2_set,
113		.to_irq			= gpio2_to_irq,
114		.base			= ALCHEMY_GPIO2_BASE,
115		.ngpio			= ALCHEMY_GPIO2_NUM,
116	},
117};
118
119static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
120{
121	return !!au1300_gpio_get_value(off + AU1300_GPIO_BASE);
122}
123
124static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
125{
126	au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
127}
128
129static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
130{
131	return au1300_gpio_direction_input(off + AU1300_GPIO_BASE);
132}
133
134static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off,
135				   int v)
136{
137	return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v);
138}
139
140static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off)
141{
142	return au1300_gpio_to_irq(off + AU1300_GPIO_BASE);
143}
144
145static struct gpio_chip au1300_gpiochip = {
146	.label			= "alchemy-gpic",
147	.direction_input	= alchemy_gpic_dir_input,
148	.direction_output	= alchemy_gpic_dir_output,
149	.get			= alchemy_gpic_get,
150	.set			= alchemy_gpic_set,
151	.to_irq			= alchemy_gpic_gpio_to_irq,
152	.base			= AU1300_GPIO_BASE,
153	.ngpio			= AU1300_GPIO_NUM,
154};
155
156static int __init alchemy_gpiochip_init(void)
157{
158	int ret = 0;
159
160	switch (alchemy_get_cputype()) {
161	case ALCHEMY_CPU_AU1000:
162		ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL);
163		break;
164	case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200:
165		ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL);
166		ret |= gpiochip_add_data(&alchemy_gpio_chip[1], NULL);
167		break;
168	case ALCHEMY_CPU_AU1300:
169		ret = gpiochip_add_data(&au1300_gpiochip, NULL);
170		break;
171	}
172	return ret;
173}
174arch_initcall(alchemy_gpiochip_init);
175