1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * BRIEF MODULE DESCRIPTION
4 *	MyCable XXS1500 board support
5 *
6 * Copyright 2003, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/platform_device.h>
14#include <linux/gpio.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <asm/bootinfo.h>
18#include <asm/reboot.h>
19#include <asm/setup.h>
20#include <asm/mach-au1x00/au1000.h>
21#include <asm/mach-au1x00/gpio-au1000.h>
22#include <prom.h>
23
24const char *get_system_type(void)
25{
26	return "XXS1500";
27}
28
29void prom_putchar(char c)
30{
31	alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
32}
33
34static void xxs1500_reset(char *c)
35{
36	/* Jump to the reset vector */
37	__asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000));
38}
39
40static void xxs1500_power_off(void)
41{
42	while (1)
43		asm volatile (
44		"	.set	mips32					\n"
45		"	wait						\n"
46		"	.set	mips0					\n");
47}
48
49void __init board_setup(void)
50{
51	u32 pin_func;
52
53	pm_power_off = xxs1500_power_off;
54	_machine_halt = xxs1500_power_off;
55	_machine_restart = xxs1500_reset;
56
57	alchemy_gpio1_input_enable();
58	alchemy_gpio2_enable();
59
60	/* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
61	pin_func  = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PF_UR3;
62	pin_func |= SYS_PF_UR3;
63	alchemy_wrsys(pin_func, AU1000_SYS_PINFUNC);
64
65	/* Enable UART */
66	alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
67	/* Enable DTR (MCR bit 0) = USB power up */
68	__raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
69	wmb();
70}
71
72/******************************************************************************/
73
74static struct resource xxs1500_pcmcia_res[] = {
75	{
76		.name	= "pcmcia-io",
77		.flags	= IORESOURCE_MEM,
78		.start	= AU1000_PCMCIA_IO_PHYS_ADDR,
79		.end	= AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
80	},
81	{
82		.name	= "pcmcia-attr",
83		.flags	= IORESOURCE_MEM,
84		.start	= AU1000_PCMCIA_ATTR_PHYS_ADDR,
85		.end	= AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
86	},
87	{
88		.name	= "pcmcia-mem",
89		.flags	= IORESOURCE_MEM,
90		.start	= AU1000_PCMCIA_MEM_PHYS_ADDR,
91		.end	= AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
92	},
93};
94
95static struct platform_device xxs1500_pcmcia_dev = {
96	.name		= "xxs1500_pcmcia",
97	.id		= -1,
98	.num_resources	= ARRAY_SIZE(xxs1500_pcmcia_res),
99	.resource	= xxs1500_pcmcia_res,
100};
101
102static struct platform_device *xxs1500_devs[] __initdata = {
103	&xxs1500_pcmcia_dev,
104};
105
106static int __init xxs1500_dev_init(void)
107{
108	irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH);
109	irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW);
110	irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW);
111	irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW);
112	irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
113	irq_set_irq_type(AU1500_GPIO207_INT, IRQ_TYPE_LEVEL_LOW);
114
115	irq_set_irq_type(AU1500_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
116	irq_set_irq_type(AU1500_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
117	irq_set_irq_type(AU1500_GPIO2_INT, IRQ_TYPE_LEVEL_LOW);
118	irq_set_irq_type(AU1500_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);
119	irq_set_irq_type(AU1500_GPIO4_INT, IRQ_TYPE_LEVEL_LOW); /* CF irq */
120	irq_set_irq_type(AU1500_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);
121
122	return platform_add_devices(xxs1500_devs,
123				    ARRAY_SIZE(xxs1500_devs));
124}
125device_initcall(xxs1500_dev_init);
126